From 22737612227193a40b8751df7a6bd8b2f447641e Mon Sep 17 00:00:00 2001
From: Guy Perfect <guytpk@gmail.com>
Date: Sun, 13 Oct 2024 16:31:18 -0500
Subject: [PATCH] Pre-bit-string adjustments

---
 core/cpu.c | 44 ++++++++++++++++++++------------------------
 1 file changed, 20 insertions(+), 24 deletions(-)

diff --git a/core/cpu.c b/core/cpu.c
index 0cf65ec..730c1a0 100644
--- a/core/cpu.c
+++ b/core/cpu.c
@@ -117,20 +117,6 @@
 #define CPU_XOR_BS  6
 #define CPU_XORN_BS 7
 
-/* Instruction code lengths by opcode */
-static const uint8_t INST_LENGTHS[] = {
-    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
-    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
-    1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2,
-    2, 2, 1, 2, 2, 2, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2
-};
-
-/* Highest interrupt level by IRQ bit mask value */
-static const int8_t IRQ_LEVELS[] = {
-    -1, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3,
-     4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4
-};
-
 
 
 /********************************** Macros ***********************************/
@@ -145,6 +131,20 @@ static const int8_t IRQ_LEVELS[] = {
 
 /******************************** Lookup Data ********************************/
 
+/* Instruction code lengths by opcode */
+static const uint8_t INST_LENGTHS[] = {
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2,
+    2, 2, 1, 2, 2, 2, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2
+};
+
+/* Highest interrupt level by IRQ bit mask value */
+static const int8_t IRQ_LEVELS[] = {
+    -1, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3,
+     4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4
+};
+
 /* Opdefs by opcode */
 static const uint8_t OPDEFS[] = {
     CPU_MOV_REG, CPU_ADD_REG, CPU_SUB      , CPU_CMP_REG  , /* 000000 */
@@ -407,7 +407,7 @@ static int cpuIRQ(VB *sim) {
     if (sim->cpu.psw.id | sim->cpu.psw.ep | sim->cpu.psw.np)
         return 0;
     level = IRQ_LEVELS[sim->cpu.irq];
-    if (level > sim->cpu.psw.i)
+    if (level == -1 || level > sim->cpu.psw.i)
         return 0;
     cpuThrow(sim, 0xFE00 | level << 4);
     return 1;
@@ -835,15 +835,7 @@ static int cpuST_OUT(VB *sim, int type) {
             }
 
             /* Update state */
-            sim->cpu.clocks += cpuClocks(1);
-
-            /* Wait for clocks taken */
-            sim->cpu.step = 2;
-            return 0;
-
-        case 2:
-            cpuSetReg2(sim, auxData.value);
-            cpuAdvance(sim, cpuClocks(3)); /* TODO: Research */
+            cpuAdvance(sim, cpuClocks(4)); /* TODO: Research */
     }
     return 0;
 }
@@ -1125,6 +1117,7 @@ static void cpuDIVU(VB *sim) {
 
 /* HALT */
 static void cpuHALT(VB *sim) {
+    sim->cpu.halt      = 1;
     sim->cpu.operation = CPU_HALTING;
     /* TODO: Research clocks */
 }
@@ -1309,6 +1302,7 @@ static void cpuREV(VB *sim) {
     x = (x <<  2 & 0xCCCCCCCC) | (x >>  2 & 0x33333333);
     x = (x <<  1 & 0xAAAAAAAA) | (x >>  1 & 0x55555555);
     cpuSetReg2(sim, x);
+    cpuAdvance(sim, cpuClocks(22));
 }
 
 /* SAR immediate */
@@ -1436,6 +1430,7 @@ static void cpuXB(VB *sim) {
     uint32_t x = cpuGetReg2(sim);
     x = (x & 0xFFFF0000) | (x << 8 & 0x0000FF00) | (x >> 8 & 0x000000FF);
     cpuSetReg2(sim, x);
+    cpuAdvance(sim, cpuClocks(6));
 }
 
 /* XH */
@@ -1443,6 +1438,7 @@ static void cpuXH(VB *sim) {
     uint32_t x = cpuGetReg2(sim);
     x = (x << 16 & 0xFFFF0000) | (x >> 16 & 0x0000FFFF);
     cpuSetReg2(sim, x);
+    cpuAdvance(sim, cpuClocks(1));
 }
 
 /* XOR */