diff --git a/core/bus.c b/core/bus.c index 3a25aa8..59fe586 100644 --- a/core/bus.c +++ b/core/bus.c @@ -112,7 +112,7 @@ static void busWriteBuffer( /***************************** Module Functions ******************************/ /* Read a typed value from the simulation bus */ -static int32_t busRead(VB *vb, uint32_t address, int type) { +static int32_t busRead(VB *sim, uint32_t address, int type) { /* Processing by address region */ switch (address >> 24 & 7) { @@ -122,11 +122,11 @@ static int32_t busRead(VB *vb, uint32_t address, int type) { case 3: return 0; /* Unmapped */ case 4: return 0; /* Game pak expansion */ case 5: return /* WRAM */ - busReadBuffer(vb->wram , 0x10000 , address, type); + busReadBuffer(sim->wram , 0x10000 , address, type); case 6: return /* Game pak RAM */ - busReadBuffer(vb->cart.ram, vb->cart.ramSize, address, type); + busReadBuffer(sim->cart.ram, sim->cart.ramSize, address, type); case 7: return /* Game pak ROM */ - busReadBuffer(vb->cart.rom, vb->cart.romSize, address, type); + busReadBuffer(sim->cart.rom, sim->cart.romSize, address, type); } /* Unreachable */ @@ -134,7 +134,7 @@ static int32_t busRead(VB *vb, uint32_t address, int type) { } /* Write a typed value to the simulation bus */ -static void busWrite(VB *vb,uint32_t address,int type,int32_t value,int debug){ +static void busWrite(VB*sim,uint32_t address,int type,int32_t value,int debug){ (void) debug; /* Processing by address region */ @@ -145,13 +145,13 @@ static void busWrite(VB *vb,uint32_t address,int type,int32_t value,int debug){ case 3: break; /* Unmapped */ case 4: break; /* Game pak expansion */ case 5: /* WRAM */ - busWriteBuffer(vb->wram ,0x10000 ,address,type,value); + busWriteBuffer(sim->wram ,0x10000 ,address,type,value); break; case 6: /* Game pak RAM */ - busWriteBuffer(vb->cart.ram,vb->cart.ramSize,address,type,value); + busWriteBuffer(sim->cart.ram,sim->cart.ramSize,address,type,value); break; case 7: /* Game pak ROM */ - busWriteBuffer(vb->cart.rom,vb->cart.romSize,address,type,value); + busWriteBuffer(sim->cart.rom,sim->cart.romSize,address,type,value); break; } diff --git a/core/cpu.c b/core/cpu.c index 441feb2..d560b32 100644 --- a/core/cpu.c +++ b/core/cpu.c @@ -43,18 +43,18 @@ typedef struct { /***************************** Utility Functions *****************************/ /* Check for an interrupt exception condition */ -static int cpuCheckIRQs(VB *vb) { +static int cpuCheckIRQs(VB *sim) { int x; /* Iterator */ /* Interrupts are masked */ - if (vb->cpu.psw.id || vb->cpu.psw.ep || vb->cpu.psw.np) + if (sim->cpu.psw.id || sim->cpu.psw.ep || sim->cpu.psw.np) return 0; /* Check for interrupt requests */ - for (x = 4; x >= vb->cpu.psw.i; x--) { - if (!vb->cpu.irq[x]) + for (x = 4; x >= sim->cpu.psw.i; x--) { + if (!sim->cpu.irq[x]) continue; - vb->cpu.exception = 0xFE00 | x << 4; + sim->cpu.exception = 0xFE00 | x << 4; return 1; } @@ -63,102 +63,102 @@ static int cpuCheckIRQs(VB *vb) { } /* Test a condition */ -static int cpuCondition(VB *vb, int index) { +static int cpuCondition(VB *sim, int index) { switch (index) { - case 0: return vb->cpu.psw.ov; /* V */ - case 1: return vb->cpu.psw.cy; /* C, L */ - case 2: return vb->cpu.psw.z; /* E, Z */ - case 3: return vb->cpu.psw.cy | vb->cpu.psw.z; /* NH */ - case 4: return vb->cpu.psw.s; /* N */ - case 5: return 1; /* T */ - case 6: return vb->cpu.psw.ov ^ vb->cpu.psw.s; /* LT */ - case 7: return (vb->cpu.psw.ov^vb->cpu.psw.s)|vb->cpu.psw.z; /* LE */ + case 0: return sim->cpu.psw.ov; /*V */ + case 1: return sim->cpu.psw.cy; /*C,L*/ + case 2: return sim->cpu.psw.z; /*E,Z*/ + case 3: return sim->cpu.psw.cy | sim->cpu.psw.z; /*NH */ + case 4: return sim->cpu.psw.s; /*N */ + case 5: return 1; /*T */ + case 6: return sim->cpu.psw.ov ^ sim->cpu.psw.s; /*LT */ + case 7: return (sim->cpu.psw.ov^sim->cpu.psw.s)|sim->cpu.psw.z;/*LE */ } - return !cpuCondition(vb, index - 8); + return !cpuCondition(sim, index - 8); } /* Retrieve the value of a system register */ -static uint32_t cpuGetSystemRegister(VB *vb, int id) { +static uint32_t cpuGetSystemRegister(VB *sim, int id) { switch (id) { - case VB_ADTRE: return vb->cpu.adtre; - case VB_EIPC : return vb->cpu.eipc; - case VB_EIPSW: return vb->cpu.eipsw; - case VB_FEPC : return vb->cpu.fepc; - case VB_FEPSW: return vb->cpu.fepsw; + case VB_ADTRE: return sim->cpu.adtre; + case VB_EIPC : return sim->cpu.eipc; + case VB_EIPSW: return sim->cpu.eipsw; + case VB_FEPC : return sim->cpu.fepc; + case VB_FEPSW: return sim->cpu.fepsw; case VB_PIR : return 0x00005346; case VB_TKCW : return 0x000000E0; - case 29 : return vb->cpu.sr29; + case 29 : return sim->cpu.sr29; case 30 : return 0x00000004; - case 31 : return vb->cpu.sr31; + case 31 : return sim->cpu.sr31; case VB_CHCW : return - (uint32_t) vb->cpu.chcw.ice << 1 + (uint32_t) sim->cpu.chcw.ice << 1 ; case VB_ECR : return - (uint32_t) vb->cpu.ecr.fecc << 16 | - (uint32_t) vb->cpu.ecr.eicc + (uint32_t) sim->cpu.ecr.fecc << 16 | + (uint32_t) sim->cpu.ecr.eicc ; case VB_PSW : return - (uint32_t) vb->cpu.psw.i << 16 | - (uint32_t) vb->cpu.psw.np << 15 | - (uint32_t) vb->cpu.psw.ep << 14 | - (uint32_t) vb->cpu.psw.ae << 13 | - (uint32_t) vb->cpu.psw.id << 12 | - (uint32_t) vb->cpu.psw.fro << 9 | - (uint32_t) vb->cpu.psw.fiv << 8 | - (uint32_t) vb->cpu.psw.fzd << 7 | - (uint32_t) vb->cpu.psw.fov << 6 | - (uint32_t) vb->cpu.psw.fud << 5 | - (uint32_t) vb->cpu.psw.fpr << 4 | - (uint32_t) vb->cpu.psw.cy << 3 | - (uint32_t) vb->cpu.psw.ov << 2 | - (uint32_t) vb->cpu.psw.s << 1 | - (uint32_t) vb->cpu.psw.z + (uint32_t) sim->cpu.psw.i << 16 | + (uint32_t) sim->cpu.psw.np << 15 | + (uint32_t) sim->cpu.psw.ep << 14 | + (uint32_t) sim->cpu.psw.ae << 13 | + (uint32_t) sim->cpu.psw.id << 12 | + (uint32_t) sim->cpu.psw.fro << 9 | + (uint32_t) sim->cpu.psw.fiv << 8 | + (uint32_t) sim->cpu.psw.fzd << 7 | + (uint32_t) sim->cpu.psw.fov << 6 | + (uint32_t) sim->cpu.psw.fud << 5 | + (uint32_t) sim->cpu.psw.fpr << 4 | + (uint32_t) sim->cpu.psw.cy << 3 | + (uint32_t) sim->cpu.psw.ov << 2 | + (uint32_t) sim->cpu.psw.s << 1 | + (uint32_t) sim->cpu.psw.z ; } return 0; /* Invalid ID */ } /* Read a memory value from the bus */ -static int cpuRead(VB *vb, uint32_t address, int type, int32_t *value) { +static int cpuRead(VB *sim, uint32_t address, int type, int32_t *value) { VBAccess access; /* Bus access descriptor */ /* Retrieve the value from the simulation state */ access.clocks = 0; /* TODO: Needs research */ - access.value = busRead(vb, address, type); + access.value = busRead(sim, address, type); /* Call the breakpoint handler */ - if (vb->onRead != NULL) { + if (sim->onRead != NULL) { access.address = address; access.type = type; - if (vb->onRead(vb, &access)) + if (sim->onRead(sim, &access)) return 1; } /* Post-processing */ - vb->cpu.clocks += access.clocks; + sim->cpu.clocks += access.clocks; *value = access.value; return 0; } /* Fetch an instruction code unit from the bus */ -static int cpuReadFetch(VB *vb) { +static int cpuReadFetch(VB *sim) { VBAccess access; /* Bus access descriptor */ /* Retrieve the value from the simulation state */ - access.address = vb->cpu.pc + (vb->cpu.step << 1); + access.address = sim->cpu.pc + (sim->cpu.step << 1); access.clocks = 0; /* TODO: Prefetch makes this tricky */ - access.value = busRead(vb, access.address, VB_U16); + access.value = busRead(sim, access.address, VB_U16); /* Call the breakpoint handler */ - if (vb->onFetch != NULL) { + if (sim->onFetch != NULL) { access.type = VB_U16; - if (vb->onFetch(vb, vb->cpu.step, &access)) + if (sim->onFetch(sim, sim->cpu.step, &access)) return 1; } /* Post-processing */ - vb->cpu.clocks += access.clocks; - vb->cpu.inst.code[vb->cpu.step++] = access.value; + sim->cpu.clocks += access.clocks; + sim->cpu.inst.code[sim->cpu.step++] = access.value; return 0; } @@ -171,66 +171,66 @@ static int cpuReadFetch(VB *vb) { ) /* Specify a value for a system register */ -static uint32_t cpuSetSystemRegister(VB *vb,int id,uint32_t value,int debug) { +static uint32_t cpuSetSystemRegister(VB *sim,int id,uint32_t value,int debug) { switch (id) { - case VB_ADTRE: return vb->cpu.adtre = value & 0xFFFFFFFE; - case VB_EIPC : return vb->cpu.eipc = value & 0xFFFFFFFE; - case VB_EIPSW: return vb->cpu.eipsw = value & 0x000FF3FF; - case VB_FEPC : return vb->cpu.fepc = value & 0xFFFFFFFE; - case VB_FEPSW: return vb->cpu.fepsw = value & 0x000FF3FF; + case VB_ADTRE: return sim->cpu.adtre = value & 0xFFFFFFFE; + case VB_EIPC : return sim->cpu.eipc = value & 0xFFFFFFFE; + case VB_EIPSW: return sim->cpu.eipsw = value & 0x000FF3FF; + case VB_FEPC : return sim->cpu.fepc = value & 0xFFFFFFFE; + case VB_FEPSW: return sim->cpu.fepsw = value & 0x000FF3FF; case VB_PIR : return 0x00005346; case VB_TKCW : return 0x000000E0; - case 29 : return vb->cpu.sr29 = value; + case 29 : return sim->cpu.sr29 = value; case 30 : return 0x00000004; case 31 : return - vb->cpu.sr31 = debug || value < (uint32_t) 0x80000000 ? + sim->cpu.sr31 = debug || value < (uint32_t) 0x80000000 ? value : (uint32_t) -(int32_t)value; case VB_CHCW: /* TODO: Manage cache functions */ - vb->cpu.chcw.ice = value >> 1 & 1; + sim->cpu.chcw.ice = value >> 1 & 1; return value & 0x00000002; case VB_ECR: if (debug) { - vb->cpu.ecr.fecc = value >> 16 & 0xFFFF; - vb->cpu.ecr.eicc = value & 0xFFFF; + sim->cpu.ecr.fecc = value >> 16 & 0xFFFF; + sim->cpu.ecr.eicc = value & 0xFFFF; } - return (uint32_t) vb->cpu.ecr.fecc << 16 | vb->cpu.ecr.eicc; + return (uint32_t) sim->cpu.ecr.fecc << 16 | sim->cpu.ecr.eicc; case VB_PSW: - vb->cpu.psw.i = value >> 16 & 15; - vb->cpu.psw.np = value >> 15 & 1; - vb->cpu.psw.ep = value >> 14 & 1; - vb->cpu.psw.ae = value >> 13 & 1; - vb->cpu.psw.id = value >> 12 & 1; - vb->cpu.psw.fro = value >> 9 & 1; - vb->cpu.psw.fiv = value >> 8 & 1; - vb->cpu.psw.fzd = value >> 7 & 1; - vb->cpu.psw.fov = value >> 6 & 1; - vb->cpu.psw.fud = value >> 5 & 1; - vb->cpu.psw.fpr = value >> 4 & 1; - vb->cpu.psw.cy = value >> 3 & 1; - vb->cpu.psw.ov = value >> 2 & 1; - vb->cpu.psw.s = value >> 1 & 1; - vb->cpu.psw.z = value & 1; + sim->cpu.psw.i = value >> 16 & 15; + sim->cpu.psw.np = value >> 15 & 1; + sim->cpu.psw.ep = value >> 14 & 1; + sim->cpu.psw.ae = value >> 13 & 1; + sim->cpu.psw.id = value >> 12 & 1; + sim->cpu.psw.fro = value >> 9 & 1; + sim->cpu.psw.fiv = value >> 8 & 1; + sim->cpu.psw.fzd = value >> 7 & 1; + sim->cpu.psw.fov = value >> 6 & 1; + sim->cpu.psw.fud = value >> 5 & 1; + sim->cpu.psw.fpr = value >> 4 & 1; + sim->cpu.psw.cy = value >> 3 & 1; + sim->cpu.psw.ov = value >> 2 & 1; + sim->cpu.psw.s = value >> 1 & 1; + sim->cpu.psw.z = value & 1; return value & 0x000FF3FF; } return 0; /* Invalid ID */ } /* Prepare to write a memory value to the bus */ -static int cpuWritePre(VB *vb,uint32_t *address,int32_t *type,int32_t *value) { +static int cpuWritePre(VB *sim,uint32_t *address,int32_t *type,int32_t *value){ VBAccess access; /* Bus access descriptor */ /* Determine how many clocks the access will take */ access.clocks = 0; /* TODO: Needs research */ /* Call the breakpoint handler */ - if (vb->onWrite != NULL) { + if (sim->onWrite != NULL) { /* Query the application */ access.address = *address; access.value = *value; access.type = *type; - if (vb->onWrite(vb, &access)) + if (sim->onWrite(sim, &access)) return 1; /* Apply changes */ @@ -241,7 +241,7 @@ static int cpuWritePre(VB *vb,uint32_t *address,int32_t *type,int32_t *value) { } /* Post-processing */ - vb->cpu.clocks += access.clocks; + sim->cpu.clocks += access.clocks; return 0; } @@ -250,24 +250,24 @@ static int cpuWritePre(VB *vb,uint32_t *address,int32_t *type,int32_t *value) { /**************************** Execute A Handlers *****************************/ /* Standard two-operand instruction */ -static int exaStdTwo(VB *vb) { - OpDef *def = (OpDef *) vb->cpu.inst.def; - vb->cpu.inst.aux[0] = def->operand(vb); - vb->cpu.clocks += def->aux; +static int exaStdTwo(VB *sim) { + OpDef *def = (OpDef *) sim->cpu.inst.def; + sim->cpu.inst.aux[0] = def->operand(sim); + sim->cpu.clocks += def->aux; return 0; } /* Standard three-operand instruction */ -static int exaStdThree(VB *vb) { - OpDef *def = (OpDef *) vb->cpu.inst.def; - vb->cpu.inst.aux[0] = def->operand(vb); - vb->cpu.inst.aux[1] = vb->cpu.program[vb->cpu.inst.code[0] & 31]; - vb->cpu.clocks += def->aux; +static int exaStdThree(VB *sim) { + OpDef *def = (OpDef *) sim->cpu.inst.def; + sim->cpu.inst.aux[0] = def->operand(sim); + sim->cpu.inst.aux[1] = sim->cpu.program[sim->cpu.inst.code[0] & 31]; + sim->cpu.clocks += def->aux; return 0; } /* Bit string bitwise */ -static int exaBitBitwise(VB *vb) { +static int exaBitBitwise(VB *sim) { int32_t bits; /* Working shift amount and bit mask */ uint32_t length; /* Number of bits remaining in bit string */ int32_t offDest; /* Bit offset of destination bit string */ @@ -276,40 +276,40 @@ static int exaBitBitwise(VB *vb) { uint32_t valDest; /* Destination word value */ /* Initial invocation */ - if (vb->cpu.step == 0) - vb->cpu.step = vb->cpu.bitstring + 1; + if (sim->cpu.step == 0) + sim->cpu.step = sim->cpu.bitstring + 1; /* Read the low-order 32 source bits */ - if (vb->cpu.step == 1) { - if (cpuRead(vb, vb->cpu.program[30], VB_S32, &vb->cpu.inst.aux[0])) + if (sim->cpu.step == 1) { + if (cpuRead(sim, sim->cpu.program[30], VB_S32, &sim->cpu.inst.aux[0])) return 1; - vb->cpu.clocks += 4; /* TODO: Needs research */ - vb->cpu.step = 2; + sim->cpu.clocks += 4; /* TODO: Needs research */ + sim->cpu.step = 2; } /* Read the high-order 32 source bits */ - if (vb->cpu.step == 2) { - if (cpuRead(vb, vb->cpu.program[30] + 4, VB_S32, &vb->cpu.inst.aux[1])) + if (sim->cpu.step == 2) { + if (cpuRead(sim,sim->cpu.program[30]+4,VB_S32,&sim->cpu.inst.aux[1])) return 1; - vb->cpu.clocks += 4; /* TODO: Needs research */ - vb->cpu.step = 3; + sim->cpu.clocks += 4; /* TODO: Needs research */ + sim->cpu.step = 3; } /* Read the destination bits */ - if (vb->cpu.step == 3) { - if (cpuRead(vb, vb->cpu.program[29], VB_S32, &vb->cpu.inst.aux[2])) + if (sim->cpu.step == 3) { + if (cpuRead(sim, sim->cpu.program[29], VB_S32, &sim->cpu.inst.aux[2])) return 1; - vb->cpu.clocks += 4; /* TODO: Needs research */ - vb->cpu.step = 4; + sim->cpu.clocks += 4; /* TODO: Needs research */ + sim->cpu.step = 4; } /* Compute the result */ - if (vb->cpu.step == 4) { - length = vb->cpu.program[28]; - offDest = vb->cpu.program[26] & 31; - offSrc = vb->cpu.program[27] & 31; - result = vb->cpu.inst.aux[0]; - valDest = vb->cpu.inst.aux[2]; + if (sim->cpu.step == 4) { + length = sim->cpu.program[28]; + offDest = sim->cpu.program[26] & 31; + offSrc = sim->cpu.program[27] & 31; + result = sim->cpu.inst.aux[0]; + valDest = sim->cpu.inst.aux[2]; bits = offDest - offSrc; /* Compose the source value */ @@ -320,75 +320,75 @@ static int exaBitBitwise(VB *vb) { #ifndef VB_SIGNED_PROPAGATE result &= ((uint32_t) 1 << (32 + bits)) - 1; #endif - result |= vb->cpu.inst.aux[1] << (32 + bits); + result |= sim->cpu.inst.aux[1] << (32 + bits); } /* Compose the destination value */ - ((OpDef *) vb->cpu.inst.def) - ->operation(vb, (int32_t *) &result, valDest); + ((OpDef *) sim->cpu.inst.def) + ->operation(sim, (int32_t *) &result, valDest); bits = (1 << offDest) - 1; if (length < 32 && offDest + length < 32) bits |= (uint32_t) 0xFFFFFFFF << (offDest + length); - vb->cpu.inst.aux[2] = (result & ~bits) | (valDest & bits); + sim->cpu.inst.aux[2] = (result & ~bits) | (valDest & bits); /* Prepare to write the result */ - vb->cpu.inst.aux[3] = vb->cpu.program[29] & 0xFFFFFFFC; - vb->cpu.inst.aux[4] = VB_S32; - if (cpuWritePre(vb, (uint32_t *) &vb->cpu.inst.aux[3], - &vb->cpu.inst.aux[4], &vb->cpu.inst.aux[2])) + sim->cpu.inst.aux[3] = sim->cpu.program[29] & 0xFFFFFFFC; + sim->cpu.inst.aux[4] = VB_S32; + if (cpuWritePre(sim, (uint32_t *) &sim->cpu.inst.aux[3], + &sim->cpu.inst.aux[4], &sim->cpu.inst.aux[2])) return 1; - vb->cpu.clocks += 4; /* TODO: Needs research */ + sim->cpu.clocks += 4; /* TODO: Needs research */ } return 0; } /* Bit string search */ -static int exaBitSearch(VB *vb) { - if (cpuRead(vb, vb->cpu.program[30], VB_S32, &vb->cpu.inst.aux[0])) +static int exaBitSearch(VB *sim) { + if (cpuRead(sim, sim->cpu.program[30], VB_S32, &sim->cpu.inst.aux[0])) return 1; - vb->cpu.clocks += 4; /* TODO: Needs research */ + sim->cpu.clocks += 4; /* TODO: Needs research */ return 0; } /* Branch on condition */ -static int exaBCOND(VB *vb) { - if (cpuCondition(vb, vb->cpu.inst.code[0] >> 9 & 15)) { - vb->cpu.inst.aux[0] = - (vb->cpu.pc + SignExtend(vb->cpu.inst.code[0], 9)) & 0xFFFFFFFE; - vb->cpu.clocks += 3; +static int exaBCOND(VB *sim) { + if (cpuCondition(sim, sim->cpu.inst.code[0] >> 9 & 15)) { + sim->cpu.inst.aux[0] = + (sim->cpu.pc + SignExtend(sim->cpu.inst.code[0], 9)) & 0xFFFFFFFE; + sim->cpu.clocks += 3; } else { - vb->cpu.inst.aux[0] = vb->cpu.pc + vb->cpu.inst.size; - vb->cpu.clocks += 1; + sim->cpu.inst.aux[0] = sim->cpu.pc + sim->cpu.inst.size; + sim->cpu.clocks += 1; } return 0; } /* Compare and exchange interlocked */ -static int exaCAXI(VB *vb) { +static int exaCAXI(VB *sim) { /* First invocation */ - if (vb->cpu.step == 0) { - exaStdThree(vb); - vb->cpu.inst.aux[0] += vb->cpu.inst.aux[1]; /* Address */ - vb->cpu.inst.aux[1] = VB_S32; /* Write type */ - vb->cpu.inst.aux[3] = vb->cpu.program[vb->cpu.inst.code[0] >> 5 & 31]; - vb->cpu.step = 1; + if (sim->cpu.step == 0) { + exaStdThree(sim); + sim->cpu.inst.aux[0] += sim->cpu.inst.aux[1]; /* Address */ + sim->cpu.inst.aux[1] = VB_S32; /* Write type */ + sim->cpu.inst.aux[3] = sim->cpu.program[sim->cpu.inst.code[0]>>5&31]; + sim->cpu.step = 1; } /* Read the lock word and determine the exchange value */ - if (vb->cpu.step == 1) { - if (cpuRead(vb, vb->cpu.inst.aux[0], VB_S32, &vb->cpu.inst.aux[4])) + if (sim->cpu.step == 1) { + if (cpuRead(sim, sim->cpu.inst.aux[0], VB_S32, &sim->cpu.inst.aux[4])) return 1; - vb->cpu.inst.aux[2] = vb->cpu.inst.aux[3] == vb->cpu.inst.aux[4] ? - vb->cpu.program[30] : vb->cpu.inst.aux[4]; - vb->cpu.step = 2; + sim->cpu.inst.aux[2] = sim->cpu.inst.aux[3] == sim->cpu.inst.aux[4] ? + sim->cpu.program[30] : sim->cpu.inst.aux[4]; + sim->cpu.step = 2; } /* Prepare to write the exchange value */ - if (vb->cpu.step == 2) { - if (cpuWritePre(vb, (uint32_t *) &vb->cpu.inst.aux[0], - &vb->cpu.inst.aux[1], &vb->cpu.inst.aux[2])) + if (sim->cpu.step == 2) { + if (cpuWritePre(sim, (uint32_t *) &sim->cpu.inst.aux[0], + &sim->cpu.inst.aux[1], &sim->cpu.inst.aux[2])) return 1; } @@ -396,102 +396,102 @@ static int exaCAXI(VB *vb) { } /* No special action */ -static int exaDefault(VB *vb) { - vb->cpu.clocks += ((OpDef *) vb->cpu.inst.def)->aux; +static int exaDefault(VB *sim) { + sim->cpu.clocks += ((OpDef *) sim->cpu.inst.def)->aux; return 0; } /* Division */ -static int exaDivision(VB *vb) { - exaStdTwo(vb); - if (vb->cpu.inst.aux[0] == 0) { - vb->cpu.clocks = 0; /* exaStdTwo adds clocks */ - vb->cpu.exception = 0xFF80; /* Zero division */ +static int exaDivision(VB *sim) { + exaStdTwo(sim); + if (sim->cpu.inst.aux[0] == 0) { + sim->cpu.clocks = 0; /* exaStdTwo adds clocks */ + sim->cpu.exception = 0xFF80; /* Zero division */ } return 0; } /* Exception */ -static int exaException(VB *vb) { +static int exaException(VB *sim) { VBException exception; /* Exception descriptor */ /* Initial invocation */ - if (vb->cpu.step == 0) { + if (sim->cpu.step == 0) { /* Call the breakpoint handler */ - if (vb->onException != NULL) { + if (sim->onException != NULL) { /* Query the application */ - exception.address = vb->cpu.inst.aux[0]; - exception.code = vb->cpu.exception; + exception.address = sim->cpu.inst.aux[0]; + exception.code = sim->cpu.exception; exception.cancel = 0; - if (vb->onException(vb, &exception)) + if (sim->onException(sim, &exception)) return 1; /* The application canceled the exception */ if (exception.cancel) { - vb->cpu.exception = 0; - vb->cpu.stage = CPU_FETCH; + sim->cpu.exception = 0; + sim->cpu.stage = CPU_FETCH; return 0; } /* Apply changes */ - vb->cpu.inst.aux[0] = exception.address; - vb->cpu.exception = exception.code; + sim->cpu.inst.aux[0] = exception.address; + sim->cpu.exception = exception.code; } /* Fatal exception: stage values for writing */ - if (vb->cpu.psw.np) { - vb->cpu.inst.aux[0] = 0x00000000; - vb->cpu.inst.aux[1] = VB_S32; - vb->cpu.inst.aux[2] = 0xFFFF0000 | vb->cpu.exception; - vb->cpu.inst.aux[3] = 0x00000004; - vb->cpu.inst.aux[4] = VB_S32; - vb->cpu.inst.aux[5] = cpuGetSystemRegister(vb, VB_PSW); - vb->cpu.inst.aux[6] = 0x00000008; - vb->cpu.inst.aux[7] = VB_S32; - vb->cpu.inst.aux[8] = vb->cpu.pc; - vb->cpu.step = 1; + if (sim->cpu.psw.np) { + sim->cpu.inst.aux[0] = 0x00000000; + sim->cpu.inst.aux[1] = VB_S32; + sim->cpu.inst.aux[2] = 0xFFFF0000 | sim->cpu.exception; + sim->cpu.inst.aux[3] = 0x00000004; + sim->cpu.inst.aux[4] = VB_S32; + sim->cpu.inst.aux[5] = cpuGetSystemRegister(sim, VB_PSW); + sim->cpu.inst.aux[6] = 0x00000008; + sim->cpu.inst.aux[7] = VB_S32; + sim->cpu.inst.aux[8] = sim->cpu.pc; + sim->cpu.step = 1; } /* Other exception */ - else vb->cpu.step = 10; + else sim->cpu.step = 10; } /* Prepare to dump fatal exception diagnostic values to memory */ - for (; vb->cpu.step < 10; vb->cpu.step += 3) { - if (cpuWritePre(vb, (uint32_t *) - &vb->cpu.inst.aux[vb->cpu.step - 1], - &vb->cpu.inst.aux[vb->cpu.step ], - &vb->cpu.inst.aux[vb->cpu.step + 1] + for (; sim->cpu.step < 10; sim->cpu.step += 3) { + if (cpuWritePre(sim, (uint32_t *) + &sim->cpu.inst.aux[sim->cpu.step - 1], + &sim->cpu.inst.aux[sim->cpu.step ], + &sim->cpu.inst.aux[sim->cpu.step + 1] )) return 1; } /* Common processing */ - vb->cpu.bitstring = 0; - vb->cpu.clocks += 1; /* TODO: Needs research */ + sim->cpu.bitstring = 0; + sim->cpu.clocks += 1; /* TODO: Needs research */ return 0; } /* One-operand floating-point instruction */ -static int exaFloating1(VB *vb) { +static int exaFloating1(VB *sim) { int bits; /* Number of bits to shift */ int32_t reg1; /* Left operand */ int32_t result; /* Operation result */ int32_t subop; /* Sub-opcode */ /* Reserved operand */ - reg1 = vb->cpu.program[vb->cpu.inst.code[0] & 31]; + reg1 = sim->cpu.program[sim->cpu.inst.code[0] & 31]; if (cpuFRO(reg1)) { - vb->cpu.fp_flags = 0x00000200; /* FRO */ - vb->cpu.exception = 0xFF60; + sim->cpu.fp_flags = 0x00000200; /* FRO */ + sim->cpu.exception = 0xFF60; return 0; } /* Working variables */ bits = (reg1 >> 23 & 0xFF) - 150; result = (reg1 & 0x007FFFFF) | 0x00800000; - subop = vb->cpu.inst.code[1] >> 10 & 63; + subop = sim->cpu.inst.code[1] >> 10 & 63; /* Zero */ if ((reg1 & 0x7FFFFFFF) == 0x00000000) @@ -506,8 +506,8 @@ static int exaFloating1(VB *vb) { /* Invalid operation */ if (bits > 7) { - vb->cpu.fp_flags = 0x00000100; /* FIV */ - vb->cpu.exception = 0xFF70; + sim->cpu.fp_flags = 0x00000100; /* FIV */ + sim->cpu.exception = 0xFF70; return 0; } @@ -529,49 +529,49 @@ static int exaFloating1(VB *vb) { result = -result; /* Stage updates */ - vb->cpu.fp_flags = result == *(float *)®1 ? 0 : 0x00000010; /* FPR */ - vb->cpu.inst.aux[0] = result; - vb->cpu.inst.aux[1] = subop; - vb->cpu.clocks += ((OpDef *) vb->cpu.inst.def)->aux; + sim->cpu.fp_flags = result==*(float *)®1 ? 0 : 0x00000010; /* FPR */ + sim->cpu.inst.aux[0] = result; + sim->cpu.inst.aux[1] = subop; + sim->cpu.clocks += ((OpDef *) sim->cpu.inst.def)->aux; return 0; } /* Two-operand floating-point instruction */ -static int exaFloating2(VB *vb) { +static int exaFloating2(VB *sim) { FloatAux *aux; /* Floating-point auxiliary memory */ int32_t bits; /* Bits of testing value */ int32_t reg1; /* Right operand */ int32_t reg2; /* Left operand */ float test; /* Floating-point testing value */ - OpDef *def = (OpDef *) vb->cpu.inst.def; + OpDef *def = (OpDef *) sim->cpu.inst.def; /* Reserved operand */ - reg1 = vb->cpu.program[vb->cpu.inst.code[0] & 31]; - reg2 = vb->cpu.program[vb->cpu.inst.code[0] >> 5 & 31]; + reg1 = sim->cpu.program[sim->cpu.inst.code[0] & 31]; + reg2 = sim->cpu.program[sim->cpu.inst.code[0] >> 5 & 31]; if (cpuFRO(reg1) || cpuFRO(reg2)) { - vb->cpu.fp_flags = 0x00000200; /* FRO */ - vb->cpu.exception = 0xFF60; + sim->cpu.fp_flags = 0x00000200; /* FRO */ + sim->cpu.exception = 0xFF60; return 0; } /* Perform the operation */ - def->operation(vb, ®2, reg1); - if (vb->cpu.exception != 0) + def->operation(sim, ®2, reg1); + if (sim->cpu.exception != 0) return 0; /* Handled in opDIVF_S() */ - aux = (FloatAux *) &vb->cpu.inst.aux; + aux = (FloatAux *) &sim->cpu.inst.aux; /* Overflow */ bits = 0x7F7FFFFF; /* Maximum value */ test = *(float *)&bits; if (aux->f64 > test || aux->f64 < -test) { - vb->cpu.fp_flags = 0x00000040; /* FOV */ - vb->cpu.exception = 0xFF64; + sim->cpu.fp_flags = 0x00000040; /* FOV */ + sim->cpu.exception = 0xFF64; return 0; } /* Process result */ - bits = *(int32_t *)&aux->f32; - vb->cpu.fp_flags = 0; + bits = *(int32_t *)&aux->f32; + sim->cpu.fp_flags = 0; /* Zero */ if ((bits & 0x7FFFFFFF) == 0x00000000) @@ -579,75 +579,75 @@ static int exaFloating2(VB *vb) { /* Underflow */ else if ((bits & 0x7F800000) == 0x00000000) { - vb->cpu.fp_flags = 0x00000020; /* FUD */ - aux->f32 = bits = 0; + sim->cpu.fp_flags = 0x00000020; /* FUD */ + aux->f32 = bits = 0; } /* Precision degradation */ if (aux->f32 != aux->f64) - vb->cpu.fp_flags |= 0x00000010; /* FPR */ + sim->cpu.fp_flags |= 0x00000010; /* FPR */ /* Other state */ - vb->cpu.inst.aux[0] = bits; - vb->cpu.inst.aux[1] = vb->cpu.inst.code[1] >> 10 & 63; - vb->cpu.clocks += def->aux; + sim->cpu.inst.aux[0] = bits; + sim->cpu.inst.aux[1] = sim->cpu.inst.code[1] >> 10 & 63; + sim->cpu.clocks += def->aux; return 0; } /* Illegal opcode */ -static int exaIllegal(VB *vb) { - vb->cpu.exception = 0xFF90; /* Illegal opcode */ +static int exaIllegal(VB *sim) { + sim->cpu.exception = 0xFF90; /* Illegal opcode */ return 0; } /* Jump relative, jump and link */ -static int exaJR(VB *vb) { - vb->cpu.inst.aux[0] = 0xFFFFFFFE & (vb->cpu.pc + SignExtend( - (int32_t) vb->cpu.inst.code[0] << 16 | vb->cpu.inst.code[1], 26)); - vb->cpu.clocks += 3; +static int exaJR(VB *sim) { + sim->cpu.inst.aux[0] = 0xFFFFFFFE & (sim->cpu.pc + SignExtend( + (int32_t) sim->cpu.inst.code[0] << 16 | sim->cpu.inst.code[1], 26)); + sim->cpu.clocks += 3; return 0; } /* Memory read */ -static int exaRead(VB *vb) { +static int exaRead(VB *sim) { /* First invocation */ - if (vb->cpu.step == 0) { - exaStdThree(vb); - vb->cpu.inst.aux[1] += vb->cpu.inst.aux[0]; /* Address */ - vb->cpu.clocks += 5; /* TODO: Needs research */ - vb->cpu.step = 1; + if (sim->cpu.step == 0) { + exaStdThree(sim); + sim->cpu.inst.aux[1] += sim->cpu.inst.aux[0]; /* Address */ + sim->cpu.clocks += 5; /* TODO: Needs research */ + sim->cpu.step = 1; } /* Read the value */ - return cpuRead(vb, vb->cpu.inst.aux[1], - ((OpDef *) vb->cpu.inst.def)->aux, &vb->cpu.inst.aux[0]); + return cpuRead(sim, sim->cpu.inst.aux[1], + ((OpDef *) sim->cpu.inst.def)->aux, &sim->cpu.inst.aux[0]); } /* Trap */ -static int exaTRAP(VB *vb) { +static int exaTRAP(VB *sim) { /* TODO: Clocks is less 1 here because exaException adds 1 */ - vb->cpu.clocks += ((OpDef *) vb->cpu.inst.def)->aux - 1; - vb->cpu.exception = 0xFFA0 | (vb->cpu.inst.code[0] & 31); + sim->cpu.clocks += ((OpDef *) sim->cpu.inst.def)->aux - 1; + sim->cpu.exception = 0xFFA0 | (sim->cpu.inst.code[0] & 31); return 0; } /* Memory write */ -static int exaWrite(VB *vb) { +static int exaWrite(VB *sim) { /* First invocation */ - if (vb->cpu.step == 0) { - exaStdThree(vb); - vb->cpu.inst.aux[0] += vb->cpu.inst.aux[1]; - vb->cpu.inst.aux[1] = ((OpDef *) vb->cpu.inst.def)->aux; /* Type */ - vb->cpu.inst.aux[2] = vb->cpu.program[vb->cpu.inst.code[0] >> 5 & 31]; - vb->cpu.clocks += 4; /* TODO: Needs research */ - vb->cpu.step = 1; + if (sim->cpu.step == 0) { + exaStdThree(sim); + sim->cpu.inst.aux[0] += sim->cpu.inst.aux[1]; + sim->cpu.inst.aux[1] = ((OpDef *) sim->cpu.inst.def)->aux; /* Type */ + sim->cpu.inst.aux[2] = sim->cpu.program[sim->cpu.inst.code[0]>>5&31]; + sim->cpu.clocks += 4; /* TODO: Needs research */ + sim->cpu.step = 1; } /* Write the value */ - return cpuWritePre(vb, (uint32_t *) &vb->cpu.inst.aux[0], - &vb->cpu.inst.aux[1], &vb->cpu.inst.aux[2]); + return cpuWritePre(sim, (uint32_t *) &sim->cpu.inst.aux[0], + &sim->cpu.inst.aux[1], &sim->cpu.inst.aux[2]); } @@ -655,242 +655,242 @@ static int exaWrite(VB *vb) { /**************************** Execute B Handlers *****************************/ /* Bit string bitwise */ -static void exbBitBitwise(VB *vb) { +static void exbBitBitwise(VB *sim) { int32_t bits; /* Write the output value */ - if (vb->cpu.program[28] != 0) { - busWrite(vb, vb->cpu.inst.aux[3], - vb->cpu.inst.aux[4], vb->cpu.inst.aux[2], 0); + if (sim->cpu.program[28] != 0) { + busWrite(sim, sim->cpu.inst.aux[3], + sim->cpu.inst.aux[4], sim->cpu.inst.aux[2], 0); } /* Prepare registers */ - vb->cpu.program[26] &= 0x0000001F; - vb->cpu.program[27] &= 0x0000001F; - vb->cpu.program[29] &= 0xFFFFFFFC; - vb->cpu.program[30] &= 0xFFFFFFFC; + sim->cpu.program[26] &= 0x0000001F; + sim->cpu.program[27] &= 0x0000001F; + sim->cpu.program[29] &= 0xFFFFFFFC; + sim->cpu.program[30] &= 0xFFFFFFFC; /* Determine how many bits of output have been processed */ - bits = 32 - vb->cpu.program[26]; - if ((uint32_t) vb->cpu.program[28] <= (uint32_t) bits) - bits = vb->cpu.program[28]; + bits = 32 - sim->cpu.program[26]; + if ((uint32_t) sim->cpu.program[28] <= (uint32_t) bits) + bits = sim->cpu.program[28]; /* Update source */ - vb->cpu.program[27] += bits; - if (vb->cpu.program[27] >= 32) { - vb->cpu.program[27] &= 31; - vb->cpu.program[30] += 4; - vb->cpu.inst.aux[0] = vb->cpu.inst.aux[1]; - vb->cpu.bitstring = 1; /* Read next source word */ - } else vb->cpu.bitstring = 2; /* Skip source reads */ + sim->cpu.program[27] += bits; + if (sim->cpu.program[27] >= 32) { + sim->cpu.program[27] &= 31; + sim->cpu.program[30] += 4; + sim->cpu.inst.aux[0] = sim->cpu.inst.aux[1]; + sim->cpu.bitstring = 1; /* Read next source word */ + } else sim->cpu.bitstring = 2; /* Skip source reads */ /* Update destination */ - vb->cpu.program[26] += bits; - if (vb->cpu.program[26] >= 32) { - vb->cpu.program[26] &= 31; - vb->cpu.program[29] += 4; + sim->cpu.program[26] += bits; + if (sim->cpu.program[26] >= 32) { + sim->cpu.program[26] &= 31; + sim->cpu.program[29] += 4; } /* Update length */ - vb->cpu.program[28] -= bits; + sim->cpu.program[28] -= bits; /* Advance to the next instruction */ - if (vb->cpu.program[28] == 0) { - vb->cpu.bitstring = 0; - vb->cpu.pc += vb->cpu.inst.size; + if (sim->cpu.program[28] == 0) { + sim->cpu.bitstring = 0; + sim->cpu.pc += sim->cpu.inst.size; } } /* Bit string search */ -static void exbBitSearch(VB *vb) { - int32_t dir = ((~vb->cpu.inst.code[0] & 1) << 1) - 1; - int32_t test = vb->cpu.inst.code[0] >> 1 & 1; +static void exbBitSearch(VB *sim) { + int32_t dir = ((~sim->cpu.inst.code[0] & 1) << 1) - 1; + int32_t test = sim->cpu.inst.code[0] >> 1 & 1; /* Prepare registers */ - vb->cpu.program[27] &= 0x0000001F; - vb->cpu.program[30] &= 0xFFFFFFFC; - vb->cpu.psw.z = 1; - vb->cpu.bitstring = 1; + sim->cpu.program[27] &= 0x0000001F; + sim->cpu.program[30] &= 0xFFFFFFFC; + sim->cpu.psw.z = 1; + sim->cpu.bitstring = 1; /* Process all remaining bits in the current word */ - while (vb->cpu.psw.z && vb->cpu.program[28] != 0) { + while (sim->cpu.psw.z && sim->cpu.program[28] != 0) { /* The bit does not match */ if ( - (vb->cpu.inst.aux[0] & 1 << vb->cpu.program[27]) != - test << vb->cpu.program[27] - ) vb->cpu.program[29]++; + (sim->cpu.inst.aux[0] & 1 << sim->cpu.program[27]) != + test << sim->cpu.program[27] + ) sim->cpu.program[29]++; /* A match was found */ - else vb->cpu.psw.z = 0; + else sim->cpu.psw.z = 0; /* Advance to the next bit */ - vb->cpu.program[28]--; - vb->cpu.program[27] += dir; - if (vb->cpu.program[27] & 0x00000020) { - vb->cpu.program[27] &= 0x0000001F; - vb->cpu.program[30] += dir << 2; + sim->cpu.program[28]--; + sim->cpu.program[27] += dir; + if (sim->cpu.program[27] & 0x00000020) { + sim->cpu.program[27] &= 0x0000001F; + sim->cpu.program[30] += dir << 2; break; } } /* Advance to the next instruction */ - if (!vb->cpu.psw.z || vb->cpu.program[28] == 0) { - vb->cpu.bitstring = 0; - vb->cpu.pc += vb->cpu.inst.size; + if (!sim->cpu.psw.z || sim->cpu.program[28] == 0) { + sim->cpu.bitstring = 0; + sim->cpu.pc += sim->cpu.inst.size; } } /* Compare and exchange interlocked */ -static void exbCAXI(VB *vb) { - int32_t left = vb->cpu.inst.aux[3]; - int32_t right = vb->cpu.inst.aux[4]; +static void exbCAXI(VB *sim) { + int32_t left = sim->cpu.inst.aux[3]; + int32_t right = sim->cpu.inst.aux[4]; int32_t result = left - right; - vb->cpu.psw.cy = (uint32_t) left < (uint32_t) right; - vb->cpu.psw.ov = (int32_t) ((left ^ right) & (left ^ result)) < 0; - vb->cpu.psw.s = result < 0; - vb->cpu.psw.z = result == 0; - vb->cpu.pc += vb->cpu.inst.size; - vb->cpu.program[vb->cpu.inst.code[0] >> 5 & 31] = right; - busWrite(vb, vb->cpu.inst.aux[0], - vb->cpu.inst.aux[1], vb->cpu.inst.aux[2], 0); + sim->cpu.psw.cy = (uint32_t) left < (uint32_t) right; + sim->cpu.psw.ov = (int32_t) ((left ^ right) & (left ^ result)) < 0; + sim->cpu.psw.s = result < 0; + sim->cpu.psw.z = result == 0; + sim->cpu.pc += sim->cpu.inst.size; + sim->cpu.program[sim->cpu.inst.code[0] >> 5 & 31] = right; + busWrite(sim, sim->cpu.inst.aux[0], + sim->cpu.inst.aux[1], sim->cpu.inst.aux[2], 0); } /* Clear interrupt disable flag */ -static void exbCLI(VB *vb) { - vb->cpu.pc += vb->cpu.inst.size; - vb->cpu.psw.id = 0; +static void exbCLI(VB *sim) { + sim->cpu.pc += sim->cpu.inst.size; + sim->cpu.psw.id = 0; } /* Exception */ -static void exbException(VB *vb) { +static void exbException(VB *sim) { int x; /* Iterator */ /* Apply staged floating-point flags */ - if (vb->cpu.fp_flags != 0) { - cpuSetSystemRegister(vb, VB_PSW, vb->cpu.fp_flags | - cpuGetSystemRegister(vb, VB_PSW), 0); - vb->cpu.fp_flags = 0; + if (sim->cpu.fp_flags != 0) { + cpuSetSystemRegister(sim, VB_PSW, sim->cpu.fp_flags | + cpuGetSystemRegister(sim, VB_PSW), 0); + sim->cpu.fp_flags = 0; } /* Fatal exception */ - if (vb->cpu.psw.np) { + if (sim->cpu.psw.np) { for (x = 0; x < 9; x += 3) { - busWrite(vb, vb->cpu.inst.aux[x], - vb->cpu.inst.aux[x + 1], vb->cpu.inst.aux[x + 2], 0); + busWrite(sim, sim->cpu.inst.aux[x], + sim->cpu.inst.aux[x + 1], sim->cpu.inst.aux[x + 2], 0); } - vb->cpu.stage = CPU_FATAL; + sim->cpu.stage = CPU_FATAL; return; } /* Duplexed exception */ - if (vb->cpu.psw.ep) { - vb->cpu.ecr.fecc = vb->cpu.exception; - vb->cpu.fepc = vb->cpu.pc; - vb->cpu.fepsw = cpuGetSystemRegister(vb, VB_PSW); - vb->cpu.pc = 0xFFFFFFD0; - vb->cpu.psw.np = 1; + if (sim->cpu.psw.ep) { + sim->cpu.ecr.fecc = sim->cpu.exception; + sim->cpu.fepc = sim->cpu.pc; + sim->cpu.fepsw = cpuGetSystemRegister(sim, VB_PSW); + sim->cpu.pc = 0xFFFFFFD0; + sim->cpu.psw.np = 1; } /* Regular exception */ else { - vb->cpu.ecr.eicc = vb->cpu.exception; - vb->cpu.eipc = vb->cpu.pc; - vb->cpu.eipsw = cpuGetSystemRegister(vb, VB_PSW); - vb->cpu.pc = vb->cpu.inst.aux[0]; - vb->cpu.psw.ep = 1; + sim->cpu.ecr.eicc = sim->cpu.exception; + sim->cpu.eipc = sim->cpu.pc; + sim->cpu.eipsw = cpuGetSystemRegister(sim, VB_PSW); + sim->cpu.pc = sim->cpu.inst.aux[0]; + sim->cpu.psw.ep = 1; /* Interrupt */ - if (vb->cpu.exception < 0xFF00) { - if ((vb->cpu.inst.code[0] & 0xFC00) == 0x6800) /* HALT */ - vb->cpu.eipc += vb->cpu.inst.size; - vb->cpu.psw.i = Min(15, (vb->cpu.exception >> 4 & 15) + 1); + if (sim->cpu.exception < 0xFF00) { + if ((sim->cpu.inst.code[0] & 0xFC00) == 0x6800) /* HALT */ + sim->cpu.eipc += sim->cpu.inst.size; + sim->cpu.psw.i = Min(15, (sim->cpu.exception >> 4 & 15) + 1); } /* TRAP */ - if ((vb->cpu.exception & 0xFFE0) == 0xFFA0) - vb->cpu.eipc += vb->cpu.inst.size; + if ((sim->cpu.exception & 0xFFE0) == 0xFFA0) + sim->cpu.eipc += sim->cpu.inst.size; } /* Common processing */ - vb->cpu.psw.ae = 0; - vb->cpu.psw.id = 1; + sim->cpu.psw.ae = 0; + sim->cpu.psw.id = 1; } /* Floating-point instruction */ -static void exbFloating(VB *vb) { - int32_t result = vb->cpu.inst.aux[0]; /* Operation result */ - int32_t subop = vb->cpu.inst.aux[1]; /* Sub-opcode */ +static void exbFloating(VB *sim) { + int32_t result = sim->cpu.inst.aux[0]; /* Operation result */ + int32_t subop = sim->cpu.inst.aux[1]; /* Sub-opcode */ /* Apply staged floating-point flags */ - if (vb->cpu.fp_flags != 0) { - cpuSetSystemRegister(vb, VB_PSW, vb->cpu.fp_flags | - cpuGetSystemRegister(vb, VB_PSW), 0); - vb->cpu.fp_flags = 0; + if (sim->cpu.fp_flags != 0) { + cpuSetSystemRegister(sim, VB_PSW, sim->cpu.fp_flags | + cpuGetSystemRegister(sim, VB_PSW), 0); + sim->cpu.fp_flags = 0; } /* Update state */ - vb->cpu.pc += vb->cpu.inst.size; - vb->cpu.psw.ov = 0; - vb->cpu.psw.s = result < 0; - vb->cpu.psw.z = result == 0; + sim->cpu.pc += sim->cpu.inst.size; + sim->cpu.psw.ov = 0; + sim->cpu.psw.s = result < 0; + sim->cpu.psw.z = result == 0; if (subop != 0x03 && subop != 0x0B) /* CVT.SW, TRNC.SW */ - vb->cpu.psw.cy = result < 0; + sim->cpu.psw.cy = result < 0; if (subop != 0x00) /* CMPF.S */ - vb->cpu.program[vb->cpu.inst.code[0] >> 5 & 31] = result; + sim->cpu.program[sim->cpu.inst.code[0] >> 5 & 31] = result; } /* Halt */ -static void exbHALT(VB *vb) { - vb->cpu.stage = CPU_HALT; +static void exbHALT(VB *sim) { + sim->cpu.stage = CPU_HALT; } /* Jump and link */ -static void exbJAL(VB *vb) { - vb->cpu.program[31] = vb->cpu.pc + vb->cpu.inst.size; - vb->cpu.pc = vb->cpu.inst.aux[0]; +static void exbJAL(VB *sim) { + sim->cpu.program[31] = sim->cpu.pc + sim->cpu.inst.size; + sim->cpu.pc = sim->cpu.inst.aux[0]; } /* Jump */ -static void exbJMP(VB *vb) { - vb->cpu.pc = vb->cpu.inst.aux[0]; +static void exbJMP(VB *sim) { + sim->cpu.pc = sim->cpu.inst.aux[0]; } /* Return from trap or interrupt */ -static void exbRETI(VB *vb) { - if (vb->cpu.psw.np) { - vb->cpu.pc = vb->cpu.fepc; - cpuSetSystemRegister(vb, VB_PSW, vb->cpu.fepsw, 0); +static void exbRETI(VB *sim) { + if (sim->cpu.psw.np) { + sim->cpu.pc = sim->cpu.fepc; + cpuSetSystemRegister(sim, VB_PSW, sim->cpu.fepsw, 0); } else { - vb->cpu.pc = vb->cpu.eipc; - cpuSetSystemRegister(vb, VB_PSW, vb->cpu.eipsw, 0); + sim->cpu.pc = sim->cpu.eipc; + cpuSetSystemRegister(sim, VB_PSW, sim->cpu.eipsw, 0); } } /* Set interrupt disable flag */ -static void exbSEI(VB *vb) { - vb->cpu.pc += vb->cpu.inst.size; - vb->cpu.psw.id = 1; +static void exbSEI(VB *sim) { + sim->cpu.pc += sim->cpu.inst.size; + sim->cpu.psw.id = 1; } /* Standard two-operand instruction */ -static void exbStdTwo(VB *vb) { - ((OpDef *) vb->cpu.inst.def)->operation(vb, - &vb->cpu.program[vb->cpu.inst.code[0] >> 5 & 31], - vb->cpu.inst.aux[0] +static void exbStdTwo(VB *sim) { + ((OpDef *) sim->cpu.inst.def)->operation(sim, + &sim->cpu.program[sim->cpu.inst.code[0] >> 5 & 31], + sim->cpu.inst.aux[0] ); - vb->cpu.pc += vb->cpu.inst.size; + sim->cpu.pc += sim->cpu.inst.size; } /* Standard three-operand instruction */ -static void exbStdThree(VB *vb) { - int32_t *reg2 = &vb->cpu.program[vb->cpu.inst.code[0] >> 5 & 31]; - *reg2 = vb->cpu.inst.aux[1]; - ((OpDef *) vb->cpu.inst.def)->operation(vb, reg2, vb->cpu.inst.aux[0]); - vb->cpu.pc += vb->cpu.inst.size; +static void exbStdThree(VB *sim) { + int32_t *reg2 = &sim->cpu.program[sim->cpu.inst.code[0] >> 5 & 31]; + *reg2 = sim->cpu.inst.aux[1]; + ((OpDef *) sim->cpu.inst.def)->operation(sim, reg2, sim->cpu.inst.aux[0]); + sim->cpu.pc += sim->cpu.inst.size; } @@ -898,18 +898,18 @@ static void exbStdThree(VB *vb) { /**************************** Operation Handlers *****************************/ /* Add */ -static void opADD(VB *vb, int32_t *dest, int32_t src) { - int32_t result = *dest + src; - vb->cpu.psw.cy = (uint32_t) result < (uint32_t) *dest; - vb->cpu.psw.ov = (int32_t) (~(*dest ^ src) & (*dest ^ result)) < 0; - vb->cpu.psw.s = result < 0; - vb->cpu.psw.z = result == 0; - *dest = result; +static void opADD(VB *sim, int32_t *dest, int32_t src) { + int32_t result = *dest + src; + sim->cpu.psw.cy = (uint32_t) result < (uint32_t) *dest; + sim->cpu.psw.ov = (int32_t) (~(*dest ^ src) & (*dest ^ result)) < 0; + sim->cpu.psw.s = result < 0; + sim->cpu.psw.z = result == 0; + *dest = result; } /* Add Floating Short */ -static void opADDF_S(VB *vb, int32_t *dest, int32_t src) { - FloatAux *aux = (FloatAux *) vb->cpu.inst.aux; +static void opADDF_S(VB *sim, int32_t *dest, int32_t src) { + FloatAux *aux = (FloatAux *) sim->cpu.inst.aux; double left = *(float *)dest; double right = *(float *)&src; double result = left + right; @@ -918,64 +918,64 @@ static void opADDF_S(VB *vb, int32_t *dest, int32_t src) { } /* And */ -static void opAND(VB *vb, int32_t *dest, int32_t src) { - int32_t result = *dest & src; - vb->cpu.psw.ov = 0; - vb->cpu.psw.s = result < 0; - vb->cpu.psw.z = result == 0; - *dest = result; +static void opAND(VB *sim, int32_t *dest, int32_t src) { + int32_t result = *dest & src; + sim->cpu.psw.ov = 0; + sim->cpu.psw.s = result < 0; + sim->cpu.psw.z = result == 0; + *dest = result; } /* And Bit String Upward */ -static void opANDBSU(VB *vb, int32_t *dest, int32_t src) { - (void) vb; +static void opANDBSU(VB *sim, int32_t *dest, int32_t src) { + (void) sim; *dest &= src; } /* And Not Bit String Upward */ -static void opANDNBSU(VB *vb, int32_t *dest, int32_t src) { - (void) vb; +static void opANDNBSU(VB *sim, int32_t *dest, int32_t src) { + (void) sim; *dest = ~*dest & src; } /* Compare */ -static void opCMP(VB *vb, int32_t *dest, int32_t src) { +static void opCMP(VB *sim, int32_t *dest, int32_t src) { int32_t result = *dest - src; - vb->cpu.psw.cy = (uint32_t) *dest < (uint32_t) src; - vb->cpu.psw.ov = (int32_t) ((*dest ^ src) & (*dest ^ result)) < 0; - vb->cpu.psw.s = result < 0; - vb->cpu.psw.z = result == 0; + sim->cpu.psw.cy = (uint32_t) *dest < (uint32_t) src; + sim->cpu.psw.ov = (int32_t) ((*dest ^ src) & (*dest ^ result)) < 0; + sim->cpu.psw.s = result < 0; + sim->cpu.psw.z = result == 0; } /* Convert Word Integer to Short Floating */ -static void opCVT_WS(VB *vb, int32_t *dest, int32_t src) { +static void opCVT_WS(VB *sim, int32_t *dest, int32_t src) { float value = (float) src; *dest = *(int32_t *)&value; if ((double) value != (double) src) - vb->cpu.psw.fpr = 1; + sim->cpu.psw.fpr = 1; } /* Divide signed */ -static void opDIV(VB *vb, int32_t *dest, int32_t src) { +static void opDIV(VB *sim, int32_t *dest, int32_t src) { int32_t result; if (*dest == INT32_MIN && src == -1) { - vb->cpu.psw.ov = 1; - vb->cpu.psw.s = 1; - vb->cpu.psw.z = 0; - vb->cpu.program[30] = 0; + sim->cpu.psw.ov = 1; + sim->cpu.psw.s = 1; + sim->cpu.psw.z = 0; + sim->cpu.program[30] = 0; } else { - result = *dest / src; - vb->cpu.psw.ov = 0; - vb->cpu.psw.s = result < 0; - vb->cpu.psw.z = result == 0; - vb->cpu.program[30] = *dest % src; - *dest = result; + result = *dest / src; + sim->cpu.psw.ov = 0; + sim->cpu.psw.s = result < 0; + sim->cpu.psw.z = result == 0; + sim->cpu.program[30] = *dest % src; + *dest = result; } } /* Divide Floating Short */ -static void opDIVF_S(VB *vb, int32_t *dest, int32_t src) { - FloatAux *aux = (FloatAux *) vb->cpu.inst.aux; +static void opDIVF_S(VB *sim, int32_t *dest, int32_t src) { + FloatAux *aux = (FloatAux *) sim->cpu.inst.aux; double left; /* Left operand */ double right; /* Right operand */ double result; /* Operation result */ @@ -985,14 +985,14 @@ static void opDIVF_S(VB *vb, int32_t *dest, int32_t src) { /* Invalid operation */ if (src == 0) { - vb->cpu.fp_flags = 0x00000100; /* FIV */ - vb->cpu.exception = 0xFF70; + sim->cpu.fp_flags = 0x00000100; /* FIV */ + sim->cpu.exception = 0xFF70; } /* Zero division */ else { - vb->cpu.fp_flags = 0x00000080; /* FZD */ - vb->cpu.exception = 0xFF68; + sim->cpu.fp_flags = 0x00000080; /* FZD */ + sim->cpu.exception = 0xFF68; } return; @@ -1007,59 +1007,59 @@ static void opDIVF_S(VB *vb, int32_t *dest, int32_t src) { } /* Divide unsigned */ -static void opDIVU(VB *vb, int32_t *dest, int32_t src) { - uint32_t result = (uint32_t) *dest / (uint32_t) src; - vb->cpu.psw.ov = 0; - vb->cpu.psw.s = (int32_t) result < 0; - vb->cpu.psw.z = result == 0; - vb->cpu.program[30] = (int32_t) ((uint32_t) *dest % (uint32_t) src); - *dest = (int32_t) result; +static void opDIVU(VB *sim, int32_t *dest, int32_t src) { + uint32_t result = (uint32_t) *dest / (uint32_t) src; + sim->cpu.psw.ov = 0; + sim->cpu.psw.s = (int32_t) result < 0; + sim->cpu.psw.z = result == 0; + sim->cpu.program[30] = (int32_t) ((uint32_t) *dest % (uint32_t) src); + *dest = (int32_t) result; } /* Load to system register */ -static void opLDSR(VB *vb, int32_t *dest, int32_t src) { - cpuSetSystemRegister(vb, src, *dest, 0); +static void opLDSR(VB *sim, int32_t *dest, int32_t src) { + cpuSetSystemRegister(sim, src, *dest, 0); } /* Move */ -static void opMOV(VB *vb, int32_t *dest, int32_t src) { - (void) vb; +static void opMOV(VB *sim, int32_t *dest, int32_t src) { + (void) sim; *dest = src; } /* Move Bit String Upward */ -static void opMOVBSU(VB *vb, int32_t *dest, int32_t src) { - (void) vb; +static void opMOVBSU(VB *sim, int32_t *dest, int32_t src) { + (void) sim; (void) dest; (void) src; } /* Add Immediate */ -static void opMOVEA(VB *vb, int32_t *dest, int32_t src) { - (void) vb; +static void opMOVEA(VB *sim, int32_t *dest, int32_t src) { + (void) sim; *dest += src; } /* Multiply Halfword */ -static void opMPYHW(VB *vb, int32_t *dest, int32_t src) { - (void) vb; +static void opMPYHW(VB *sim, int32_t *dest, int32_t src) { + (void) sim; *dest *= SignExtend(src, 17); } /* Multiply signed */ -static void opMUL(VB *vb, int32_t *dest, int32_t src) { - int64_t result = (int64_t) *dest * (int64_t) src; - int32_t resultLow = (int32_t) result; - vb->cpu.psw.ov = result != resultLow; - vb->cpu.psw.s = resultLow < 0; - vb->cpu.psw.z = resultLow == 0; - vb->cpu.program[30] = (int32_t) (result >> 32); - *dest = resultLow; +static void opMUL(VB *sim, int32_t *dest, int32_t src) { + int64_t result = (int64_t) *dest * (int64_t) src; + int32_t resultLow = (int32_t) result; + sim->cpu.psw.ov = result != resultLow; + sim->cpu.psw.s = resultLow < 0; + sim->cpu.psw.z = resultLow == 0; + sim->cpu.program[30] = (int32_t) (result >> 32); + *dest = resultLow; } /* Multiply Floating Short */ -static void opMULF_S(VB *vb, int32_t *dest, int32_t src) { - FloatAux *aux = (FloatAux *) vb->cpu.inst.aux; +static void opMULF_S(VB *sim, int32_t *dest, int32_t src) { + FloatAux *aux = (FloatAux *) sim->cpu.inst.aux; double left = *(float *)dest; double right = *(float *)&src; double result = left * right; @@ -1068,56 +1068,56 @@ static void opMULF_S(VB *vb, int32_t *dest, int32_t src) { } /* Multiply unsigned */ -static void opMULU(VB *vb, int32_t *dest, int32_t src) { - uint64_t result = (uint64_t)(uint32_t)*dest * (uint64_t)(uint32_t)src; - uint32_t resultLow = (uint32_t) result; - vb->cpu.psw.ov = result != resultLow; - vb->cpu.psw.s = (int32_t) resultLow < 0; - vb->cpu.psw.z = resultLow == 0; - vb->cpu.program[30] = (int32_t) (result >> 32); - *dest = (int32_t) resultLow; +static void opMULU(VB *sim, int32_t *dest, int32_t src) { + uint64_t result = (uint64_t)(uint32_t)*dest * (uint64_t)(uint32_t)src; + uint32_t resultLow = (uint32_t) result; + sim->cpu.psw.ov = result != resultLow; + sim->cpu.psw.s = (int32_t) resultLow < 0; + sim->cpu.psw.z = resultLow == 0; + sim->cpu.program[30] = (int32_t) (result >> 32); + *dest = (int32_t) resultLow; } /* Not */ -static void opNOT(VB *vb, int32_t *dest, int32_t src) { +static void opNOT(VB *sim, int32_t *dest, int32_t src) { int32_t result = ~src; - vb->cpu.psw.ov = 0; - vb->cpu.psw.s = result < 0; - vb->cpu.psw.z = result == 0; - *dest = result; + sim->cpu.psw.ov = 0; + sim->cpu.psw.s = result < 0; + sim->cpu.psw.z = result == 0; + *dest = result; } /* Not Bit String Upward */ -static void opNOTBSU(VB *vb, int32_t *dest, int32_t src) { - (void) vb; +static void opNOTBSU(VB *sim, int32_t *dest, int32_t src) { + (void) sim; (void) src; *dest = ~*dest; } /* Or */ -static void opOR(VB *vb, int32_t *dest, int32_t src) { - int32_t result = *dest | src; - vb->cpu.psw.ov = 0; - vb->cpu.psw.s = result < 0; - vb->cpu.psw.z = result == 0; - *dest = result; +static void opOR(VB *sim, int32_t *dest, int32_t src) { + int32_t result = *dest | src; + sim->cpu.psw.ov = 0; + sim->cpu.psw.s = result < 0; + sim->cpu.psw.z = result == 0; + *dest = result; } /* Or Bit String Upward */ -static void opORBSU(VB *vb, int32_t *dest, int32_t src) { - (void) vb; +static void opORBSU(VB *sim, int32_t *dest, int32_t src) { + (void) sim; *dest |= src; } /* Or Not Bit String Upward */ -static void opORNBSU(VB *vb, int32_t *dest, int32_t src) { - (void) vb; +static void opORNBSU(VB *sim, int32_t *dest, int32_t src) { + (void) sim; *dest = ~*dest | src; } /* Reverse Bits in Word */ -static void opREV(VB *vb, int32_t *dest, int32_t src) { - (void) vb; +static void opREV(VB *sim, int32_t *dest, int32_t src) { + (void) sim; src = (src << 16 & 0xFFFF0000) | (src >> 16 & 0x0000FFFF); src = (src << 8 & 0xFF00FF00) | (src >> 8 & 0x00FF00FF); src = (src << 4 & 0xF0F0F0F0) | (src >> 4 & 0x0F0F0F0F); @@ -1126,73 +1126,73 @@ static void opREV(VB *vb, int32_t *dest, int32_t src) { } /* Set flag condition */ -static void opSETF(VB *vb, int32_t *dest, int32_t src) { - *dest = cpuCondition(vb, src & 15); +static void opSETF(VB *sim, int32_t *dest, int32_t src) { + *dest = cpuCondition(sim, src & 15); } /* Shift right arithmetic */ -static void opSAR(VB *vb, int32_t *dest, int32_t src) { +static void opSAR(VB *sim, int32_t *dest, int32_t src) { int32_t result = *dest >> (src &= 31); #ifndef VB_SIGNED_PROPAGATE if (src != 0) result = SignExtend(result, 32 - src); #endif - vb->cpu.psw.cy = src != 0 && *dest & 1 << (src - 1); - vb->cpu.psw.ov = 0; - vb->cpu.psw.s = result < 0; - vb->cpu.psw.z = result == 0; - *dest = result; + sim->cpu.psw.cy = src != 0 && *dest & 1 << (src - 1); + sim->cpu.psw.ov = 0; + sim->cpu.psw.s = result < 0; + sim->cpu.psw.z = result == 0; + *dest = result; } /* Shift left */ -static void opSHL(VB *vb, int32_t *dest, int32_t src) { - int32_t result = *dest << (src &= 31); - vb->cpu.psw.cy = src != 0 && *dest & 1 << (32 - src); - vb->cpu.psw.ov = 0; - vb->cpu.psw.s = result < 0; - vb->cpu.psw.z = result == 0; - *dest = result; +static void opSHL(VB *sim, int32_t *dest, int32_t src) { + int32_t result = *dest << (src &= 31); + sim->cpu.psw.cy = src != 0 && *dest & 1 << (32 - src); + sim->cpu.psw.ov = 0; + sim->cpu.psw.s = result < 0; + sim->cpu.psw.z = result == 0; + *dest = result; } /* Shift right logical */ -static void opSHR(VB *vb, int32_t *dest, int32_t src) { +static void opSHR(VB *sim, int32_t *dest, int32_t src) { int32_t result = (uint32_t) *dest >> (src &= 31); #ifndef VB_SIGNED_PROPAGATE if (src != 0) result &= ((uint32_t) 1 << (32 - src)) - 1; #endif - vb->cpu.psw.cy = src != 0 && *dest & 1 << (src - 1); - vb->cpu.psw.ov = 0; - vb->cpu.psw.s = result < 0; - vb->cpu.psw.z = result == 0; - *dest = result; + sim->cpu.psw.cy = src != 0 && *dest & 1 << (src - 1); + sim->cpu.psw.ov = 0; + sim->cpu.psw.s = result < 0; + sim->cpu.psw.z = result == 0; + *dest = result; } /* Store */ -static void opST(VB *vb, int32_t *dest, int32_t src) { +static void opST(VB *sim, int32_t *dest, int32_t src) { (void) dest, (void) src; - busWrite(vb, vb->cpu.inst.aux[0], - vb->cpu.inst.aux[1], vb->cpu.inst.aux[2], 0); + busWrite(sim, sim->cpu.inst.aux[0], + sim->cpu.inst.aux[1], sim->cpu.inst.aux[2], 0); } /* Store to system register */ -static void opSTSR(VB *vb, int32_t *dest, int32_t src) { - *dest = cpuGetSystemRegister(vb, src); +static void opSTSR(VB *sim, int32_t *dest, int32_t src) { + *dest = cpuGetSystemRegister(sim, src); } /* Subtract */ -static void opSUB(VB *vb, int32_t *dest, int32_t src) { - int32_t result = *dest - src; - vb->cpu.psw.cy = (uint32_t) *dest < (uint32_t) src; - vb->cpu.psw.ov = (int32_t) ((*dest ^ src) & (*dest ^ result)) < 0; - vb->cpu.psw.s = result < 0; - vb->cpu.psw.z = result == 0; - *dest = result; +static void opSUB(VB *sim, int32_t *dest, int32_t src) { + int32_t result = *dest - src; + sim->cpu.psw.cy = (uint32_t) *dest < (uint32_t) src; + sim->cpu.psw.ov = (int32_t) ((*dest ^ src) & (*dest ^ result)) < 0; + sim->cpu.psw.s = result < 0; + sim->cpu.psw.z = result == 0; + *dest = result; } /* Subtract Floating Short */ -static void opSUBF_S(VB *vb, int32_t *dest, int32_t src) { - FloatAux *aux = (FloatAux *) vb->cpu.inst.aux; +static void opSUBF_S(VB *sim, int32_t *dest, int32_t src) { + FloatAux *aux = (FloatAux *) sim->cpu.inst.aux; double left = *(float *)dest; double right = *(float *)&src; double result = left - right; @@ -1201,35 +1201,35 @@ static void opSUBF_S(VB *vb, int32_t *dest, int32_t src) { } /* Exchange Byte */ -static void opXB(VB *vb, int32_t *dest, int32_t src) { - (void) vb; +static void opXB(VB *sim, int32_t *dest, int32_t src) { + (void) sim; *dest = (src & 0xFFFF0000) | (src << 8 & 0xFF00) | (src >> 8 & 0x00FF); } /* Exchange Halfword */ -static void opXH(VB *vb, int32_t *dest, int32_t src) { - (void) vb; +static void opXH(VB *sim, int32_t *dest, int32_t src) { + (void) sim; *dest = (src << 16 & 0xFFFF0000) | (src >> 16 & 0x0000FFFF); } /* Exclusive Or */ -static void opXOR(VB *vb, int32_t *dest, int32_t src) { - int32_t result = *dest ^ src; - vb->cpu.psw.ov = 0; - vb->cpu.psw.s = result < 0; - vb->cpu.psw.z = result == 0; - *dest = result; +static void opXOR(VB *sim, int32_t *dest, int32_t src) { + int32_t result = *dest ^ src; + sim->cpu.psw.ov = 0; + sim->cpu.psw.s = result < 0; + sim->cpu.psw.z = result == 0; + *dest = result; } /* Exclusive Or Bit String Upward */ -static void opXORBSU(VB *vb, int32_t *dest, int32_t src) { - (void) vb; +static void opXORBSU(VB *sim, int32_t *dest, int32_t src) { + (void) sim; *dest ^= src; } /* Exclusive Or Not Bit String Upward */ -static void opXORNBSU(VB *vb, int32_t *dest, int32_t src) { - (void) vb; +static void opXORNBSU(VB *sim, int32_t *dest, int32_t src) { + (void) sim; *dest = ~*dest ^ src; } @@ -1238,38 +1238,38 @@ static void opXORNBSU(VB *vb, int32_t *dest, int32_t src) { /***************************** Operand Handlers ******************************/ /* imm5 (sign-extended) */ -static int32_t opImm5S(VB *vb) { - return SignExtend(vb->cpu.inst.code[0] & 31, 5); +static int32_t opImm5S(VB *sim) { + return SignExtend(sim->cpu.inst.code[0] & 31, 5); } /* imm5 */ -static int32_t opImm5U(VB *vb) { - return vb->cpu.inst.code[0] & 31; +static int32_t opImm5U(VB *sim) { + return sim->cpu.inst.code[0] & 31; } /* imm16 (shifted left by 16) */ -static int32_t opImm16H(VB *vb) { - return (uint32_t) vb->cpu.inst.code[1] << 16; +static int32_t opImm16H(VB *sim) { + return (uint32_t) sim->cpu.inst.code[1] << 16; } /* imm16 (sign-extended) */ -static int32_t opImm16S(VB *vb) { - return SignExtend(vb->cpu.inst.code[1], 16); +static int32_t opImm16S(VB *sim) { + return SignExtend(sim->cpu.inst.code[1], 16); } /* imm16 */ -static int32_t opImm16U(VB *vb) { - return vb->cpu.inst.code[1]; +static int32_t opImm16U(VB *sim) { + return sim->cpu.inst.code[1]; } /* reg1 */ -static int32_t opReg1(VB *vb) { - return vb->cpu.program[vb->cpu.inst.code[0] & 31]; +static int32_t opReg1(VB *sim) { + return sim->cpu.program[sim->cpu.inst.code[0] & 31]; } /* reg2 */ -static int32_t opReg2(VB *vb) { - return vb->cpu.program[vb->cpu.inst.code[0] >> 5 & 31]; +static int32_t opReg2(VB *sim) { + return sim->cpu.program[sim->cpu.inst.code[0] >> 5 & 31]; } @@ -1457,19 +1457,19 @@ static const OpDef OPDEFS_FLOATENDO[] = { }; /* Bit string instructions */ -static int exaBitString(VB *vb) { +static int exaBitString(VB *sim) { OpDef *def; /* Opcode definition */ - vb->cpu.inst.def = def = - (OpDef *) &OPDEFS_BITSTRING[vb->cpu.inst.code[0] & 31]; - return def->executeA(vb); + sim->cpu.inst.def = def = + (OpDef *) &OPDEFS_BITSTRING[sim->cpu.inst.code[0] & 31]; + return def->executeA(sim); } /* Floating-point and Nintendo instruction parser */ -static int exaFloatendo(VB *vb) { +static int exaFloatendo(VB *sim) { OpDef *def; /* Opcode definition */ - vb->cpu.inst.def = def = - (OpDef *) &OPDEFS_FLOATENDO[vb->cpu.inst.code[1] >> 10 & 63]; - return def->executeA(vb); + sim->cpu.inst.def = def = + (OpDef *) &OPDEFS_FLOATENDO[sim->cpu.inst.code[1] >> 10 & 63]; + return def->executeA(sim); } @@ -1477,106 +1477,106 @@ static int exaFloatendo(VB *vb) { /****************************** Pipeline Stages ******************************/ /* Raise an exception */ -static void cpuException(VB *vb) { - vb->cpu.inst.def = (OpDef *) &OPDEF_EXCEPTION; - vb->cpu.stage = CPU_EXECUTE_A; - vb->cpu.inst.aux[0] = 0xFFFF0000 | (vb->cpu.exception & 0xFFF0); - if (vb->cpu.inst.aux[0] == (int32_t) 0xFFFFFF70) - vb->cpu.inst.aux[0] = 0xFFFFFF60; +static void cpuException(VB *sim) { + sim->cpu.inst.def = (OpDef *) &OPDEF_EXCEPTION; + sim->cpu.stage = CPU_EXECUTE_A; + sim->cpu.inst.aux[0] = 0xFFFF0000 | (sim->cpu.exception & 0xFFF0); + if (sim->cpu.inst.aux[0] == (int32_t) 0xFFFFFF70) + sim->cpu.inst.aux[0] = 0xFFFFFF60; } /* Execute: Pre-processing, does not update state */ -static int cpuExecuteA(VB *vb) { +static int cpuExecuteA(VB *sim) { OpDef *def; /* Opcode descriptor */ VBInstruction inst; /* Instruction descriptor */ /* First invocation */ - if (vb->cpu.step == 0 && vb->cpu.exception == 0) { + if (sim->cpu.step == 0 && sim->cpu.exception == 0) { /* Call the breakpoint handler */ - if (vb->onExecute != NULL) { + if (sim->onExecute != NULL) { /* Query the application */ - inst.address = vb->cpu.pc; - inst.code[0] = vb->cpu.inst.code[0]; - inst.code[1] = vb->cpu.inst.code[1]; - inst.size = vb->cpu.inst.size; - if (vb->onExecute(vb, &inst)) + inst.address = sim->cpu.pc; + inst.code[0] = sim->cpu.inst.code[0]; + inst.code[1] = sim->cpu.inst.code[1]; + inst.size = sim->cpu.inst.size; + if (sim->onExecute(sim, &inst)) return 1; /* Apply changes */ - vb->cpu.inst.code[0] = inst.code[0]; - vb->cpu.inst.code[1] = inst.code[1]; - vb->cpu.inst.size = inst.size; - vb->cpu.inst.def = - (OpDef *) &OPDEFS[vb->cpu.inst.code[0] >> 10 & 63]; + sim->cpu.inst.code[0] = inst.code[0]; + sim->cpu.inst.code[1] = inst.code[1]; + sim->cpu.inst.size = inst.size; + sim->cpu.inst.def = + (OpDef *) &OPDEFS[sim->cpu.inst.code[0] >> 10 & 63]; } /* Detect non-bit string instruction */ - if ((vb->cpu.inst.code[0] & 0xFC00) != 0x7C00) - vb->cpu.bitstring = 0; + if ((sim->cpu.inst.code[0] & 0xFC00) != 0x7C00) + sim->cpu.bitstring = 0; } /* Processing before updating simulation state */ - def = vb->cpu.inst.def; + def = sim->cpu.inst.def; for (;;) { - if (def->executeA(vb)) + if (def->executeA(sim)) return 1; - vb->cpu.step = 0; + sim->cpu.step = 0; /* Advance to exception processing */ - if (vb->cpu.exception == 0 || def == &OPDEF_EXCEPTION) + if (sim->cpu.exception == 0 || def == &OPDEF_EXCEPTION) break; def = (OpDef *) &OPDEF_EXCEPTION; - cpuException(vb); + cpuException(sim); } /* Advance to execute B */ - vb->cpu.stage = CPU_EXECUTE_B; + sim->cpu.stage = CPU_EXECUTE_B; return 0; } /* Execute: Post-processing, updates state */ -static void cpuExecuteB(VB *vb) { +static void cpuExecuteB(VB *sim) { /* Perform the operation and update state */ - ((OpDef *) vb->cpu.inst.def)->executeB(vb); - vb->cpu.program[0] = 0; + ((OpDef *) sim->cpu.inst.def)->executeB(sim); + sim->cpu.program[0] = 0; /* Advance to next pipeline stage */ - if (vb->cpu.stage == CPU_EXECUTE_B) { - if (cpuCheckIRQs(vb)) - cpuException(vb); - else if (vb->cpu.bitstring != 0) - vb->cpu.stage = CPU_EXECUTE_A; - else vb->cpu.stage = CPU_FETCH; + if (sim->cpu.stage == CPU_EXECUTE_B) { + if (cpuCheckIRQs(sim)) + cpuException(sim); + else if (sim->cpu.bitstring != 0) + sim->cpu.stage = CPU_EXECUTE_A; + else sim->cpu.stage = CPU_FETCH; } } /* Retrieve instruction data from the bus */ -static int cpuFetch(VB *vb) { +static int cpuFetch(VB *sim) { OpDef *def; /* Opcode definition */ /* First fetch */ - if (vb->cpu.step == 0) { - if (cpuReadFetch(vb)) + if (sim->cpu.step == 0) { + if (cpuReadFetch(sim)) return 1; - vb->cpu.inst.def = def = - (OpDef *) &OPDEFS[vb->cpu.inst.code[0] >> 10 & 0x003F]; - vb->cpu.inst.size = def->size << 1; - vb->cpu.step = 1; - } else def = (OpDef *) vb->cpu.inst.def; + sim->cpu.inst.def = def = + (OpDef *) &OPDEFS[sim->cpu.inst.code[0] >> 10 & 0x003F]; + sim->cpu.inst.size = def->size << 1; + sim->cpu.step = 1; + } else def = (OpDef *) sim->cpu.inst.def; /* Second fetch */ - for (; vb->cpu.step < def->size; vb->cpu.step++) { - if (cpuReadFetch(vb)) + for (; sim->cpu.step < def->size; sim->cpu.step++) { + if (cpuReadFetch(sim)) return 1; } /* Advance to execute A */ - vb->cpu.stage = CPU_EXECUTE_A; - vb->cpu.step = 0; + sim->cpu.stage = CPU_EXECUTE_A; + sim->cpu.step = 0; return 0; } @@ -1585,23 +1585,23 @@ static int cpuFetch(VB *vb) { /***************************** Module Functions ******************************/ /* Process a simulation for a given number of clocks */ -static int cpuEmulate(VB *vb, uint32_t clocks) { +static int cpuEmulate(VB *sim, uint32_t clocks) { /* Process all clocks */ for (;;) { /* Processing by pipeline stage */ - switch (vb->cpu.stage) { + switch (sim->cpu.stage) { /* Fetch: Retrive instruction code from memory */ case CPU_FETCH: - if (cpuFetch(vb)) + if (cpuFetch(sim)) return 1; break; /* Execute A: Check for exceptions, configure CPU clocks */ case CPU_EXECUTE_A: - if (cpuExecuteA(vb)) + if (cpuExecuteA(sim)) return 1; break; @@ -1609,22 +1609,22 @@ static int cpuEmulate(VB *vb, uint32_t clocks) { case CPU_EXECUTE_B: /* Clocks remaining exceeds emulation clocks */ - if (clocks < vb->cpu.clocks) { - vb->cpu.clocks -= clocks; + if (clocks < sim->cpu.clocks) { + sim->cpu.clocks -= clocks; return 0; } /* Update simulation state */ - clocks -= vb->cpu.clocks; - vb->cpu.clocks = 0; - cpuExecuteB(vb); + clocks -= sim->cpu.clocks; + sim->cpu.clocks = 0; + cpuExecuteB(sim); break; /* Halt: Wait for an interrupt */ case CPU_HALT: - if (!cpuCheckIRQs(vb)) + if (!cpuCheckIRQs(sim)) return 0; - cpuException(vb); + cpuException(sim); break; /* Fatal exception: Cannot recover */ @@ -1639,9 +1639,9 @@ static int cpuEmulate(VB *vb, uint32_t clocks) { } /* Compute clocks without breakpoint or state change */ -static int cpuUntil(VB *vb, uint32_t clocks) { - return vb->cpu.stage == CPU_HALT || vb->cpu.stage == CPU_FATAL ? - clocks : Min(vb->cpu.clocks, clocks); +static int cpuUntil(VB *sim, uint32_t clocks) { + return sim->cpu.stage == CPU_HALT || sim->cpu.stage == CPU_FATAL ? + clocks : Min(sim->cpu.clocks, clocks); } diff --git a/core/vb.c b/core/vb.c index 22ab713..f2996a6 100644 --- a/core/vb.c +++ b/core/vb.c @@ -38,15 +38,15 @@ static uint32_t Min(uint32_t a, uint32_t b) { /***************************** Module Functions ******************************/ /* Process a simulation for a given number of clocks */ -static int sysEmulate(VB *vb, uint32_t clocks) { +static int sysEmulate(VB *sim, uint32_t clocks) { return - cpuEmulate(vb, clocks) + cpuEmulate(sim, clocks) ; } /* Determine how many clocks can be simulated without a breakpoint */ -static uint32_t sysUntil(VB *vb, uint32_t clocks) { - clocks = cpuUntil(vb, clocks); +static uint32_t sysUntil(VB *sim, uint32_t clocks) { + clocks = cpuUntil(sim, clocks); return clocks; } @@ -55,21 +55,21 @@ static uint32_t sysUntil(VB *vb, uint32_t clocks) { /************************************ API ************************************/ /* Process a simulation */ -int vbEmulate(VB *vb, uint32_t *clocks) { +int vbEmulate(VB *sim, uint32_t *clocks) { int brk; /* A break was requested */ uint32_t until; /* Number of clocks during which no break will occur */ /* Process all clocks */ for (brk = 0; *clocks != 0 && !brk; *clocks -= until) { - until = sysUntil (vb, *clocks); - brk = sysEmulate(vb, until ); + until = sysUntil (sim, *clocks); + brk = sysEmulate(sim, until ); } return brk; } /* Process multiple simulations */ -int vbEmulateEx(VB **vbs, int count, uint32_t *clocks) { +int vbEmulateEx(VB **sims, int count, uint32_t *clocks) { int brk; /* A break was requested */ uint32_t until; /* Number of clocks during which no break will occur */ int x; /* Iterator */ @@ -78,160 +78,160 @@ int vbEmulateEx(VB **vbs, int count, uint32_t *clocks) { for (brk = 0; *clocks != 0 && !brk; *clocks -= until) { until = *clocks; for (x = 0; x < count; x++) - until = sysUntil (vbs[x], until); + until = sysUntil (sims[x], until); for (x = 0; x < count; x++) - brk |= sysEmulate(vbs[x], until); + brk |= sysEmulate(sims[x], until); } return brk; } /* Retrieve a current breakpoint handler */ -void* vbGetCallback(VB *vb, int id) { +void* vbGetCallback(VB *sim, int id) { switch (id) { - case VB_ONEXCEPTION: return *(void **)&vb->onException; - case VB_ONEXECUTE : return *(void **)&vb->onExecute; - case VB_ONFETCH : return *(void **)&vb->onFetch; - case VB_ONREAD : return *(void **)&vb->onRead; - case VB_ONWRITE : return *(void **)&vb->onWrite; + case VB_ONEXCEPTION: return *(void **)&sim->onException; + case VB_ONEXECUTE : return *(void **)&sim->onExecute; + case VB_ONFETCH : return *(void **)&sim->onFetch; + case VB_ONREAD : return *(void **)&sim->onRead; + case VB_ONWRITE : return *(void **)&sim->onWrite; } return NULL; } /* Retrieve the value of a register */ -int32_t vbGetRegister(VB *vb, int type, int id) { +int32_t vbGetRegister(VB *sim, int type, int id) { switch (type) { case VB_PROGRAM: - return id < 0 || id > 31 ? 0 : vb->cpu.program[id]; + return id < 0 || id > 31 ? 0 : sim->cpu.program[id]; case VB_SYSTEM: - return cpuGetSystemRegister(vb, id); + return cpuGetSystemRegister(sim, id); case VB_OTHER: switch (id) { - case VB_PC: return vb->cpu.pc; + case VB_PC: return sim->cpu.pc; } } return 0; /* Invalid type */ } /* Retrieve a handle to the current cartridge ROM data */ -uint8_t* vbGetROM(VB *vb, uint32_t *size) { +uint8_t* vbGetROM(VB *sim, uint32_t *size) { if (size != NULL) - *size = vb->cart.romSize; - return vb->cart.rom; + *size = sim->cart.romSize; + return sim->cart.rom; } /* Retrieve a handle to the current cartridge RAM data */ -uint8_t* vbGetSRAM(VB *vb, uint32_t *size) { +uint8_t* vbGetSRAM(VB *sim, uint32_t *size) { if (size != NULL) - *size = vb->cart.ramSize; - return vb->cart.ram; + *size = sim->cart.ramSize; + return sim->cart.ram; } /* Prepare a simulation instance for use */ -void vbInit(VB *vb) { +void vbInit(VB *sim) { /* Breakpoint handlers */ - vb->onException = NULL; - vb->onExecute = NULL; - vb->onFetch = NULL; - vb->onRead = NULL; - vb->onWrite = NULL; + sim->onException = NULL; + sim->onExecute = NULL; + sim->onFetch = NULL; + sim->onRead = NULL; + sim->onWrite = NULL; /* Game pak */ - vb->cart.ram = NULL; - vb->cart.ramSize = 0; - vb->cart.rom = NULL; - vb->cart.romSize = 0; + sim->cart.ram = NULL; + sim->cart.ramSize = 0; + sim->cart.rom = NULL; + sim->cart.romSize = 0; /* Hardware reset */ - vbReset(vb); + vbReset(sim); } /* Read a value from memory */ -int32_t vbRead(VB *vb, uint32_t address, int type) { - return busRead(vb, address, type); +int32_t vbRead(VB *sim, uint32_t address, int type) { + return busRead(sim, address, type); } /* Read multiple bytes from memory */ -void vbReadEx(VB *vb, uint32_t address, uint8_t *buffer, uint32_t length) { - while (length--) *buffer++ = busRead(vb, address++, VB_U8); +void vbReadEx(VB *sim, uint32_t address, uint8_t *buffer, uint32_t length) { + while (length--) *buffer++ = busRead(sim, address++, VB_U8); } /* Simulate a hardware reset */ -void vbReset(VB *vb) { +void vbReset(VB *sim) { int x; /* Iterator */ /* Reset WRAM (the hardware does not do this) */ for (x = 0; x < 0x10000; x++) - vb->wram[x] = 0x00; + sim->wram[x] = 0x00; /* CPU (normal) */ - vb->cpu.pc = 0xFFFFFFF0; - cpuSetSystemRegister(vb, VB_ECR, 0x0000FFF0, 1); - cpuSetSystemRegister(vb, VB_PSW, 0x00008000, 1); + sim->cpu.pc = 0xFFFFFFF0; + cpuSetSystemRegister(sim, VB_ECR, 0x0000FFF0, 1); + cpuSetSystemRegister(sim, VB_PSW, 0x00008000, 1); for (x = 0; x < 5; x++) - vb->cpu.irq[x] = 0; + sim->cpu.irq[x] = 0; /* CPU (extra, hardware doesn't do this) */ - vb->cpu.adtre = 0x00000000; - vb->cpu.eipc = 0x00000000; - vb->cpu.eipsw = 0x00000000; - vb->cpu.fepc = 0x00000000; - vb->cpu.fepsw = 0x00000000; - vb->cpu.sr29 = 0x00000000; - vb->cpu.sr31 = 0x00000000; - cpuSetSystemRegister(vb, VB_CHCW, 0x00000000, 1); + sim->cpu.adtre = 0x00000000; + sim->cpu.eipc = 0x00000000; + sim->cpu.eipsw = 0x00000000; + sim->cpu.fepc = 0x00000000; + sim->cpu.fepsw = 0x00000000; + sim->cpu.sr29 = 0x00000000; + sim->cpu.sr31 = 0x00000000; + cpuSetSystemRegister(sim, VB_CHCW, 0x00000000, 1); for (x = 0; x < 32; x++) - vb->cpu.program[x] = 0x00000000; + sim->cpu.program[x] = 0x00000000; /* CPU (internal) */ - vb->cpu.bitstring = 0; - vb->cpu.clocks = 0; - vb->cpu.exception = 0; - vb->cpu.stage = CPU_FETCH; - vb->cpu.step = 0; + sim->cpu.bitstring = 0; + sim->cpu.clocks = 0; + sim->cpu.exception = 0; + sim->cpu.stage = CPU_FETCH; + sim->cpu.step = 0; } /* Specify a breakpoint handler */ -void* vbSetCallback(VB *vb, int id, void *proc) { - void *prev = vbGetCallback(vb, id); +void* vbSetCallback(VB *sim, int id, void *proc) { + void *prev = vbGetCallback(sim, id); switch (id) { - case VB_ONEXCEPTION: *(void **)&vb->onException = proc; break; - case VB_ONEXECUTE : *(void **)&vb->onExecute = proc; break; - case VB_ONFETCH : *(void **)&vb->onFetch = proc; break; - case VB_ONREAD : *(void **)&vb->onRead = proc; break; - case VB_ONWRITE : *(void **)&vb->onWrite = proc; break; + case VB_ONEXCEPTION: *(void **)&sim->onException = proc; break; + case VB_ONEXECUTE : *(void **)&sim->onExecute = proc; break; + case VB_ONFETCH : *(void **)&sim->onFetch = proc; break; + case VB_ONREAD : *(void **)&sim->onRead = proc; break; + case VB_ONWRITE : *(void **)&sim->onWrite = proc; break; } return prev; } /* Specify a value for a register */ -int32_t vbSetRegister(VB *vb, int type, int id, int32_t value) { +int32_t vbSetRegister(VB *sim, int type, int id, int32_t value) { switch (type) { case VB_PROGRAM: - return id < 1 || id > 31 ? 0 : (vb->cpu.program[id] = value); + return id < 1 || id > 31 ? 0 : (sim->cpu.program[id] = value); case VB_SYSTEM: - return cpuSetSystemRegister(vb, id, value, 1); + return cpuSetSystemRegister(sim, id, value, 1); case VB_OTHER: switch (id) { case VB_PC: - vb->cpu.bitstring = 0; - vb->cpu.clocks = 0; - vb->cpu.exception = 0; - vb->cpu.stage = CPU_FETCH; - return vb->cpu.pc = value & 0xFFFFFFFE; + sim->cpu.bitstring = 0; + sim->cpu.clocks = 0; + sim->cpu.exception = 0; + sim->cpu.stage = CPU_FETCH; + return sim->cpu.pc = value & 0xFFFFFFFE; } } return 0; /* Invalid type or ID */ } /* Specify a cartridge ROM buffer */ -int vbSetROM(VB *vb, uint8_t *data, uint32_t size) { +int vbSetROM(VB *sim, uint8_t *data, uint32_t size) { /* Specifying no ROM */ if (data == NULL) { - vb->cart.rom = NULL; - vb->cart.romSize = 0; + sim->cart.rom = NULL; + sim->cart.romSize = 0; return 0; } @@ -243,18 +243,18 @@ int vbSetROM(VB *vb, uint8_t *data, uint32_t size) { ) return 1; /* Register the ROM data */ - vb->cart.rom = data; - vb->cart.romSize = size; + sim->cart.rom = data; + sim->cart.romSize = size; return 0; } /* Specify a cartridge RAM buffer */ -int vbSetSRAM(VB *vb, uint8_t *data, uint32_t size) { +int vbSetSRAM(VB *sim, uint8_t *data, uint32_t size) { /* Specifying no SRAM */ if (data == NULL) { - vb->cart.ram = NULL; - vb->cart.ramSize = 0; + sim->cart.ram = NULL; + sim->cart.ramSize = 0; return 0; } @@ -266,17 +266,17 @@ int vbSetSRAM(VB *vb, uint8_t *data, uint32_t size) { ) return 1; /* Register the SRAM data */ - vb->cart.ram = data; - vb->cart.ramSize = size; + sim->cart.ram = data; + sim->cart.ramSize = size; return 0; } /* Write a value to memory */ -void vbWrite(VB *vb, uint32_t address, int type, int32_t value) { - busWrite(vb, address, type, value, 1); +void vbWrite(VB *sim, uint32_t address, int type, int32_t value) { + busWrite(sim, address, type, value, 1); } /* Write multiple values to memory */ -void vbWriteEx(VB *vb, uint32_t address, uint8_t *buffer, uint32_t length) { - while (length--) busWrite(vb, address++, VB_U8, *buffer++, 1); +void vbWriteEx(VB *sim, uint32_t address, uint8_t *buffer, uint32_t length) { + while (length--) busWrite(sim, address++, VB_U8, *buffer++, 1); } diff --git a/core/vb.h b/core/vb.h index 49afac9..0c47276 100644 --- a/core/vb.h +++ b/core/vb.h @@ -195,22 +195,22 @@ struct VB { /************************************ API ************************************/ -VBAPI int vbEmulate (VB *vb, uint32_t *clocks); -VBAPI int vbEmulateEx (VB **vbs, int count, uint32_t *clocks); -VBAPI void* vbGetCallback(VB *vb, int id); -VBAPI int32_t vbGetRegister(VB *vb, int type, int id); -VBAPI uint8_t* vbGetROM (VB *vb, uint32_t *size); -VBAPI uint8_t* vbGetSRAM (VB *vb, uint32_t *size); -VBAPI void vbInit (VB *vb); -VBAPI int32_t vbRead (VB *vb, uint32_t address, int type); -VBAPI void vbReadEx (VB *vb, uint32_t address, uint8_t *buffer, uint32_t length); -VBAPI void vbReset (VB *vb); -VBAPI void* vbSetCallback(VB *vb, int id, void *proc); -VBAPI int32_t vbSetRegister(VB *vb, int type, int id, int32_t value); -VBAPI int vbSetROM (VB *vb, uint8_t *data, uint32_t size); -VBAPI int vbSetSRAM (VB *vb, uint8_t *data, uint32_t size); -VBAPI void vbWrite (VB *vb, uint32_t address, int type, int32_t value); -VBAPI void vbWriteEx (VB *vb, uint32_t address, uint8_t *buffer, uint32_t length); +VBAPI int vbEmulate (VB *sim, uint32_t *clocks); +VBAPI int vbEmulateEx (VB **sims, int count, uint32_t *clocks); +VBAPI void* vbGetCallback(VB *sim, int id); +VBAPI int32_t vbGetRegister(VB *sim, int type, int id); +VBAPI uint8_t* vbGetROM (VB *sim, uint32_t *size); +VBAPI uint8_t* vbGetSRAM (VB *sim, uint32_t *size); +VBAPI void vbInit (VB *sim); +VBAPI int32_t vbRead (VB *sim, uint32_t address, int type); +VBAPI void vbReadEx (VB *sim, uint32_t address, uint8_t *buffer, uint32_t length); +VBAPI void vbReset (VB *sim); +VBAPI void* vbSetCallback(VB *sim, int id, void *proc); +VBAPI int32_t vbSetRegister(VB *sim, int type, int id, int32_t value); +VBAPI int vbSetROM (VB *sim, uint8_t *data, uint32_t size); +VBAPI int vbSetSRAM (VB *sim, uint8_t *data, uint32_t size); +VBAPI void vbWrite (VB *sim, uint32_t address, int type, int32_t value); +VBAPI void vbWriteEx (VB *sim, uint32_t address, uint8_t *buffer, uint32_t length); diff --git a/web/core/Core.js b/web/core/Core.js index ae8bfe8..70c2aa9 100644 --- a/web/core/Core.js +++ b/web/core/Core.js @@ -147,7 +147,7 @@ class Core { } // Retrieve the value of a program register - getSystemRegister(sim, id, options) { + getProgramRegister(sim, id, options) { return this.message({ command: "getProgramRegister", id : id,