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Backporting from concurrent project

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GuyPerfect
2023-03-19 18:15:55 -05:00
parent 386f4a904f
commit 77c256f2e0
12 changed files with 342 additions and 300 deletions
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core/cpu.c
+18 -18
View File
@@ -483,7 +483,7 @@ static int exaFloating1(VB *sim) {
/* Reserved operand */
reg1 = sim->cpu.program[sim->cpu.inst.code[0] & 31];
if (cpuFRO(reg1)) {
sim->cpu.fp_flags = 0x00000200; /* FRO */
sim->cpu.fpFlags = 0x00000200; /* FRO */
sim->cpu.exception = 0xFF60;
return 0;
}
@@ -506,7 +506,7 @@ static int exaFloating1(VB *sim) {
/* Invalid operation */
if (bits > 7) {
sim->cpu.fp_flags = 0x00000100; /* FIV */
sim->cpu.fpFlags = 0x00000100; /* FIV */
sim->cpu.exception = 0xFF70;
return 0;
}
@@ -529,7 +529,7 @@ static int exaFloating1(VB *sim) {
result = -result;
/* Stage updates */
sim->cpu.fp_flags = result==*(float *)&reg1 ? 0 : 0x00000010; /* FPR */
sim->cpu.fpFlags = result==*(float *)&reg1 ? 0 : 0x00000010; /* FPR */
sim->cpu.inst.aux[0] = result;
sim->cpu.inst.aux[1] = subop;
sim->cpu.clocks += ((OpDef *) sim->cpu.inst.def)->aux;
@@ -549,7 +549,7 @@ static int exaFloating2(VB *sim) {
reg1 = sim->cpu.program[sim->cpu.inst.code[0] & 31];
reg2 = sim->cpu.program[sim->cpu.inst.code[0] >> 5 & 31];
if (cpuFRO(reg1) || cpuFRO(reg2)) {
sim->cpu.fp_flags = 0x00000200; /* FRO */
sim->cpu.fpFlags = 0x00000200; /* FRO */
sim->cpu.exception = 0xFF60;
return 0;
}
@@ -564,14 +564,14 @@ static int exaFloating2(VB *sim) {
bits = 0x7F7FFFFF; /* Maximum value */
test = *(float *)&bits;
if (aux->f64 > test || aux->f64 < -test) {
sim->cpu.fp_flags = 0x00000040; /* FOV */
sim->cpu.fpFlags = 0x00000040; /* FOV */
sim->cpu.exception = 0xFF64;
return 0;
}
/* Process result */
bits = *(int32_t *)&aux->f32;
sim->cpu.fp_flags = 0;
bits = *(int32_t *)&aux->f32;
sim->cpu.fpFlags = 0;
/* Zero */
if ((bits & 0x7FFFFFFF) == 0x00000000)
@@ -579,13 +579,13 @@ static int exaFloating2(VB *sim) {
/* Underflow */
else if ((bits & 0x7F800000) == 0x00000000) {
sim->cpu.fp_flags = 0x00000020; /* FUD */
aux->f32 = bits = 0;
sim->cpu.fpFlags = 0x00000020; /* FUD */
aux->f32 = bits = 0;
}
/* Precision degradation */
if (aux->f32 != aux->f64)
sim->cpu.fp_flags |= 0x00000010; /* FPR */
sim->cpu.fpFlags |= 0x00000010; /* FPR */
/* Other state */
sim->cpu.inst.aux[0] = bits;
@@ -770,10 +770,10 @@ static void exbException(VB *sim) {
int x; /* Iterator */
/* Apply staged floating-point flags */
if (sim->cpu.fp_flags != 0) {
cpuSetSystemRegister(sim, VB_PSW, sim->cpu.fp_flags |
if (sim->cpu.fpFlags != 0) {
cpuSetSystemRegister(sim, VB_PSW, sim->cpu.fpFlags |
cpuGetSystemRegister(sim, VB_PSW), 0);
sim->cpu.fp_flags = 0;
sim->cpu.fpFlags = 0;
}
/* Fatal exception */
@@ -826,10 +826,10 @@ static void exbFloating(VB *sim) {
int32_t subop = sim->cpu.inst.aux[1]; /* Sub-opcode */
/* Apply staged floating-point flags */
if (sim->cpu.fp_flags != 0) {
cpuSetSystemRegister(sim, VB_PSW, sim->cpu.fp_flags |
if (sim->cpu.fpFlags != 0) {
cpuSetSystemRegister(sim, VB_PSW, sim->cpu.fpFlags |
cpuGetSystemRegister(sim, VB_PSW), 0);
sim->cpu.fp_flags = 0;
sim->cpu.fpFlags = 0;
}
/* Update state */
@@ -985,13 +985,13 @@ static void opDIVF_S(VB *sim, int32_t *dest, int32_t src) {
/* Invalid operation */
if (src == 0) {
sim->cpu.fp_flags = 0x00000100; /* FIV */
sim->cpu.fpFlags = 0x00000100; /* FIV */
sim->cpu.exception = 0xFF70;
}
/* Zero division */
else {
sim->cpu.fp_flags = 0x00000080; /* FZD */
sim->cpu.fpFlags = 0x00000080; /* FZD */
sim->cpu.exception = 0xFF68;
}
core/vb.h
+1 -1
View File
@@ -172,7 +172,7 @@ struct VB {
/* Other state */
uint32_t clocks; /* Clocks until next activity */
uint32_t fp_flags; /* Floating-point exception flags */
uint32_t fpFlags; /* Floating-point exception flags */
uint16_t exception; /* Current exception cause code */
uint8_t irq[5]; /* Interrupt requests */
uint8_t bitstring; /* Processing a bit string instruction */