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Introducing CPU register lists

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This commit is contained in:
GuyPerfect
2020-08-06 16:37:05 -05:00
parent 2e38c1fa49
commit 7d8d33158f
17 changed files with 890 additions and 98 deletions
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src/core/bus.c
+7
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@@ -69,6 +69,13 @@ static int32_t busReadValue(VUE *vue, uint32_t address, int type) {
return 0; /* Unreachable */
}
/* Perform a system reset */
static void busReset(VUE *vue) {
int x;
for (x = 0; x < 0x10000; x++)
vue->bus.wram[x] = 0;
}
/* Write bytes to host memory */
static void busWriteBytes(uint8_t *dest, uint8_t *src, uint32_t address,
uint32_t size, uint32_t length) {
src/core/cpu.c
+17 -8
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@@ -90,6 +90,13 @@ static int32_t cpuSetSystemRegister(VUE *vue, int index, int32_t value,
return vue->cpu.chcw_ice << 1;
case VUE_ECR:
if (debug) {
vue->cpu.ecr_fecc = value >> 16 & 0xFFFF;
vue->cpu.ecr_eicc = value & 0xFFFF;
}
return vue->cpu.ecr_fecc << 16 | vue->cpu.ecr_eicc;
case VUE_PSW :
vue->cpu.psw_i = value >> 16 & 15;
vue->cpu.psw_np = value >> 15 & 1;
@@ -109,16 +116,16 @@ static int32_t cpuSetSystemRegister(VUE *vue, int index, int32_t value,
return value & 0x000FF3FF;
/* Remaining cases to encourage tableswitch */
case 4: case 6: case 7: case 8: case 9: case 10: case 11:
case 12: case 13: case 14: case 15: case 16: case 17: case 18:
case 19: case 20: case 21: case 22: case 23: case 26: case 27:
case 28: case 30:
case 6: case 7: case 8: case 9: case 10: case 11: case 12:
case 13: case 14: case 15: case 16: case 17: case 18: case 19:
case 20: case 21: case 22: case 23: case 26: case 27: case 28:
case 30:
return 0;
}
return 1; /* Unreachable */
}
/* System reset */
/* Perform a system reset */
static void cpuReset(VUE *vue) {
int x;
@@ -127,15 +134,17 @@ static void cpuReset(VUE *vue) {
vue->cpu.fetch = 0;
vue->cpu.stage = CPU_FETCH;
/* Reset program counter */
vue->cpu.pc = 0xFFFFFFF0;
/* Clear all registers (hardware only sets ECR, PC and PSW) */
for (x = 0; x < 32; x++) {
vue->cpu.program[x] = 0;
cpuSetSystemRegister(vue, x, 0, VUE_TRUE);
}
/* Configure registers */
vue->cpu.ecr_eicc = 0xFFF0;
vue->cpu.lastPC = 0xFFFFFFF0;
vue->cpu.pc = 0xFFFFFFF0;
vue->cpu.psw_np = 1;
}
/* Test a condition */
src/core/include/vue.h
+18 -9
View File
@@ -43,6 +43,13 @@ extern "C" {
#define VUE_PSW 5
#define VUE_TKCW 7
/* Program register indexes */
#define VUE_GP 4
#define VUE_HP 2
#define VUE_LP 31
#define VUE_SP 3
#define VUE_TP 5
/*****************************************************************************
@@ -68,6 +75,7 @@ typedef struct {
struct {
uint32_t cycles; /* Cycles until next stage */
int fetch; /* Fetch unit index */
int32_t lastPC; /* Previous value of PC */
int stage; /* Current processing stage */
/* Program registers */
@@ -101,17 +109,17 @@ typedef struct {
int8_t psw_z; /* Zero */
/* Cache Control Word */
int32_t chcw_cec; /* Clear Entry Count */
int32_t chcw_cen; /* Clear Entry Number */
int8_t chcw_icc; /* Instruction Cache Clear */
int8_t chcw_icd; /* Instruction Cache Dump */
int8_t chcw_ice; /* Instruction Cache Enable */
int8_t chcw_icr; /* Instruction Cache Restore */
int32_t chcw_sa; /* Spill-Out Base Address */
uint16_t chcw_cec; /* Clear Entry Count */
uint16_t chcw_cen; /* Clear Entry Number */
int8_t chcw_icc; /* Instruction Cache Clear */
int8_t chcw_icd; /* Instruction Cache Dump */
int8_t chcw_ice; /* Instruction Cache Enable */
int8_t chcw_icr; /* Instruction Cache Restore */
int32_t chcw_sa; /* Spill-Out Base Address */
/* Exception Cause Register */
int8_t ecr_eicc; /* Exception/Interrupt Cause Code */
int8_t ecr_fecc; /* Fatal Error Cause Code */
uint16_t ecr_eicc; /* Exception/Interrupt Cause Code */
uint16_t ecr_fecc; /* Fatal Error Cause Code */
} cpu;
} VUE;
@@ -125,6 +133,7 @@ typedef struct {
VUEAPI int32_t vueGetRegister(VUE *vue, int index, vbool system);
VUEAPI void vueInitialize (VUE *vue);
VUEAPI vbool vueRead (VUE *vue, uint32_t address, uint8_t *dest, uint32_t length);
VUEAPI void vueReset (VUE *vue);
VUEAPI int32_t vueSetRegister(VUE *vue, int index, vbool system, int32_t value);
VUEAPI vbool vueSetROM (VUE *vue, uint8_t *rom, uint32_t size);
VUEAPI vbool vueWrite (VUE *vue, uint32_t address, uint8_t *src, uint32_t length);
src/core/vue.c
+13 -4
View File
@@ -2,7 +2,6 @@
#include <vue.h>
/*****************************************************************************
* Constants *
*****************************************************************************/
@@ -27,7 +26,7 @@ static const int TYPE_SIZES[] = { 1, 1, 2, 2, 4 };
/* Retrieve the value of a register */
int32_t vueGetRegister(VUE *vue, int index, vbool system) {
return
return vue == NULL ? 0 :
index == VUE_PC && system ? vue->cpu.pc :
index < 0 || index > 31 ? 0 :
system ? cpuGetSystemRegister(vue, index) :
@@ -37,6 +36,8 @@ int32_t vueGetRegister(VUE *vue, int index, vbool system) {
/* Prepare an emulation state context for use */
void vueInitialize(VUE *vue) {
if (vue == NULL)
return;
vue->bus.rom = NULL;
vue->bus.sram = NULL;
}
@@ -79,13 +80,21 @@ vbool vueRead(VUE *vue, uint32_t address, uint8_t *dest, uint32_t length) {
return VUE_TRUE;
}
/* Initialize all system components */
void vueReset(VUE *vue) {
if (vue == NULL)
return;
busReset(vue);
cpuReset(vue);
}
/* Specify a value for a register */
int32_t vueSetRegister(VUE *vue, int index, vbool system, int32_t value) {
return
return vue == NULL ? 0 :
index == VUE_PC && system ? vue->cpu.pc = value & 0xFFFFFFFE :
index < 0 || index > 31 ? 0 :
system ? cpuSetSystemRegister(vue, index, value, VUE_TRUE) :
index == 0 ? 0 : vue->cpu.program[index]
index == 0 ? 0 : (vue->cpu.program[index] = value)
;
}