Implement halt, exception, fatal
This commit is contained in:
parent
7c25a4ac93
commit
bfc2254b9e
465
core/cpu.c
465
core/cpu.c
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@ -125,6 +125,12 @@ static const uint8_t INST_LENGTHS[] = {
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2, 2, 1, 2, 2, 2, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2
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};
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/* Highest interrupt level by IRQ bit mask value */
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static const int8_t IRQ_LEVELS[] = {
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-1, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3,
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4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4
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};
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/********************************** Macros ***********************************/
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@ -195,6 +201,18 @@ static const uint8_t OPDEFS_FLOATENDO[] = {
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/***************************** Callback Handlers *****************************/
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/* Prepare to handle an exception */
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#ifndef VB_DIRECT_EXCEPTION
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#define VB_ON_EXCEPTION sim->onException
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#else
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extern int vbxOnException(VB *, uint16_t *);
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#define VB_ON_EXCEPTION sim->onException
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#endif
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static int cpuOnException(VB *sim, uint16_t *cause) {
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return sim->onException != NULL && VB_ON_EXCEPTION(sim, cause);
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}
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#undef VB_ON_EXCEPTION
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/* Prepare to execute an instruction */
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#ifndef VB_DIRECT_EXECUTE
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#define VB_ON_EXECUTE sim->onExecute
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@ -202,7 +220,7 @@ static const uint8_t OPDEFS_FLOATENDO[] = {
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extern int vbxOnExecute(VB *, uint32_t, const uint16_t *, int);
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#define VB_ON_EXECUTE vbxOnExecute
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#endif
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static int cpuExecute(VB *sim) {
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static int cpuOnExecute(VB *sim) {
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return
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sim->onExecute != NULL &&
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VB_ON_EXECUTE(sim, sim->cpu.pc, sim->cpu.code, sim->cpu.length)
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@ -289,160 +307,8 @@ static int cpuWrite(VB *sim, uint32_t address, int type, int32_t value) {
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/****************************** Pipeline Stages ******************************/
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/* Fetch the code bits for the next instruction */
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static int cpuFetch(VB *sim) {
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int32_t value;
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switch (sim->cpu.step) {
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case 0:
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sim->cpu.pc = sim->cpu.nextPC;
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/* Fallthrough */
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case 1:
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/* Retrieve the first code unit */
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if (cpuReadFetch(sim, 0, sim->cpu.pc, &value)) {
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sim->cpu.step = 1;
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return 1;
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}
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/* Update state */
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sim->cpu.code[0] = value;
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sim->cpu.length = INST_LENGTHS[value >> 10 & 63];
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sim->cpu.step = 3 - sim->cpu.length;
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/* Wait any clocks taken */
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if (sim->cpu.clocks != 0)
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return 0;
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/* Skip fetching a second code unit */
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if (sim->cpu.length == 1)
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goto Step3;
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/* Fallthrough */
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case 2:
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/* Retrieve the second code unit */
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if (cpuReadFetch(sim, 1, sim->cpu.pc + 2, &value))
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return 1;
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/* Update state */
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sim->cpu.code[1] = value;
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sim->cpu.step = 3;
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/* Wait any clocks taken */
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if (sim->cpu.clocks != 0)
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return 0;
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/* Fallthrough */
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case 3: Step3:
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/* Prepare to execute the instruction */
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if (cpuExecute(sim))
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return 1;
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/* Select operation definition */
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sim->cpu.operation = OPDEFS[sim->cpu.code[0] >> 10];
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switch (sim->cpu.operation) {
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case CPU_BITSTRING:
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sim->cpu.operation =
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OPDEFS_BITSTRING[sim->cpu.code[0] & 31];
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break;
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case CPU_FLOATENDO:
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sim->cpu.operation =
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OPDEFS_FLOATENDO[sim->cpu.code[1] >> 10];
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}
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/* Update state */
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sim->cpu.step = 0;
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}
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return 0;
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}
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/**************************** Instruction Helpers ****************************/
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/* Parse the immediate 4-bit condition value */
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static int32_t cpuGetCond(VB *sim) {
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return sim->cpu.code[0] >> 9 & 15;
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}
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/* Parse the 9-bit displacement value */
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static int32_t cpuGetDisp9(VB *sim) {
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return SignExtend(sim->cpu.code[0], 9);
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}
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/* Parse the 26-bit displacement value */
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static int32_t cpuGetDisp26(VB *sim) {
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return SignExtend((int32_t) sim->cpu.code[0] << 16 | sim->cpu.code[1], 26);
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}
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/* Parse the immediate 5-bit sign-extended value */
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static int32_t cpuGetImm5S(VB *sim) {
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return SignExtend(sim->cpu.code[0], 5);
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}
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/* Parse the immediate 5-bit zero-filled value */
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static int32_t cpuGetImm5U(VB *sim) {
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return sim->cpu.code[0] & 31;
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}
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/* Parse the immediate 16-bit sign-extended value */
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static int32_t cpuGetImm16S(VB *sim) {
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return SignExtend(sim->cpu.code[1], 16);
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}
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/* Parse the immediate 16-bit zero-filled value */
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static int32_t cpuGetImm16U(VB *sim) {
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return sim->cpu.code[1];
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}
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/* Resolve the operand value for reg1 */
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static int32_t cpuGetReg1(VB *sim) {
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return sim->cpu.program[sim->cpu.code[0] & 31];
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}
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/* Resolve the operand value for reg2 */
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static int32_t cpuGetReg2(VB *sim) {
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return sim->cpu.program[sim->cpu.code[0] >> 5 & 31];
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}
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/* Supply an operand value for reg2 */
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static void cpuSetReg2(VB *sim, int32_t value) {
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int reg2 = sim->cpu.code[0] >> 5 & 31;
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if (reg2 != 0)
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sim->cpu.program[reg2] = value;
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}
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/* Advance to the next instruction */
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static void cpuAdvance(VB *sim, uint32_t clocks) {
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sim->cpu.clocks += clocks;
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sim->cpu.operation = CPU_FETCH;
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sim->cpu.nextPC = sim->cpu.pc + (sim->cpu.length << 1);
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sim->cpu.step = 0;
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}
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/* Interpret floating short bits as word integer bits */
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static int32_t cpuFloatToWord(float x) {
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return *(int32_t *) &x;
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}
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/* Raise an exception */
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static int cpuThrow(VB *sim, uint16_t cause) {
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sim->cpu.exception = cause;
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sim->cpu.operation = CPU_EXCEPTION;
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return 0;
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}
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/* Interpret word integer bits as floating short bits */
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static float cpuWordToFloat(int32_t x) {
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return *(float *) &x;
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}
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/* Retrieve the value of a system register */
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static uint32_t cpuGetSystemRegister(VB *sim, int index) {
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switch (index) {
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@ -528,6 +394,260 @@ static uint32_t cpuSetSystemRegister(VB*sim,
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return 0x00000000; /* All others */
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}
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/* Raise an exception */
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static void cpuThrow(VB *sim, uint16_t cause) {
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sim->cpu.exception = cause;
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sim->cpu.operation = CPU_EXCEPTION;
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sim->cpu.step = 0;
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}
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/* Check for an interrupt request */
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static int cpuIRQ(VB *sim) {
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int level;
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if (sim->cpu.psw.id | sim->cpu.psw.ep | sim->cpu.psw.np)
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return 0;
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level = IRQ_LEVELS[sim->cpu.irq];
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if (level > sim->cpu.psw.i)
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return 0;
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cpuThrow(sim, 0xFE00 | level << 4);
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return 1;
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}
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/****************************** Pipeline Stages ******************************/
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/* Handle an exception */
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static int cpuException(VB *sim) {
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uint16_t cause = sim->cpu.exception;
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/* Invoke the exception callback */
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if (sim->cpu.step == 0 && cpuOnException(sim, &cause))
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return 1;
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/* Fatal exception */
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if (sim->cpu.psw.np) {
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switch (sim->cpu.step) {
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case 0:
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auxData.value = 0xFFFF0000 | cause;
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/* Fallthrough */
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case 1:
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if (cpuWrite(sim, 0x00000000, VB_S32, auxData.value)) {
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sim->cpu.step = 1;
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return 1;
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}
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auxData.value = cpuGetSystemRegister(sim, VB_PSW);
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/* Fallthrough */
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case 2:
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if (cpuWrite(sim, 0x00000004, VB_S32, auxData.value)) {
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sim->cpu.step = 2;
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return 1;
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}
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/* Fallthrough */
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case 3:
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if (cpuWrite(sim, 0x00000008, VB_S32, sim->cpu.pc)) {
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sim->cpu.step = 3;
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return 1;
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}
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}
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/* Enter fatal halting state */
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sim->cpu.halt = 1;
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sim->cpu.operation = CPU_FATAL;
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return 0;
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}
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/* Duplexed exception */
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if (sim->cpu.psw.ep) {
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sim->cpu.ecr.fecc = cause;
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sim->cpu.fepsw = cpuGetSystemRegister(sim, VB_PSW);
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sim->cpu.fepc = sim->cpu.pc;
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sim->cpu.psw.np = 1;
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sim->cpu.nextPC = 0xFFFFFFD0;
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}
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/* Regular exception */
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else {
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/* Interrupts only */
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if ((cause & 0xFF00) == 0xFE00) {
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sim->cpu.psw.i = (cause >> 4 & 7) + 1;
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if (sim->cpu.halt) {
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sim->cpu.halt = 0;
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sim->cpu.pc += 2;
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}
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}
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/* All exceptions */
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sim->cpu.ecr.eicc = cause;
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sim->cpu.eipsw = cpuGetSystemRegister(sim, VB_PSW);
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sim->cpu.eipc = sim->cpu.pc;
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sim->cpu.psw.ep = 1;
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sim->cpu.nextPC = 0xFFFF0000 |
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((cause & 0xFFF0) == 0xFF60 ? 0xFF60 : cause & 0xFFF0);
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}
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/* All exceptions */
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sim->cpu.psw.ae = 0;
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sim->cpu.psw.id = 1;
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sim->cpu.operation = CPU_FETCH;
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/* TODO: Research clocks */
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return 0;
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}
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/* Fetch the code bits for the next instruction */
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static int cpuFetch(VB *sim) {
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int32_t value;
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switch (sim->cpu.step) {
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case 0:
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sim->cpu.pc = sim->cpu.nextPC;
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if (cpuIRQ(sim))
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return 0;
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/* Fallthrough */
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case 1:
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/* Retrieve the first code unit */
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if (cpuReadFetch(sim, 0, sim->cpu.pc, &value)) {
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sim->cpu.step = 1;
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return 1;
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}
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/* Update state */
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sim->cpu.code[0] = value;
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sim->cpu.length = INST_LENGTHS[value >> 10 & 63];
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sim->cpu.step = 3 - sim->cpu.length;
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/* Wait any clocks taken */
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if (sim->cpu.clocks != 0)
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return 0;
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/* Skip fetching a second code unit */
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if (sim->cpu.length == 1)
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goto Step3;
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/* Fallthrough */
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case 2:
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/* Retrieve the second code unit */
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if (cpuReadFetch(sim, 1, sim->cpu.pc + 2, &value))
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return 1;
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/* Update state */
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sim->cpu.code[1] = value;
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sim->cpu.step = 3;
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/* Wait any clocks taken */
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if (sim->cpu.clocks != 0)
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return 0;
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/* Fallthrough */
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case 3: Step3:
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/* Prepare to execute the instruction */
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if (cpuOnExecute(sim))
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return 1;
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/* Select operation definition */
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sim->cpu.operation = OPDEFS[sim->cpu.code[0] >> 10];
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switch (sim->cpu.operation) {
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case CPU_BITSTRING:
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sim->cpu.operation =
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OPDEFS_BITSTRING[sim->cpu.code[0] & 31];
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break;
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case CPU_FLOATENDO:
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sim->cpu.operation =
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OPDEFS_FLOATENDO[sim->cpu.code[1] >> 10];
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}
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/* Update state */
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sim->cpu.step = 0;
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}
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return 0;
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}
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/* HALT instruction is pending */
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static int cpuHalt(VB *sim) {
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/* TODO: Research clocks */
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return !cpuIRQ(sim);
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}
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/**************************** Instruction Helpers ****************************/
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/* Parse the immediate 4-bit condition value */
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static int32_t cpuGetCond(VB *sim) {
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return sim->cpu.code[0] >> 9 & 15;
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}
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/* Parse the 9-bit displacement value */
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static int32_t cpuGetDisp9(VB *sim) {
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return SignExtend(sim->cpu.code[0], 9);
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}
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/* Parse the 26-bit displacement value */
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static int32_t cpuGetDisp26(VB *sim) {
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return SignExtend((int32_t) sim->cpu.code[0] << 16 | sim->cpu.code[1], 26);
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}
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/* Parse the immediate 5-bit sign-extended value */
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static int32_t cpuGetImm5S(VB *sim) {
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return SignExtend(sim->cpu.code[0], 5);
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}
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/* Parse the immediate 5-bit zero-filled value */
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static int32_t cpuGetImm5U(VB *sim) {
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return sim->cpu.code[0] & 31;
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}
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/* Parse the immediate 16-bit sign-extended value */
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static int32_t cpuGetImm16S(VB *sim) {
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return SignExtend(sim->cpu.code[1], 16);
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}
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/* Parse the immediate 16-bit zero-filled value */
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static int32_t cpuGetImm16U(VB *sim) {
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return sim->cpu.code[1];
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}
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/* Resolve the operand value for reg1 */
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static int32_t cpuGetReg1(VB *sim) {
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return sim->cpu.program[sim->cpu.code[0] & 31];
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}
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/* Resolve the operand value for reg2 */
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static int32_t cpuGetReg2(VB *sim) {
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return sim->cpu.program[sim->cpu.code[0] >> 5 & 31];
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}
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/* Supply an operand value for reg2 */
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static void cpuSetReg2(VB *sim, int32_t value) {
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int reg2 = sim->cpu.code[0] >> 5 & 31;
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if (reg2 != 0)
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sim->cpu.program[reg2] = value;
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}
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/* Advance to the next instruction */
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static void cpuAdvance(VB *sim, uint32_t clocks) {
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sim->cpu.clocks += clocks;
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sim->cpu.operation = CPU_FETCH;
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sim->cpu.nextPC = sim->cpu.pc + (sim->cpu.length << 1);
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sim->cpu.step = 0;
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}
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/* Interpret floating short bits as word integer bits */
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static int32_t cpuFloatToWord(float x) {
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return *(int32_t *) &x;
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}
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/* Interpret word integer bits as floating short bits */
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static float cpuWordToFloat(int32_t x) {
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return *(float *) &x;
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}
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/* Addition common processing */
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static int32_t cpuAdd(VB *sim, int32_t a, int32_t b) {
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int32_t c = a + b;
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@ -649,7 +769,8 @@ static int32_t cpuShiftLeft(VB *sim, int32_t b) {
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/* Logical right shift common processing */
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static int32_t cpuShiftRight(VB *sim, int32_t b) {
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int32_t a = cpuGetReg2(sim);
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int32_t c = a >> b & (uint32_t) 0xFFFFFFFF << (32 - b);
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int32_t c = b == 0 ? (uint32_t) a :
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a >> b & ~((uint32_t) 0xFFFFFFFF << (32 - b));
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sim->cpu.psw.cy = b == 0 ? 0 : a >> (b - 1) & 1;
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sim->cpu.psw.ov = 0;
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sim->cpu.psw.s = c < 0;
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@ -1087,6 +1208,7 @@ static void cpuMOVHI(VB *sim) {
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/* MPYHW */
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static void cpuMPYHW(VB *sim) {
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cpuSetReg2(sim, cpuGetReg2(sim) * SignExtend(cpuGetReg1(sim), 17));
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cpuAdvance(sim, cpuClocks(9));
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}
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/* MUL */
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@ -1120,14 +1242,14 @@ static void cpuMULF_S(VB *sim) {
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/* MULU */
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static void cpuMULU(VB *sim) {
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uint64_t a = cpuGetReg2(sim);
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uint64_t b = cpuGetReg1(sim);
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int64_t c = a * b;
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int32_t d = c;
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uint64_t a = (uint32_t) cpuGetReg2(sim);
|
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uint64_t b = (uint32_t) cpuGetReg1(sim);
|
||||
uint64_t c = a * b;
|
||||
uint32_t d = c;
|
||||
sim->cpu.program[30] = c >> 32;
|
||||
cpuSetReg2(sim, d);
|
||||
sim->cpu.psw.ov = d != c;
|
||||
sim->cpu.psw.s = d < 0;
|
||||
sim->cpu.psw.s = (int32_t) d < 0;
|
||||
sim->cpu.psw.z = d == 0;
|
||||
cpuAdvance(sim, 13);
|
||||
}
|
||||
|
|
@ -1195,6 +1317,12 @@ static void cpuSARImm(VB *sim) {
|
|||
cpuAdvance(sim, cpuClocks(1));
|
||||
}
|
||||
|
||||
/* SAR register */
|
||||
static void cpuSARReg(VB *sim) {
|
||||
cpuSetReg2(sim, cpuShiftArithmetic(sim, cpuGetReg1(sim) & 31));
|
||||
cpuAdvance(sim, cpuClocks(1));
|
||||
}
|
||||
|
||||
/* SEI */
|
||||
static void cpuSEI(VB *sim) {
|
||||
sim->cpu.psw.id = 1;
|
||||
|
|
@ -1207,19 +1335,13 @@ static void cpuSETF(VB *sim) {
|
|||
cpuAdvance(sim, cpuClocks(1));
|
||||
}
|
||||
|
||||
/* SHR register */
|
||||
static void cpuSARReg(VB *sim) {
|
||||
cpuSetReg2(sim, cpuShiftArithmetic(sim, cpuGetReg1(sim) & 31));
|
||||
cpuAdvance(sim, cpuClocks(1));
|
||||
}
|
||||
|
||||
/* SHL immediate */
|
||||
static void cpuSHLImm(VB *sim) {
|
||||
cpuSetReg2(sim, cpuShiftLeft(sim, cpuGetImm5U(sim)));
|
||||
cpuAdvance(sim, cpuClocks(1));
|
||||
}
|
||||
|
||||
/* SHR register */
|
||||
/* SHL register */
|
||||
static void cpuSHLReg(VB *sim) {
|
||||
cpuSetReg2(sim, cpuShiftLeft(sim, cpuGetReg1(sim) & 31));
|
||||
cpuAdvance(sim, cpuClocks(1));
|
||||
|
|
@ -1282,8 +1404,7 @@ static void cpuSUBF_S(VB *sim) {
|
|||
/* TRAP */
|
||||
static void cpuTRAP(VB *sim) {
|
||||
sim->cpu.clocks += cpuClocks(15);
|
||||
sim->cpu.exception = 0xFFA0 + cpuGetImm5U(sim);
|
||||
sim->cpu.operation = CPU_EXCEPTION;
|
||||
cpuThrow(sim, 0xFFA0 + cpuGetImm5U(sim));
|
||||
}
|
||||
|
||||
/* TRNC.SW */
|
||||
|
|
@ -1361,7 +1482,10 @@ static int cpuEmulate(VB *sim, uint32_t clocks) {
|
|||
|
||||
/* Processing by operation ID */
|
||||
switch (sim->cpu.operation) {
|
||||
case CPU_FETCH: brk = cpuFetch(sim); break;
|
||||
case CPU_EXCEPTION: brk = cpuException(sim); break;
|
||||
case CPU_FATAL : return 0;
|
||||
case CPU_FETCH : brk = cpuFetch (sim); break;
|
||||
case CPU_HALTING : if (cpuHalt(sim)) return 0; break;
|
||||
|
||||
case CPU_ADD_IMM: cpuADDImm (sim); break;
|
||||
case CPU_ADD_REG: cpuADDReg (sim); break;
|
||||
|
|
@ -1441,7 +1565,8 @@ static int cpuEmulate(VB *sim, uint32_t clocks) {
|
|||
|
||||
/* Determine how many clocks are guaranteed to process */
|
||||
static uint32_t cpuUntil(VB *sim, uint32_t clocks) {
|
||||
return sim->cpu.clocks < clocks ? sim->cpu.clocks : clocks;
|
||||
return sim->cpu.halt || sim->cpu.clocks > clocks ?
|
||||
clocks : sim->cpu.clocks;
|
||||
}
|
||||
|
||||
#endif /* VBAPI */
|
||||
|
|
|
|||
15
core/vb.c
15
core/vb.c
|
|
@ -75,6 +75,7 @@ struct VB {
|
|||
uint32_t clocks; /* Master clocks to wait */
|
||||
uint16_t code[2]; /* Instruction code units */
|
||||
uint16_t exception; /* Exception cause code */
|
||||
int halt; /* CPU is halting */
|
||||
uint16_t irq; /* Interrupt request lines */
|
||||
int length; /* Instruction code length */
|
||||
uint32_t nextPC; /* Address of next instruction */
|
||||
|
|
@ -86,6 +87,7 @@ struct VB {
|
|||
uint8_t wram[0x10000]; /* System RAM */
|
||||
|
||||
/* Application data */
|
||||
vbOnException onException; /* CPU exception */
|
||||
vbOnExecute onExecute; /* CPU instruction execute */
|
||||
vbOnFetch onFetch; /* CPU instruction fetch */
|
||||
vbOnRead onRead; /* CPU instruction read */
|
||||
|
|
@ -185,6 +187,11 @@ VBAPI void* vbGetCartROM(VB *sim, uint32_t *size) {
|
|||
return sim->cart.rom;
|
||||
}
|
||||
|
||||
/* Retrieve the exception callback handle */
|
||||
VBAPI vbOnException vbGetExceptionCallback(VB *sim) {
|
||||
return sim->onException;
|
||||
}
|
||||
|
||||
/* Retrieve the execute callback handle */
|
||||
VBAPI vbOnExecute vbGetExecuteCallback(VB *sim) {
|
||||
return sim->onExecute;
|
||||
|
|
@ -256,6 +263,7 @@ VBAPI VB* vbReset(VB *sim) {
|
|||
|
||||
/* CPU (normal) */
|
||||
sim->cpu.exception = 0;
|
||||
sim->cpu.halt = 0;
|
||||
sim->cpu.irq = 0;
|
||||
sim->cpu.pc = 0xFFFFFFF0;
|
||||
cpuSetSystemRegister(sim, VB_ECR, 0x0000FFF0, 1);
|
||||
|
|
@ -304,6 +312,13 @@ VBAPI int vbSetCartROM(VB *sim, void *rom, uint32_t size) {
|
|||
return 0;
|
||||
}
|
||||
|
||||
/* Specify a new exception callback handle */
|
||||
VBAPI vbOnException vbSetExceptionCallback(VB *sim, vbOnException callback) {
|
||||
vbOnException prev = sim->onException;
|
||||
sim->onException = callback;
|
||||
return prev;
|
||||
}
|
||||
|
||||
/* Specify a new execute callback handle */
|
||||
VBAPI vbOnExecute vbSetExecuteCallback(VB *sim, vbOnExecute callback) {
|
||||
vbOnExecute prev = sim->onExecute;
|
||||
|
|
|
|||
13
core/vb.h
13
core/vb.h
|
|
@ -52,7 +52,8 @@ extern "C" {
|
|||
typedef struct VB VB;
|
||||
|
||||
/* Callbacks */
|
||||
typedef int (*vbOnExecute)(VB *sim, uint32_t address, const uint16_t *code, int length);
|
||||
typedef int (*vbOnException)(VB *sim, uint16_t *cause);
|
||||
typedef int (*vbOnExecute )(VB *sim, uint32_t address, const uint16_t *code, int length);
|
||||
typedef int (*vbOnFetch )(VB *sim, int fetch, uint32_t address, int32_t *value, uint32_t *cycles);
|
||||
typedef int (*vbOnRead )(VB *sim, uint32_t address, int type, int32_t *value, uint32_t *cycles);
|
||||
typedef int (*vbOnWrite )(VB *sim, uint32_t address, int type, int32_t *value, uint32_t *cycles, int *cancel);
|
||||
|
|
@ -67,10 +68,11 @@ VBAPI int vbEmulateEx (VB **sims, int count, uint32_t *clocks);
|
|||
VBAPI void* vbGetCallback (VB *sim, int id);
|
||||
VBAPI void* vbGetCartRAM (VB *sim, uint32_t *size);
|
||||
VBAPI void* vbGetCartROM (VB *sim, uint32_t *size);
|
||||
VBAPI vbOnExecute vbGetExecuteCallback(VB *sim);
|
||||
VBAPI vbOnException vbGetExceptionCallback(VB *sim);
|
||||
VBAPI vbOnExecute vbGetExecuteCallback (VB *sim);
|
||||
VBAPI vbOnFetch vbGetFetchCallback (VB *sim);
|
||||
VBAPI uint32_t vbGetProgramCounter (VB *sim);
|
||||
VBAPI int32_t vbGetProgramRegister(VB *sim, int index);
|
||||
VBAPI int32_t vbGetProgramRegister (VB *sim, int index);
|
||||
VBAPI vbOnRead vbGetReadCallback (VB *sim);
|
||||
VBAPI uint32_t vbGetSystemRegister (VB *sim, int index);
|
||||
VBAPI void* vbGetUserData (VB *sim);
|
||||
|
|
@ -80,10 +82,11 @@ VBAPI int32_t vbRead (VB *sim, uint32_t address, int type);
|
|||
VBAPI VB* vbReset (VB *sim);
|
||||
VBAPI int vbSetCartRAM (VB *sim, void *sram, uint32_t size);
|
||||
VBAPI int vbSetCartROM (VB *sim, void *rom, uint32_t size);
|
||||
VBAPI vbOnExecute vbSetExecuteCallback(VB *sim, vbOnExecute callback);
|
||||
VBAPI vbOnException vbSetExceptionCallback(VB *sim, vbOnException callback);
|
||||
VBAPI vbOnExecute vbSetExecuteCallback (VB *sim, vbOnExecute callback);
|
||||
VBAPI vbOnFetch vbSetFetchCallback (VB *sim, vbOnFetch callback);
|
||||
VBAPI uint32_t vbSetProgramCounter (VB *sim, uint32_t value);
|
||||
VBAPI int32_t vbSetProgramRegister(VB *sim, int index, int32_t value);
|
||||
VBAPI int32_t vbSetProgramRegister (VB *sim, int index, int32_t value);
|
||||
VBAPI vbOnRead vbSetReadCallback (VB *sim, vbOnRead callback);
|
||||
VBAPI uint32_t vbSetSystemRegister (VB *sim, int index, uint32_t value);
|
||||
VBAPI void* vbSetUserData (VB *sim, void *tag);
|
||||
|
|
|
|||
Loading…
Reference in New Issue