/* This file is included into vb.c and cannot be compiled on its own. */ #ifdef VBAPI /********************************* Constants *********************************/ /* Instruction IDs */ #define CPU_ILLEGAL -1 #define CPU_ADD_IMM 0 #define CPU_ADD_REG 1 #define CPU_ADDF_S 2 #define CPU_ADDI 3 #define CPU_AND 4 #define CPU_ANDBSU 5 #define CPU_ANDI 6 #define CPU_ANDNBSU 7 #define CPU_BCOND 8 #define CPU_CAXI 9 #define CPU_CLI 10 #define CPU_CMP_IMM 11 #define CPU_CMP_REG 12 #define CPU_CMPF_S 13 #define CPU_CVT_SW 14 #define CPU_CVT_WS 15 #define CPU_DIV 16 #define CPU_DIVF_S 17 #define CPU_DIVU 18 #define CPU_HALT 19 #define CPU_IN_B 20 #define CPU_IN_H 21 #define CPU_IN_W 22 #define CPU_JAL 23 #define CPU_JMP 24 #define CPU_JR 25 #define CPU_LD_B 26 #define CPU_LD_H 27 #define CPU_LD_W 28 #define CPU_LDSR 29 #define CPU_MOV_IMM 30 #define CPU_MOV_REG 31 #define CPU_MOVBSU 32 #define CPU_MOVEA 33 #define CPU_MOVHI 34 #define CPU_MPYHW 35 #define CPU_MUL 36 #define CPU_MULF_S 37 #define CPU_MULU 38 #define CPU_NOT 39 #define CPU_NOTBSU 40 #define CPU_OR 41 #define CPU_ORBSU 42 #define CPU_ORI 43 #define CPU_ORNBSU 44 #define CPU_OUT_B 45 #define CPU_OUT_H 46 #define CPU_OUT_W 47 #define CPU_RETI 48 #define CPU_REV 49 #define CPU_SAR_IMM 50 #define CPU_SAR_REG 51 #define CPU_SCH0BSD 52 #define CPU_SCH0BSU 53 #define CPU_SCH1BSD 54 #define CPU_SCH1BSU 55 #define CPU_SEI 56 #define CPU_SETF 57 #define CPU_SHL_IMM 58 #define CPU_SHL_REG 59 #define CPU_SHR_IMM 60 #define CPU_SHR_REG 61 #define CPU_ST_B 62 #define CPU_ST_H 63 #define CPU_ST_W 64 #define CPU_STSR 65 #define CPU_SUB 66 #define CPU_SUBF_S 67 #define CPU_TRAP 68 #define CPU_TRNC_SW 69 #define CPU_XB 70 #define CPU_XH 71 #define CPU_XOR 72 #define CPU_XORBSU 73 #define CPU_XORI 74 #define CPU_XORNBSU 75 #define CPU_BITSTRING 76 #define CPU_FLOATENDO 77 /* Mapping for bit string sub-opcodes */ static const int8_t CPU_BITSTRINGS[] = { CPU_SCH0BSU, CPU_SCH0BSD, CPU_SCH1BSU, CPU_SCH1BSD, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ORBSU , CPU_ANDBSU , CPU_XORBSU , CPU_MOVBSU , CPU_ORNBSU , CPU_ANDNBSU, CPU_XORNBSU, CPU_NOTBSU , CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL }; /* Mapping for floating-point/Nintendo sub-opcodes */ static const int8_t CPU_FLOATENDO[] = { CPU_CMPF_S , CPU_ILLEGAL, CPU_CVT_WS , CPU_CVT_SW , CPU_ADDF_S , CPU_SUBF_S , CPU_MULF_S , CPU_DIVF_S , CPU_XB , CPU_XH , CPU_REV , CPU_TRNC_SW, CPU_MPYHW , CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL }; #endif /* VBAPI */