494 lines
17 KiB
Java
494 lines
17 KiB
Java
package vue;
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// Java imports
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import java.util.*;
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// CPU state
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class CPU {
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// Private fields
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private JavaVUE vue; // Emulation state
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// Package fields
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Access access; // Access state
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int cycles; // Cycles until next stage
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int exception; // Exception code
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int fetch; // Fetch unit index
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Instruction inst; // Instruction state
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int irq; // Interrupt lines
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int[] jumpFrom; // Source PCs of most recent jumps
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int[] jumpTo; // Destination PCs of most recent jumps
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int stage; // Current processing stage
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// Program registers
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int[] program;
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// System registers
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int adtre; // Address Trap Register for Execution
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int eipc; // Exception/interrupt PC
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int eipsw; // Exception/interrupt PSW
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int fepc; // Duplexed exception PC
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int fepsw; // Duplexed exception PSW
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int pc; // Program Counter
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int sr29; // System register 29
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int sr31; // System register 31
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// Program Status Word
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int psw_ae; // Address Trap Enable
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int psw_ep; // Exception Pending
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int psw_id; // Interrupt Disable
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int psw_cy; // Carry
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int psw_fiv; // Floating Reserved Operand
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int psw_fov; // Floating Overflow
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int psw_fpr; // Floating Precision
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int psw_fro; // Floating Reserved Operand
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int psw_fud; // Floating Underflow
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int psw_fzd; // Floating Zero Divide
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int psw_i; // Interrupt Level
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int psw_np; // NMI Pending
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int psw_ov; // Overflow
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int psw_s; // Sign
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int psw_z; // Zero
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// Cache Control Word
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int chcw_cec; // Clear Entry Count
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int chcw_cen; // Clear Entry Number
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int chcw_icc; // Instruction Cache Clear
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int chcw_icd; // Instruction Cache Dump
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int chcw_ice; // Instruction Cache Enable
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int chcw_icr; // Instruction Cache Restore
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int chcw_sa; // Spill-Out Base Address
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// Exception Cause Register
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int ecr_eicc; // Exception/Interrupt Cause Code
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int ecr_fecc; // Fatal Error Cause Code
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///////////////////////////////////////////////////////////////////////////
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// Constants //
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///////////////////////////////////////////////////////////////////////////
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// Stages
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static final int FATAL = -1;
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static final int FETCH = 0;
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static final int EXECUTE = 1;
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static final int EXCEPTION = 2;
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static final int HALT = 3;
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static final int CLEAR = 4;
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static final int DUMP = 5;
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static final int RESTORE = 6;
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// Instruction cycle counts
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private static final byte[] CYCLES = {
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1, 1, 28, 1, 1, 1, 1, 1, 1, 26, 12, 1, 1, 10, 14, 16,
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38, 44, 36, 1, 5, 5, 5, 3, 3, 3, 5, 5, 5, 8, 1, 1,
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1, 1, 1, 9, 13, 30, 13, 1, 1, 1, 1, 1, 1, 4, 4, 4,
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10, 22, 1, 1, 1, 1, 1, 1, 12, 1, 1, 1, 1, 1, 4, 4,
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4, 8, 1, 28, 15, 14, 6, 1, 1, 1, 1, 1
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};
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///////////////////////////////////////////////////////////////////////////
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// Constructors //
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///////////////////////////////////////////////////////////////////////////
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// Default constructor
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CPU(JavaVUE vue) {
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access = new Access();
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inst = new Instruction();
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jumpFrom = new int[3];
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jumpTo = new int[3];
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program = new int[32];
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this.vue = vue;
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}
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///////////////////////////////////////////////////////////////////////////
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// Package Methods //
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///////////////////////////////////////////////////////////////////////////
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// Process the simulation
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void emulate(int cycles) {
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// The CPU is in permanent halt
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if (stage == FATAL)
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return;
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// Process for the given number of cycles
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do {
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// The next event occurs after the given number of cycles
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if (this.cycles > cycles) {
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this.cycles -= cycles;
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return;
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}
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// Processing by stage
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switch (stage) {
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case FETCH : if (fetch ()) return;
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case EXECUTE : if (execute ()) return;
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case HALT : testException(); break;
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case EXCEPTION: if (exception()) return;
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}
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} while (cycles > 0);
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}
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// Read a system register
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int getSystemRegister(int index) {
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switch (index) {
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case VUE.ADTRE: return adtre;
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case VUE.EIPC : return eipc;
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case VUE.EIPSW: return eipsw;
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case VUE.FEPC : return fepc;
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case VUE.FEPSW: return fepsw;
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case VUE.ECR : return ecr_fecc << 16 | ecr_eicc;
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case VUE.PIR : return 0x00005346;
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case VUE.TKCW : return 0x000000E0;
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case VUE.CHCW : return chcw_ice << 1;
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case 29 : return sr29;
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case 30 : return 0x00000004;
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case 31 : return sr31;
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case VUE.PSW : return
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psw_i << 16 | psw_fro << 9 | psw_fpr << 4 |
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psw_np << 15 | psw_fiv << 8 | psw_cy << 3 |
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psw_ep << 14 | psw_fzd << 7 | psw_ov << 2 |
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psw_ae << 13 | psw_fov << 6 | psw_s << 1 |
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psw_id << 12 | psw_fud << 5 | psw_z
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;
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// Remaining cases to encourage tableswitch
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case 8: case 9: case 10: case 11: case 12: case 13: case 14:
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case 15: case 16: case 17: case 18: case 19: case 20: case 21:
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return 0;
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}
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return 1; // Unreachable
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}
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// System reset
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void reset() {
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// Configure instance fields
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cycles = 0; // Duration of first fetch
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exception = 0;
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fetch = 0;
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irq = 0;
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stage = FETCH;
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// Clear all registers (hardware only sets ECR, PC and PSW)
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for (int x = 0; x < 32; x++) {
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program[x] = 0;
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setSystemRegister(x, 0, true);
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}
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// Configure jump histories
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Arrays.fill(jumpFrom, 0xFFFFFFF0);
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Arrays.fill(jumpTo , 0xFFFFFFF0);
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// Configure registers
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ecr_eicc = 0xFFF0;
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pc = 0xFFFFFFF0;
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psw_np = 1;
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}
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// Write a system register
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int setSystemRegister(int index, int value, boolean debug) {
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switch (index) {
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case VUE.ADTRE: return adtre = value & 0xFFFFFFFE;
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case VUE.EIPC : return eipc = value & 0xFFFFFFFE;
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case VUE.EIPSW: return eipsw = value & 0x000FF3FF;
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case VUE.FEPC : return fepc = value & 0xFFFFFFFE;
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case VUE.FEPSW: return fepsw = value & 0x000FF3FF;
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case 29 : return sr29 = value;
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case 31 : return sr31 = debug || value >= 0 ? value : -value;
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case VUE.ECR:
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if (debug) {
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ecr_fecc = value >> 16 & 0xFFFF;
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ecr_eicc = value & 0xFFFF;
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}
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return ecr_fecc << 16 | ecr_eicc;
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case VUE.CHCW :
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chcw_cen = value >> 20 & 0x00000FFF;
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chcw_cec = value >> 8 & 0x00000FFF;
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chcw_sa = value >> 8 & 0x00FFFFFF;
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chcw_icr = value >> 5 & 1;
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chcw_icd = value >> 4 & 1;
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chcw_ice = value >> 1 & 1;
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chcw_icc = value & 1;
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// Only one of ICC, ICD or ICR is set
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value &= 0x00000031;
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if ((value & value - 1) == 0) {
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// Clear
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// Dump
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// Restore
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}
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return chcw_ice << 1;
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case VUE.PSW :
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psw_i = value >> 16 & 15; psw_fov = value >> 6 & 1;
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psw_np = value >> 15 & 1; psw_fud = value >> 5 & 1;
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psw_ep = value >> 14 & 1; psw_fpr = value >> 4 & 1;
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psw_ae = value >> 13 & 1; psw_cy = value >> 3 & 1;
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psw_id = value >> 12 & 1; psw_ov = value >> 2 & 1;
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psw_fro = value >> 9 & 1; psw_s = value >> 1 & 1;
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psw_fiv = value >> 8 & 1; psw_z = value & 1;
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psw_fzd = value >> 7 & 1;
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return value & 0x000FF3FF;
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// Remaining cases to encourage tableswitch
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case 6: case 7: case 8: case 9: case 10: case 11: case 12:
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case 13: case 14: case 15: case 16: case 17: case 18: case 19:
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case 20: case 21: case 22: case 23: case 26: case 27: case 28:
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case 30:
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return 0;
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}
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return 1; // Unreachable
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}
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// Test a condition
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int test(int condition) {
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switch (condition) {
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case 0: return psw_ov;
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case 1: return psw_cy;
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case 2: return psw_z;
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case 3: return psw_cy | psw_z;
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case 4: return psw_s;
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case 5: return 1;
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case 6: return psw_ov | psw_s;
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case 7: return psw_ov ^ psw_s | psw_z;
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}
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return test(condition & 7) ^ 1;
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}
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// Determine the number of CPU cycles until something can happen
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int until(int cycles) {
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if (stage == FATAL || stage == HALT)
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return cycles;
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return cycles < 0 ? this.cycles : Math.min(cycles, this.cycles);
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}
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///////////////////////////////////////////////////////////////////////////
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// Private Methods //
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///////////////////////////////////////////////////////////////////////////
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// Operations for exception stage
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private boolean exception() {
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// Application callback
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if (vue.onException != null) {
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vue.breakCode = vue.onException.call(vue, exception);
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if (vue.breakCode != 0)
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return true;
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}
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exception &= 0xFFFF;
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boolean isIRQ = (exception & 0xFF00) == 0xFE00;
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int psw = getSystemRegister(VUE.PSW);
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// Fatal exception
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if (psw_np != 0) {
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vue.write(0x00000000, VUE.S32, 0xFFFF0000 | exception);
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vue.write(0x00000004, VUE.S32, psw);
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vue.write(0x00000008, VUE.S32, pc);
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}
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// Duplexed exception
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if (psw_ep != 0) {
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ecr_fecc = exception;
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fepc = pc;
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fepsw = psw;
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pc = 0xFFFFFFD0;
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}
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// Regular exception
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else {
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ecr_eicc = exception;
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eipc = pc;
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eipsw = psw;
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pc = 0xFFFF0000 | exception & 0xFFF0;
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if (pc == 0xFFFFFF70) // FIV
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pc = 0xFFFFFF60;
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}
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// Interrupt
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if (isIRQ)
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psw_i = Math.min(15, exception >> 4 & 15);
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// Common processing
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exception = 0;
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psw_ae = 0;
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psw_id = 1;
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stage = FETCH;
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return false;
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}
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// Operations for execute stage
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private boolean execute() {
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// Application callback
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if (vue.onExecute != null) {
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vue.breakCode = vue.onExecute.call(vue, inst);
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if (vue.breakCode != 0)
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return true;
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}
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// Determine the default number of cycles for the instruction
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if (inst.id >= 0 && inst.id <= 75)
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cycles = CYCLES[inst.id];
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// Processing by instruction ID
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switch (inst.id) {
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//case VUE.ADD_IMM: ADD_IMM(); break;
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//case VUE.ADD_REG: ADD_REG(); break;
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//case VUE.ADDF_S : ADDF_S (); break;
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//case VUE.ADDI : ADDI (); break;
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//case VUE.AND : AND (); break;
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//case VUE.ANDBSU : ANDBSU (); break;
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//case VUE.ANDI : ANDI (); break;
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//case VUE.ANDNBSU: ANDNBSU(); break;
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//case VUE.BCOND : BCOND (); break;
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//case VUE.CAXI : CAXI (); break;
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//case VUE.CLI : CLI (); break;
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//case VUE.CMP_IMM: CMP_IMM(); break;
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//case VUE.CMP_REG: CMP_REG(); break;
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//case VUE.CMPF_S : CMPF_S (); break;
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//case VUE.CVT_SW : CVT_SW (); break;
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//case VUE.CVT_WS : CVT_WS (); break;
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//case VUE.DIV : DIV (); break;
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//case VUE.DIVF_S : DIVF_S (); break;
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//case VUE.DIVU : DIVU (); break;
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//case VUE.HALT : HALT (); break;
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//case VUE.IN_B : IN_B (); break;
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//case VUE.IN_H : IN_H (); break;
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//case VUE.IN_W : IN_W (); break;
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//case VUE.JAL : JAL (); break;
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//case VUE.JMP : JMP (); break;
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//case VUE.JR : JR (); break;
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//case VUE.LD_B : LD_B (); break;
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//case VUE.LD_H : LD_H (); break;
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//case VUE.LD_W : LD_W (); break;
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//case VUE.LDSR : LDSR (); break;
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//case VUE.MOV_IMM: MOV_IMM(); break;
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//case VUE.MOV_REG: MOV_REG(); break;
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//case VUE.MOVBSU : MOVBSU (); break;
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//case VUE.MOVEA : MOVEA (); break;
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//case VUE.MOVHI : MOVHI (); break;
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//case VUE.MPYHW : MPYHW (); break;
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//case VUE.MUL : MUL (); break;
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//case VUE.MULF_S : MULF_S (); break;
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//case VUE.MULU : MULU (); break;
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//case VUE.NOT : NOT (); break;
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//case VUE.NOTBSU : NOTBSU (); break;
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//case VUE.OR : OR (); break;
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//case VUE.ORBSU : ORBSU (); break;
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//case VUE.ORI : ORI (); break;
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//case VUE.ORNBSU : ORNBSU (); break;
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//case VUE.OUT_B : OUT_B (); break;
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//case VUE.OUT_H : OUT_H (); break;
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//case VUE.OUT_W : OUT_W (); break;
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//case VUE.RETI : RETI (); break;
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//case VUE.REV : REV (); break;
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//case VUE.SAR_IMM: SAR_IMM(); break;
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//case VUE.SAR_REG: SAR_REG(); break;
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//case VUE.SCH0BSD: SCH0BSD(); break;
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//case VUE.SCH0BSU: SCH0BSU(); break;
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//case VUE.SCH1BSD: SCH1BSD(); break;
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//case VUE.SCH1BSU: SCH1BSU(); break;
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//case VUE.SEI : SEI (); break;
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//case VUE.SETF : SETF (); break;
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//case VUE.SHL_IMM: SHL_IMM(); break;
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//case VUE.SHL_REG: SHL_REG(); break;
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//case VUE.SHR_IMM: SHR_IMM(); break;
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//case VUE.SHR_REG: SHR_REG(); break;
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//case VUE.ST_B : ST_B (); break;
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//case VUE.ST_H : ST_H (); break;
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//case VUE.ST_W : ST_W (); break;
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//case VUE.STSR : STSR (); break;
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//case VUE.SUB : SUB (); break;
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//case VUE.SUBF_S : SUBF_S (); break;
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//case VUE.TRAP : TRAP (); break;
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//case VUE.TRNC_SW: TRNC_SW(); break;
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//case VUE.XB : XB (); break;
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//case VUE.XH : XH (); break;
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//case VUE.XOR : XOR (); break;
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//case VUE.XORBSU : XORBSU (); break;
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//case VUE.XORI : XORI (); break;
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//case VUE.XORNBSU: XORNBSU(); break;
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default: exception = 0xFF90; // Invalid instruction
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}
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// Common processing
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pc += inst.size;
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program[0] = 0;
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testException();
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return false;
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}
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// Operations for fetch stage
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private boolean fetch() {
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// Read the bits from the bus
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access.address = pc + (fetch << 1);
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access.fetch = fetch;
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access.type = VUE.U16;
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access.value = vue.read(access.address, VUE.U16);
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// Application callback
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if (vue.onRead != null) {
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vue.breakCode = vue.onRead.call(vue, access);
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if (vue.breakCode != 0)
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return true;
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}
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// First unit
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if (fetch == 0) {
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inst.bits = access.value << 16;
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if (Instruction.size(access.value & 0x3F) == 4) {
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fetch = 1;
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return false;
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}
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}
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// Second unit
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else {
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inst.bits |= access.value & 0xFFFF;
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fetch = 0;
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}
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// Decode the instruction and advance to execute stage
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inst.decode(inst.bits);
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stage = EXECUTE;
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return false;
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}
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// Check for an exception or interrupt
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private void testException() {
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// Check for an interrupt
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if (irq != 0 && (exception | psw_id | psw_ep | psw_np) == 0) {
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int level;
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for (level = 4; level >= 0; level--)
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if ((irq >> level & 1) != 0)
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break;
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exception = 0xFE00 | level << 4;
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}
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// Check for an exception
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if (exception != 0) {
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cycles = 0;
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stage = EXCEPTION;
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}
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}
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}
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