Implement GDB/LLDB compatible server #3

Merged
SonicSwordcane merged 33 commits from debugger into main 2025-01-19 00:13:43 +00:00
3 changed files with 12 additions and 10 deletions
Showing only changes of commit 2cf99dbc21 - Show all commits

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@ -3,7 +3,6 @@ use std::{
fmt::Display, fmt::Display,
fs::{self, File}, fs::{self, File},
io::{Read, Seek, SeekFrom, Write}, io::{Read, Seek, SeekFrom, Write},
ops::Range,
path::{Path, PathBuf}, path::{Path, PathBuf},
sync::{ sync::{
atomic::{AtomicBool, Ordering}, atomic::{AtomicBool, Ordering},
@ -529,11 +528,11 @@ impl Emulator {
let value = sim.read_register(register); let value = sim.read_register(register);
let _ = done.send(value); let _ = done.send(value);
} }
EmulatorCommand::ReadMemory(sim_id, addresses, mut buffer, done) => { EmulatorCommand::ReadMemory(sim_id, start, length, mut buffer, done) => {
let Some(sim) = self.sims.get_mut(sim_id.to_index()) else { let Some(sim) = self.sims.get_mut(sim_id.to_index()) else {
return; return;
}; };
sim.read_memory(addresses, &mut buffer); sim.read_memory(start, length, &mut buffer);
let _ = done.send(buffer); let _ = done.send(buffer);
} }
EmulatorCommand::AddBreakpoint(sim_id, address) => { EmulatorCommand::AddBreakpoint(sim_id, address) => {
@ -611,7 +610,7 @@ pub enum EmulatorCommand {
DebugContinue(SimId), DebugContinue(SimId),
DebugStep(SimId), DebugStep(SimId),
ReadRegister(SimId, VBRegister, oneshot::Sender<u32>), ReadRegister(SimId, VBRegister, oneshot::Sender<u32>),
ReadMemory(SimId, Range<u32>, Vec<u8>, oneshot::Sender<Vec<u8>>), ReadMemory(SimId, u32, usize, Vec<u8>, oneshot::Sender<Vec<u8>>),
AddBreakpoint(SimId, u32), AddBreakpoint(SimId, u32),
RemoveBreakpoint(SimId, u32), RemoveBreakpoint(SimId, u32),
SetAudioEnabled(bool, bool), SetAudioEnabled(bool, bool),

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@ -1,4 +1,4 @@
use std::{ffi::c_void, ops::Range, ptr, slice}; use std::{ffi::c_void, ptr, slice};
use anyhow::{anyhow, Result}; use anyhow::{anyhow, Result};
use bitflags::bitflags; use bitflags::bitflags;
@ -349,10 +349,12 @@ impl Sim {
} }
} }
pub fn read_memory(&mut self, addresses: Range<u32>, into: &mut Vec<u8>) { pub fn read_memory(&mut self, start: u32, length: usize, into: &mut Vec<u8>) {
for address in addresses { let mut address = start;
for _ in 0..length {
let byte = unsafe { vb_read(self.sim, address, VBDataType::U8) }; let byte = unsafe { vb_read(self.sim, address, VBDataType::U8) };
into.push(byte as u8); into.push(byte as u8);
address = address.wrapping_add(1);
} }
} }

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@ -280,17 +280,18 @@ impl GdbConnection {
} }
} else if let Some(op) = req.match_some_str(["m", "x"]) { } else if let Some(op) = req.match_some_str(["m", "x"]) {
let mut read_memory = || { let mut read_memory = || {
let start = req.match_hex::<u32>()?; let start = req.match_hex::<u64>()? as u32;
if !req.match_str(",") { if !req.match_str(",") {
return None; return None;
}; };
let size = req.match_hex::<u32>()?; let length = req.match_hex::<usize>()?;
let mut buf = self.memory_buf.take().unwrap_or_default(); let mut buf = self.memory_buf.take().unwrap_or_default();
buf.clear(); buf.clear();
let (tx, rx) = ::oneshot::channel(); let (tx, rx) = ::oneshot::channel();
self.client.send_command(EmulatorCommand::ReadMemory( self.client.send_command(EmulatorCommand::ReadMemory(
self.sim_id, self.sim_id,
start..(start + size), start,
length,
buf, buf,
tx, tx,
)); ));