Fix linker script to be more generic
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parent
7c8ce09516
commit
0c214e4afc
18
vb.ld
18
vb.ld
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@ -10,13 +10,10 @@ MEMORY {
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rom (rx): ORIGIN = 0x07000000, LENGTH = 16M
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rom (rx): ORIGIN = 0x07000000, LENGTH = 16M
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}
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}
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__text_vma = 0x07000000;
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__data_vma = 0x05000000;
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SECTIONS
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SECTIONS
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{
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{
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/* Read-only sections, merged into text segment: */
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/* Read-only sections, merged into text segment: */
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.text __text_vma : {
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.text ORIGIN(rom) : {
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*(.text)
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*(.text)
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*(.text.*)
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*(.text.*)
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/* .gnu.warning sections are handled specially by elf32.em. */
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/* .gnu.warning sections are handled specially by elf32.em. */
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@ -63,7 +60,7 @@ SECTIONS
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/* Ram memory */
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/* Ram memory */
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__data_lma = .;
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__data_lma = .;
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.data __data_vma : AT(__data_lma) {
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.data ORIGIN(ram) : AT(__data_lma) {
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*(.data)
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*(.data)
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*(.data.*)
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*(.data.*)
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*(.sdata)
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*(.sdata)
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@ -74,7 +71,7 @@ SECTIONS
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__data_end = .;
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__data_end = .;
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.bss : {
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.bss (NOLOAD) : {
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*(.dynbss)
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*(.dynbss)
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*(.bss)
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*(.bss)
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*(.sdata)
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*(.sdata)
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@ -88,11 +85,10 @@ SECTIONS
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/* Prevent overlaps with vbvectors */
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/* Prevent overlaps with vbvectors */
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__sections_size = SIZEOF(.text) + SIZEOF(.rodata) + SIZEOF(.data);
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__sections_size = SIZEOF(.text) + SIZEOF(.rodata) + SIZEOF(.data);
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__rom_size = 1 << LOG2CEIL(__sections_size + 0x220);
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__rom_size = 1 << LOG2CEIL(__sections_size + 0x220);
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__rom_end = ORIGIN(rom) + __rom_size;
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__rom_header_start = ORIGIN(rom) + __rom_size - 0x220;
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/* Place interupt and reset vector at end of rom */
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/* Place interupt and reset vector at end of rom */
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.rom_header 0x07FFFDE0 : AT(__rom_header_start) {
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.vbvectors 0x07FFFDE0 : AT(__rom_end - 0x220) {
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KEEP (*(.rom_header))
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KEEP (*(.vbvectors))
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} >rom
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} >rom = 0xFF
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}
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}
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