commit ec3b02d8a5af0b4aab87071a45bd68aaf559dafd Author: Simon Gellis Date: Sun Oct 13 21:29:17 2024 -0400 Initial gauntlet diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..5cce23b --- /dev/null +++ b/.gitignore @@ -0,0 +1,2 @@ +.vscode +output \ No newline at end of file diff --git a/gauntlet.s b/gauntlet.s new file mode 100644 index 0000000..71d5161 --- /dev/null +++ b/gauntlet.s @@ -0,0 +1,2611 @@ +.section .text +.align 4 + +.global start +start: +begin_validation: + +#Start with basic branch testing +#by directly modifying the PSW. +#These instructions must work before +#We can trust much else of the gauntlet. + ldsr r0, psw + bnz 4 + halt + bnc 4 + halt + bp 4 + halt + bnv 4 + halt + mov -1, r1 # New instruction + ldsr r1, psw + bz 4 + halt + bc 4 + halt + bn 4 + halt + bv 4 + halt + +#BR + br 4 + halt + +#BV / BNV + mov 4, r1 + ldsr r1, psw + bv 4 + halt + bnv 4 + br 4 + halt + not r1, r1 # New instruction + ldsr r1, psw + bnv 4 + halt + bv 4 + br 4 + halt + +#BC / BNC + mov 8, r1 + ldsr r1, psw + bc 4 + halt + bnc 4 + br 4 + halt + not r1, r1 + ldsr r1, psw + bnc 4 + halt + bc 4 + br 4 + halt + +#BE / BNE + mov 1, r1 + ldsr r1, psw + be 4 + halt + bne 4 + br 4 + halt + not r1, r1 + ldsr r1, psw + bne 4 + halt + be 4 + br 4 + halt + +#BN / BP + mov 2, r1 + ldsr r1, psw + bn 4 + halt + bp 4 + br 4 + halt + not r1, r1 + ldsr r1, psw + bp 4 + halt + bn 4 + br 4 + halt + +#BNH / BH + mov 1, r1 + ldsr r1, psw + bnh 4 + halt + bh 4 + br 4 + halt + mov 8, r1 + ldsr r1, psw + bnh 4 + halt + bh 4 + br 4 + halt + mov 9, r1 + ldsr r1, psw + bnh 4 + halt + bh 4 + br 4 + halt + not r1, r1 + ldsr r1, psw + bh 4 + halt + bnh 4 + br 4 + halt + +#BLT / BGE + mov 2, r1 + ldsr r1, psw + blt 4 + halt + bge 4 + br 4 + halt + mov 4, r1 + ldsr r1, psw + blt 4 + halt + bge 4 + br 4 + halt + mov 6, r1 + ldsr r1, psw + bge 4 + halt + blt 4 + br 4 + halt + +#BLE / BGT +#Zero flag off + mov 2, r1 + ldsr r1, psw + ble 4 + halt + bgt 4 + br 4 + halt + mov 4, r1 + ldsr r1, psw + ble 4 + halt + bgt 4 + br 4 + halt + mov 6, r1 + ldsr r1, psw + bgt 4 + halt + ble 4 + br 4 + halt + +#Zero flag on + mov 3, r1 + ldsr r1, psw + ble 4 + halt + bgt 4 + br 4 + halt + mov 5, r1 + ldsr r1, psw + ble 4 + halt + bgt 4 + br 4 + halt + mov 7, r1 + ldsr r1, psw + bgt 4 + br 4 + halt + ble 4 + halt + +#Move on to cmp, since that's important for running the tests... +cmp_imm: + mov 10, r1 + cmp 10, r1 + be 4 + halt + cmp 9, r1 + blt 4 + br 4 + halt + be 4 + br 4 + halt + bgt 4 + halt + cmp 11, r1 + blt 4 + halt + be 4 + br 4 + halt + bgt 4 + br 4 + halt + +cmp_reg: + mov 10, r1 + mov 10, r6 + cmp r6, r1 + be 4 + halt + mov 9, r6 + cmp r6, r1 + blt 4 + br 4 + halt + be 4 + br 4 + halt + bgt 4 + halt + mov 11, r6 + cmp r6, r1 + blt 4 + halt + be 4 + br 4 + halt + bgt 4 + br 4 + halt + +check_mov: + mov 7, r1 + cmp 7, r1 + be mov0 + halt +mov0: + mov -4, r1 + cmp -4, r1 + be mov1 + halt +mov1: + mov 10, r0 + cmp 0, r0 + be mov2 + halt +mov2: + mov 7, r6 + mov r6, r8 + cmp 7, r8 + be mov3 + halt +mov3: + mov -7, r6 + mov r6, r8 + cmp -7, r8 + be mov4 + halt +mov4: + +check_movea: + mov 1, r6 + movea 5, r6, r7 + cmp 6, r7 + be movea0 + halt +movea0: + mov -1, r6 + movea -5, r6, r7 + cmp -6, r7 + be movea1 + halt +movea1: + +movhi0: + mov 7, r6 + movhi 5, r6, r7 + mov 5, r8 + shl 16, r8 + add 7, r8 + cmp r8, r7 + be movhi1 + halt +movhi1: + mov 7, r6 + movhi -5, r6, r7 + mov -5, r8 + shl 16, r8 + add 7, r8 + cmp r8, r7 + be movhi2 + halt +movhi2: + + +add_imm: +#Simple case + mov 2, r1 + add 3, r1 + bnz 4 + halt + bp 4 + halt + bnv 4 + halt + bnc 4 + halt + cmp 5, r1 + be 4 + halt + +#Add negative and go to zero + mov 2, r1 + add -2, r1 + bz 4 + halt + bp 4 + halt + bnv 4 + halt + bc 4 + halt + cmp 0, r1 + be 4 + halt + +#Add negative and go negative + mov 2, r1 + add -3, r1 + bnz 4 + halt + bn 4 + halt + bnv 4 + halt + bnc 4 + halt + cmp -1, r1 + be 4 + halt + +#Overflow + movhi hi(0xFFFFFFFF), r0, r1 + movea lo(0xFFFFFFFF), r1, r1 + add 2, r1 + bnz 4 + halt + bp 4 + halt + bnv 4 + halt + bc 4 + halt + cmp 1, r1 + be 4 + halt + +add_reg: +#Simple case + mov 2, r1 + mov 3, r6 + add r6, r1 + bnz 4 + halt + bp 4 + halt + bnv 4 + halt + bnc 4 + halt + cmp 5, r1 + be 4 + halt + +#Add negative and go to zero + mov 2, r1 + mov -2, r6 + add r6, r1 + bz 4 + halt + bp 4 + halt + bnv 4 + halt + bc 4 + halt + cmp 0, r1 + be 4 + halt + +#Add negative and go negative + mov 2, r1 + mov -3, r6 + add r6, r1 + bnz 4 + halt + bn 4 + halt + bnv 4 + halt + bnc 4 + halt + cmp -1, r1 + be 4 + halt + +#Overflow + movhi hi(0xFFFFFFFF), r0, r1 + movea lo(0xFFFFFFFF), r1, r1 + mov 2, r6 + add r6, r1 + bnz 4 + halt + bp 4 + halt + bnv 4 + halt + bc 4 + halt + cmp 1, r1 + be 4 + halt + +addi: +#Simple case + mov 2, r6 + addi 3, r6, r1 + bnz 4 + halt + bp 4 + halt + bnv 4 + halt + bnc 4 + halt + cmp 5, r1 + be 4 + halt + +#Add negative and go to zero + mov 2, r6 + addi -2, r6, r1 + bz 4 + halt + bp 4 + halt + bnv 4 + halt + bc 4 + halt + cmp 0, r1 + be 4 + halt + +#Add negative and go negative + mov 2, r6 + addi -3, r6, r1 + bnz 4 + halt + bn 4 + halt + bnv 4 + halt + bnc 4 + halt + cmp -1, r1 + be 4 + halt + +#Overflow + movhi hi(0xFFFFFFFF), r0, r6 + movea lo(0xFFFFFFFF), r6, r6 + addi 2, r6, r1 + bnz 4 + halt + bp 4 + halt + bnv 4 + halt + bc 4 + halt + cmp 1, r1 + be 4 + halt + + + +sub: +#Sub but remain positive + mov 3, r1 + mov 2, r6 + sub r6, r1 + bnz 4 + halt + bp 4 + halt + bnv 4 + halt + bnc 4 + halt + cmp 1, r1 + be 4 + halt + +#Sub to zero + mov 2, r1 + mov 2, r6 + sub r6, r1 + bz 4 + halt + bp 4 + halt + bnv 4 + halt + bnc 4 + halt + cmp 0, r1 + be 4 + halt + +#Sub to negative + mov 2, r1 + mov 3, r6 + sub r6, r1 + bnz 4 + halt + bn 4 + halt + bnv 4 + halt + bc 4 + halt + cmp -1, r1 + be 4 + halt + +#Overflow + movhi hi(0xFFFFFFFF), r0, r1 + movea lo(0xFFFFFFFF), r1, r1 + mov 2, r6 + sub r6, r1 + bnz 4 + halt + bn 4 + halt + bnv 4 + halt + bnc 4 + halt + movhi hi(0xFFFFFFFD), r0, r6 + movea lo(0xFFFFFFFD), r6, r6 + cmp r6, r1 + be 4 + halt + +div: +# 2 small positive numbers + mov 9, r6 + mov 2, r7 + div r7, r6 + bnz 4 + halt + bp 4 + halt + bnv 4 + halt + bnc 4 + halt + cmp 4, r6 + be 4 + halt + cmp 1, r30 + be 4 + halt + +# 2 small negative numbers + mov -9, r6 + mov -2, r7 + div r7, r6 + bnz 4 + halt + bp 4 + halt + bnv 4 + halt + bnc 4 + halt + cmp 4, r6 + be 4 + halt + cmp -1, r30 + be 4 + halt + +#Negative dividend + mov -9, r6 + mov 2, r7 + div r7, r6 + bnz 4 + halt + bn 4 + halt + bnv 4 + halt + bnc 4 + halt + cmp -4, r6 + be 4 + halt + cmp -1, r30 + be 4 + halt + +#Negative divisor + mov 9, r6 + mov -2, r7 + div r7, r6 + bnz 4 + halt + bn 4 + halt + bnv 4 + halt + bnc 4 + halt + cmp -4, r6 + be 4 + halt + cmp 1, r30 + be 4 + halt + +#Divides to zero + mov 9, r6 + mov 10, r7 + div r7, r6 + bz 4 + halt + bp 4 + halt + bnv 4 + halt + bnc 4 + halt + cmp 0, r6 + be 4 + halt + cmp 9, r30 + be 4 + halt + +divu: +# 2 small positive numbers + mov 9, r6 + mov 2, r7 + divu r7, r6 + bnz 4 + halt + bp 4 + halt + bnv 4 + halt + bnc 4 + halt + cmp 4, r6 + be 4 + halt + cmp 1, r30 + be 4 + halt + +# 2 small negative numbers + mov -9, r6 + mov -2, r7 + divu r7, r6 + bz 4 + halt + bp 4 + halt + bnv 4 + halt + bnc 4 + halt + cmp 0, r6 + be 4 + halt + add -7, r7 + cmp r7, r30 + be 4 + halt + +#Negative dividend + mov -9, r6 + mov 2, r7 + divu r7, r6 + bnz 4 + halt + bp 4 + halt + bnv 4 + halt + bnc 4 + halt + movhi hi(0x7FFFFFFB), r0, r7 + movea lo(0x7FFFFFFB), r7, r7 + cmp r6, r7 + be 4 + halt + cmp 1, r30 + be 4 + halt + +#Negative divisor + mov 9, r6 + mov -2, r7 + divu r7, r6 + bz 4 + halt + bp 4 + halt + bnv 4 + halt + bnc 4 + halt + cmp 0, r6 + be 4 + halt + cmp 9, r30 + be 4 + halt + +#Divides to zero + mov 9, r6 + mov 10, r7 + divu r7, r6 + bz 4 + halt + bp 4 + halt + bnv 4 + halt + bnc 4 + halt + cmp 0, r6 + be 4 + halt + cmp 9, r30 + be 4 + halt + + +mul: +# 2 small positive numbers + mov 3, r6 + mov 2, r7 + mul r7, r6 + bnz 4 + halt + bp 4 + halt + bnv 4 + halt + bnc 4 + halt + cmp 6, r6 + be 4 + halt + cmp 0, r30 + be 4 + halt + +# 2 small negative numbers + mov -3, r6 + mov -2, r7 + mul r7, r6 + bnz 4 + halt + bp 4 + halt + bnv 4 + halt + bnc 4 + halt + cmp 6, r6 + be 4 + halt + cmp 0, r30 + be 4 + halt + +#Negative rhs + mov -3, r6 + mov 2, r7 + mul r7, r6 + bnz 4 + halt + bn 4 + halt + bnv 4 + halt + bnc 4 + halt + cmp -6, r6 + be 4 + halt + movhi hi(0xFFFFFFFF), r0, r7 + movea lo(0xFFFFFFFF), r7, r7 + cmp r7, r30 + be 4 + halt + +#Negative lhs + mov 3, r6 + mov -2, r7 + mul r7, r6 + bnz 4 + halt + bn 4 + halt + bnv 4 + halt + bnc 4 + halt + cmp -6, r6 + be 4 + halt + movhi hi(0xFFFFFFFF), r0, r7 + movea lo(0xFFFFFFFF), r7, r7 + cmp r7, r30 + be 4 + halt + +#Multiplies to zero + mov 9, r6 + mov 0, r7 + mul r7, r6 + bz 4 + halt + bp 4 + halt + bnv 4 + halt + bnc 4 + halt + cmp 0, r6 + be 4 + halt + cmp 0, r30 + be 4 + halt + +#Big number, no overflow +#but sign flag goes +#negative even though product +#is not . + movhi hi(123456), r0, r6 + movea lo(123456), r6, r6 + movhi hi(87654), r0, r7 + movea lo(87654), r7, r7 + mul r7, r6 + bnz 4 + halt + bn 4 # Hardware bug + halt + bv 4 + halt + bnc 4 + halt + movhi hi(0x8501A580), r0, r7 + movea lo(0x8501A580), r7, r7 + cmp r7, r6 + be 4 + halt + cmp 2, r30 + be 4 + halt + +#Total Annihilation + movhi hi(0xFFFFFFFF), r0, r6 + movea lo(0xFFFFFFFF), r6, r6 + movhi hi(0xFFFFFFFF), r0, r7 + movea lo(0xFFFFFFFF), r7, r7 + mul r7, r6 + bnz 4 + halt + bp 4 # Hardware bug + halt + bnv 4 + halt + bnc 4 + halt + cmp 1, r6 + be 4 + halt + cmp 0, r30 + be 4 + halt + +mpyhw: # Note that no flags are set by this instruction +# 2 small positive numbers + mov 3, r6 + mov 2, r7 + mpyhw r7, r6 + cmp 6, r6 + be 4 + halt + +# 2 small negative numbers + mov -3, r6 + mov -2, r7 + mpyhw r7, r6 + cmp 6, r6 + be 4 + halt + +#Negative rhs + mov -3, r6 + mov 2, r7 + mpyhw r7, r6 + cmp -6, r6 + be 4 + halt + +#Negative lhs + mov 3, r6 + mov -2, r7 + mpyhw r7, r6 + cmp -6, r6 + be 4 + halt + +#Multiplies to zero + mov 9, r6 + mov 0, r7 + mpyhw r7, r6 + cmp 0, r6 + be 4 + halt + +#Total Annihilation + movhi hi(0xFFFFFFFF), r0, r6 + movea lo(0xFFFFFFFF), r6, r6 + movhi hi(0xFFFFFFFF), r0, r7 + movea lo(0xFFFFFFFF), r7, r7 + mpyhw r7, r6 + cmp 1, r6 + be 4 + halt + +mulu: +# 2 small positive numbers + mov 3, r6 + mov 2, r7 + mulu r7, r6 + bnz 4 + halt + bp 4 + halt + bnv 4 + halt + bnc 4 + halt + cmp 6, r6 + be 4 + halt + cmp 0, r30 + be 4 + halt + +# 2 small negative numbers + mov -3, r6 + mov -2, r7 + mulu r7, r6 + bnz 4 + halt + bp 4 + halt + bv 4 + halt + bnc 4 + halt + cmp 6, r6 + be 4 + halt + cmp -5, r30 + be 4 + halt + +#Negative rhs + mov -3, r6 + mov 2, r7 + mulu r7, r6 + bnz 4 + halt + bn 4 + halt + bv 4 + halt + bnc 4 + halt + cmp -6, r6 + be 4 + halt + cmp 1, r30 + be 4 + halt + +#Negative lhs + mov 3, r6 + mov -2, r7 + mulu r7, r6 + bnz 4 + halt + bn 4 + halt + bv 4 + halt + bnc 4 + halt + cmp -6, r6 + be 4 + halt + cmp 2, r30 + be 4 + halt + +#Multiplies to zero + mov 9, r6 + mov 0, r7 + mulu r7, r6 + bz 4 + halt + bp 4 + halt + bnv 4 + halt + bnc 4 + halt + cmp 0, r6 + be 4 + halt + cmp 0, r30 + be 4 + halt + +#Big number, no overflow +#but sign flag goes +#negative even though product +#is not . + movhi hi(123456), r0, r6 + movea lo(123456), r6, r6 + movhi hi(87654), r0, r7 + movea lo(87654), r7, r7 + mulu r7, r6 + bnz 4 + halt + bn 4 # Hardware bug + halt + bv 4 + halt + bnc 4 + halt + movhi hi(0x8501A580), r0, r7 + movea lo(0x8501A580), r7, r7 + cmp r7, r6 + be 4 + halt + cmp 2, r30 + be 4 + halt + +#Total Annihilation + movhi hi(0xFFFFFFFF), r0, r6 + movea lo(0xFFFFFFFF), r6, r6 + movhi hi(0xFFFFFFFF), r0, r7 + movea lo(0xFFFFFFFF), r7, r7 + mulu r7, r6 + bnz 4 + halt + bp 4 # Hardware bug + halt + bv 4 + halt + bnc 4 + halt + cmp 1, r6 + be 4 + halt + cmp -2, r30 + be 4 + halt + +and: +#Basic + mov 3, r6 + mov 9, r7 + and r7, r6 + bnz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + cmp 1, r6 + be 4 + halt + +#Negative + mov -1, r6 + mov -1, r7 + and r7, r6 + bnz 4 + halt + bn 4 + halt + bnv 4 # Always + halt + cmp -1, r6 + be 4 + halt + +#Zero + mov 0, r6 + mov 13, r7 + and r7, r6 + bz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + cmp 0, r6 + be 4 + halt + +andi: +#Basic + mov 3, r6 + andi 9, r6, r7 + bnz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + cmp 1, r7 + be 4 + halt + +#Negative + mov -1, r6 + andi -1, r6, r7 + bnz 4 + halt + bp 4 # Differs from and and is always 0 (??) + halt + bnv 4 # Always + halt + movhi hi(0xFFFF), r0, r6 + movea lo(0xFFFF), r6, r6 + cmp r6, r7 + be 4 + halt + +#Zero + mov 0, r6 + andi 13, r6, r7 + bz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + cmp 0, r7 + be 4 + halt + +or: +#Basic + mov 3, r6 + mov 9, r7 + or r7, r6 + bnz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + cmp 0xB, r6 + be 4 + halt + +#Negative + mov -1, r6 + mov -1, r7 + or r7, r6 + bnz 4 + halt + bn 4 + halt + bnv 4 # Always + halt + cmp -1, r6 + be 4 + halt + +#Zero + mov 0, r6 + mov 0, r7 + or r7, r6 + bz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + cmp 0, r6 + be 4 + halt + + +ori: +#Basic + mov 3, r6 + ori 9, r6, r7 + bnz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + cmp 0xB, r7 + be 4 + halt + +#Negative + mov -1, r6 + ori -1, r6, r7 + bnz 4 + halt + bn 4 + halt + bnv 4 # Always + halt + cmp r6, r7 + be 4 + halt + +#Zero + mov 0, r6 + ori 0, r6, r7 + bz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + cmp 0, r7 + be 4 + halt + +not: +#Zero + mov -1, r6 + not r6, r7 + bz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + cmp 0, r7 + be 4 + halt + +#Positive + movhi hi(0xAAAAAAAA), r0, r6 + movea lo(0xAAAAAAAA), r6, r6 + not r6, r7 + bnz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + movhi hi(0x55555555), r0, r6 + movea lo(0x55555555), r6, r6 + cmp r6, r7 + be 4 + halt + +#Negative + movhi hi(0x55555555), r0, r6 + movea lo(0x55555555), r6, r6 + not r6, r7 + bnz 4 + halt + bn 4 + halt + bnv 4 # Always + halt + movhi hi(0xAAAAAAAA), r0, r6 + movea lo(0xAAAAAAAA), r6, r6 + cmp r6, r7 + be 4 + halt + +sar_imm: +#Zero shift + mov 7, r6 + sar 0, r6 + bnz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + bnc 4 + halt + cmp 7, r6 + be 4 + halt + +#Positive to Positive, shifting out 1 + mov 7, r6 + sar 1, r6 + bnz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + bc 4 + halt + cmp 3, r6 + be 4 + halt + +#Positive to Positive, shifting out 0 + mov 6, r6 + sar 1, r6 + bnz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + bnc 4 + halt + cmp 3, r6 + be 4 + halt + +#Positive shift of negative number + mov -6, r6 + sar 1, r6 + bnz 4 + halt + bn 4 + halt + bnv 4 # Always + halt + bnc 4 + halt + cmp -3, r6 + be 4 + halt + +#Negative shift of positive number. + mov 6, r6 + sar -1, r6 # Just an unsigned shift I guess + bz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + bnc 4 + halt + cmp 0, r6 + be 4 + halt + +#Negative shift of negative number + mov -6, r6 + sar -1, r6 # Just an unsigned shift I guess + bnz 4 + halt + bn 4 + halt + bnv 4 # Always + halt + bc 4 + halt + cmp -1, r6 + be 4 + halt + +#Shift to zero result + mov 6, r6 + sar 3, r6 + bz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + bc 4 + halt + cmp 0, r6 + be 4 + halt + + +sar_reg: +#Zero shift + mov 7, r6 + mov 0, r7 + sar r7, r6 + bnz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + bnc 4 + halt + cmp 7, r6 + be 4 + halt + +#Positive to Positive, shifting out 1 + mov 7, r6 + mov 1, r7 + sar r7, r6 + bnz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + bc 4 + halt + cmp 3, r6 + be 4 + halt + +#Positive to Positive, shifting out 0 + mov 6, r6 + mov 1, r7 + sar r7, r6 + bnz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + bnc 4 + halt + cmp 3, r6 + be 4 + halt + +#Positive shift of negative number + mov -6, r6 + mov 1, r7 + sar r7, r6 + bnz 4 + halt + bn 4 + halt + bnv 4 # Always + halt + bnc 4 + halt + cmp -3, r6 + be 4 + halt + +#Negative shift of positive number. + mov 6, r6 + mov -1, r7 # Just an unsigned shift I guess + sar r7, r6 + bz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + bnc 4 + halt + cmp 0, r6 + be 4 + halt + +#Negative shift of negative number + mov -6, r6 + mov -1, r7 # Just an unsigned shift I guess + sar r7, r6 + bnz 4 + halt + bn 4 + halt + bnv 4 # Always + halt + bc 4 + halt + cmp -1, r6 + be 4 + halt + +#Shift to zero result + mov 6, r6 + mov 3, r7 + sar r7, r6 + bz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + bc 4 + halt + cmp 0, r6 + be 4 + halt + +shr_imm: +#Zero shift + mov 7, r6 + shr 0, r6 + bnz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + bnc 4 + halt + cmp 7, r6 + be 4 + halt + +#Positive to Positive, shifting out 1 + mov 7, r6 + shr 1, r6 + bnz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + bc 4 + halt + cmp 3, r6 + be 4 + halt + +#Positive to Positive, shifting out 0 + mov 6, r6 + shr 1, r6 + bnz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + bnc 4 + halt + cmp 3, r6 + be 4 + halt + +#Positive shift of negative number + mov -6, r6 + shr 1, r6 + bnz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + bnc 4 + halt + movhi hi(0x7FFFFFFD), r0, r7 + movea lo(0x7FFFFFFD), r7, r7 + cmp r7, r6 + be 4 + halt + +#Negative shift of positive number. + mov 6, r6 + shr -1, r6 # Just an unsigned shift I guess + bz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + bnc 4 + halt + cmp 0, r6 + be 4 + halt + +#Negative shift of negative number + mov -6, r6 + shr -1, r6 # Just an unsigned shift I guess + bnz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + bc 4 + halt + cmp 1, r6 + be 4 + halt + +#Shift to zero result + mov 6, r6 + shr 3, r6 + bz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + bc 4 + halt + cmp 0, r6 + be 4 + halt + +shr_reg: +#Zero shift + mov 7, r6 + mov 0, r7 + shr r7, r6 + bnz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + bnc 4 + halt + cmp 7, r6 + be 4 + halt + +#Positive to Positive, shifting out 1 + mov 7, r6 + mov 1, r7 + shr r7, r6 + bnz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + bc 4 + halt + cmp 3, r6 + be 4 + halt + +#Positive to Positive, shifting out 0 + mov 6, r6 + mov 1, r7 + shr r7, r6 + bnz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + bnc 4 + halt + cmp 3, r6 + be 4 + halt + +#Positive shift of negative number + mov -6, r6 + mov 1, r7 + shr r7, r6 + bnz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + bnc 4 + halt + movhi hi(0x7FFFFFFD), r0, r7 + movea lo(0x7FFFFFFD), r7, r7 + cmp r7, r6 + be 4 + halt + +#Negative shift of positive number. + mov 6, r6 + mov -1, r7 # Just an unsigned shift I guess + shr r7, r6 + bz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + bnc 4 + halt + cmp 0, r6 + be 4 + halt + +#Negative shift of negative number + mov -6, r6 + mov -1, r7 # Just an unsigned shift I guess + shr r7, r6 + bnz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + bc 4 + halt + cmp 1, r6 + be 4 + halt + +#Shift to zero result + mov 6, r6 + mov 3, r7 + shr r7, r6 + bz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + bc 4 + halt + cmp 0, r6 + be 4 + halt + + +shl_imm: +#Zero shift + mov -1, r6 + shl 0, r6 + bnz 4 + halt + bn 4 + halt + bnv 4 # Always + halt + bnc 4 + halt + cmp -1, r6 + be 4 + halt + +#Positive to Positive, shifting out 1 + movhi hi(0xBFFFFFFF), r0, r6 + movea lo(0xBFFFFFFF), r6, r6 + shl 1, r6 + bnz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + bc 4 + halt + movhi hi(0x7FFFFFFE), r0, r7 + movea lo(0x7FFFFFFE), r7, r7 + cmp r7, r6 + be 4 + halt + +#Positive to Positive, shifting out 0 + mov 6, r6 + shl 1, r6 + bnz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + bnc 4 + halt + cmp 12, r6 + be 4 + halt + +#Positive shift of negative number + mov -6, r6 + shl 1, r6 + bnz 4 + halt + bn 4 + halt + bnv 4 # Always + halt + bc 4 + halt + movhi hi(0xFFFFFFF4), r0, r7 + movea lo(0xFFFFFFF4), r7, r7 + cmp r7, r6 + be 4 + halt + +#Negative shift of positive number. + mov 6, r6 + shl -1, r6 # Just an unsigned shift I guess + bz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + bc 4 + halt + cmp 0, r6 + be 4 + halt + +#Negative shift of negative number + mov -6, r6 + shl -1, r6 # Just an unsigned shift I guess + bz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + bc 4 + halt + cmp 0, r6 + be 4 + halt + +#Shift to zero result + mov 8, r6 + shl 29, r6 + bz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + bc 4 + halt + cmp 0, r6 + be 4 + halt + + +shl_reg: +#Zero shift + mov 7, r6 + mov 0, r7 + shl r7, r6 + bnz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + bnc 4 + halt + cmp 7, r6 + be 4 + halt + +#Positive to Positive, shifting out 1 + movhi hi(0xBFFFFFFF), r0, r6 + movea lo(0xBFFFFFFF), r6, r6 + mov 1, r7 + shl r7, r6 + bnz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + bc 4 + halt + movhi hi(0x7FFFFFFE), r0, r7 + movea lo(0x7FFFFFFE), r7, r7 + cmp r7, r6 + be 4 + halt + +#Positive to Positive, shifting out 0 + mov 6, r6 + mov 1, r7 + shl r7, r6 + bnz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + bnc 4 + halt + cmp 12, r6 + be 4 + halt + +#Positive shift of negative number + mov -6, r6 + mov 1, r7 + shl r7, r6 + bnz 4 + halt + bn 4 + halt + bnv 4 # Always + halt + bc 4 + halt + movhi hi(0xFFFFFFF4), r0, r7 + movea lo(0xFFFFFFF4), r7, r7 + cmp r7, r6 + be 4 + halt + +#Negative shift of positive number. + mov 6, r6 + mov -1, r7 + shl r7, r6 # Just an unsigned shift I guess + bz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + bc 4 + halt + cmp 0, r6 + be 4 + halt + +#Negative shift of negative number + mov -6, r6 + mov -1, r7 + shl r7, r6 # Just an unsigned shift I guess + bz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + bc 4 + halt + cmp 0, r6 + be 4 + halt + +#Shift to zero result + mov 8, r6 + mov 29, r7 + shl r7, r6 + bz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + bc 4 + halt + cmp 0, r6 + be 4 + halt + + +xor: +#Positive + mov 0xF, r6 + mov 0xA, r7 + xor r6, r7 + bnz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + cmp 5, r7 + be 4 + halt + +#Zero + mov 0x9, r6 + mov 0x9, r7 + xor r6, r7 + bz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + cmp 0, r7 + be 4 + halt + +#Negative + mov -1, r6 + mov 0xA, r7 + xor r6, r7 + bnz 4 + halt + bn 4 + halt + bnv 4 # Always + halt + cmp -0xB, r7 + be 4 + halt + + +xori: +#Positive + mov 0xF, r6 + xori 0xA, r6, r7 + bnz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + cmp 5, r7 + be 4 + halt + +#Zero + mov 0x9, r6 + xori 0x9, r6, r7 + bz 4 + halt + bp 4 + halt + bnv 4 # Always + halt + cmp 0, r7 + be 4 + halt + +#Negative + mov -1, r6 + xori 0xA, r6, r7 + bnz 4 + halt + bn 4 + halt + bnv 4 # Always + halt + cmp -0xB, r7 + be 4 + halt + +jal: + movhi hi(jal_target), r0, r1 + movea lo(jal_target), r1, r1 + jal jal_target +jal_target: + cmp r1, r31 + be 4 + halt + movhi hi(jmp_target), r0, r1 + movea lo(jmp_target), r1, r1 + jmp [r1] + halt +jmp_target: + jr jr_target + halt +jr_target: + +stsr: +#Note that lowest bit isn't preserved... hence deadbeee + movhi hi(0xdeadbeee), r0, r1 + movea lo(0xdeadbeee), r1, r1 + ldsr r1, adtre + stsr adtre, r6 + cmp r1, r6 + be 4 + halt +#Now try writing to a readonly register + ldsr r0, pir + stsr pir, r1 + movea 0x5346, r0, r6 # VB-specific CPU ID + cmp r1, r6 + be 4 + halt + +reti: +#NP = 0 + mov 0, r1 + ldsr r1, psw + mov 5, r1 + ldsr r1, eipsw + movhi hi(trigger_reti_np0), r0, r1 + movea lo(trigger_reti_np0), r1, r1 + ldsr r1, eipc + reti #Should hop over to trigger_reti_np0 + halt +trigger_reti_np0: + stsr psw, r1 + cmp 5, r1 + be 4 + halt +#NP = 1 + mov 0, r1 + ldsr r1, psw + movea 0x804, r0, r1 + ldsr r1, eipsw + movhi hi(trigger_reti_np1), r0, r1 + movea lo(trigger_reti_np1), r1, r1 + ldsr r1, eipc + reti #Should hop over to trigger_reti_np1 + halt +trigger_reti_np1: + stsr psw, r1 + cmp 4, r1 + be 4 + halt + +trap: + movea 0x2000, r0, r1 + ldsr r1, psw # Enable + mov 0, r6 + trap 0 + halt +return_from_trap: + cmp 0xc, r6 # Was set in trap handler + be 4 + halt + movea 0x2000, r0, r1 + ldsr r1, psw # Enable + mov 0, r6 +# Trap 1 + trap 16 + halt +return_from_trap2: + cmp 0x8, r6 # Was set in trap handler + be 4 + halt + +# TODO: Floats +# TODO: Bitstrings + +#========= I / O ============================ + +words: + movhi 0x500, r0, r6 + movea 0x10, r6, r6 + movhi hi(0xdeadbeef), r0, r7 + movea lo(0xdeadbeef), r7, r7 + + st.w r7, 4[r6] + ld.w 4[r6], r8 + cmp r7, r8 + be 4 + halt + + out.w r7, -3[r6] # Unaligned write + ld.w -4[r6], r8 + cmp r7, r8 + be 4 + halt + + st.w r7, 0[r6] + in.w 3[r6], r8 # Unaligned read + cmp r7, r8 + be 4 + halt + + out.w r7, -8[r6] + in.w -8[r6], r8 + cmp r7, r8 + be 4 + halt + +halfwords: + movhi 0x500, r0, r6 + movea 0x10, r6, r6 + movhi hi(0xdeadffff), r0, r7 + movea lo(0xdeadffff), r7, r7 + movea 0xffff, r0, r9 + shr 16, r9 + +#st.h + st.w r0, 4[r6] + st.h r7, 4[r6] + ld.w 4[r6], r8 + cmp r9, r8 + be 4 + halt + +#out.h + st.w r0, -4[r6] + out.h r7, -4[r6] + ld.w -4[r6], r8 + cmp r9, r8 + be 4 + halt + +#in.h + st.w r7, 0[r6] + in.h 0[r6], r8 + cmp r9, r8 + be 4 + halt + +#ld.h + st.w r7, 0[r6] + ld.h 0[r6], r8 + cmp -1, r8 + be 4 + halt + +#out.h unaligned + st.w r0, 5[r6] + out.h r7, 5[r6] + ld.w 5[r6], r8 + cmp r9, r8 + be 4 + halt + +#in.h unaligned + st.w r7, 6[r6] + in.h 5[r6], r8 + cmp r9, r8 + be 4 + halt + + +bytes: + movhi 0x500, r0, r6 + movea 0x10, r6, r6 + movhi hi(0xdeadffff), r0, r7 + movea lo(0xdeadffff), r7, r7 + movea 0x00ff, r0, r9 + +#st.b + st.w r0, 4[r6] + st.b r7, 4[r6] + ld.w 4[r6], r8 + cmp r9, r8 + be 4 + halt + mov 13, r11 + st.b r11, -1[r6] + ld.b -1[r6], r8 + cmp r11, r8 + be 4 + halt + +#out.b + st.w r0, -5[r6] + out.b r7, -5[r6] + ld.w -5[r6], r8 # Unaligned read + shr 24, r8 # Correct for it + cmp r9, r8 + be 4 + halt + +#in.b + st.w r7, 0[r6] + in.b 0[r6], r8 + cmp r9, r8 + be 4 + halt + +#ld.b + st.w r7, 0[r6] + ld.b 0[r6], r8 + cmp -1, r8 + be 4 + halt +# Bitstrings +movbsu: + # Set up our test data. + movhi hi(0x05000000), r0, r30 + movea lo(0x05000000), r30, r30 + + # Source data + movhi hi(0x76543210), r0, r7 + movea lo(0x76543210), r7, r7 + st.w r7, 0[r30] + movhi hi(0xfedcba98), r0, r7 + movea lo(0xfedcba98), r7, r7 + st.w r7, 4[r30] + movhi hi(0xdeadbeef), r0, r7 + movea lo(0xdeadbeef), r7, r7 + st.w r7, 8[r30] + + + # Destination at 0x05000100 + addi 0x100, r30, r29 + + # Dst data (set to some known values) + movhi hi(0x11111111), r0, r7 + movea lo(0x11111111), r7, r7 + st.w r7, 0[r29] + st.w r7, 4[r29] + st.w r7, 8[r29] + st.w r7, 12[r29] + + # Copy 93 bits + movea 93, r0, r28 + + # Read from bit 4 + mov 4, r27 + + # Write starting at bit 7 + mov 7, r26 + + # Execute + movbsu + + # 0 bits left + cmp 0, r28 + be 4 + halt + + # Dst offset now 4 + cmp 4, r26 + be 4 + halt + + # Src offset now 1 + cmp 1, r27 + be 4 + halt + + # Now inspect the memory... + movhi hi(0x05000100), r0, r29 + movea lo(0x05000100), r29, r29 + + ld.w 0[r29], r6 + movhi hi(0xB2A19091), r0, r7 + movea lo(0xB2A19091), r7, r7 + cmp r6, r7 + be 4 + halt + + ld.w 4[r29], r6 + movhi hi(0xF6E5D4C3), r0, r7 + movea lo(0xF6E5D4C3), r7, r7 + cmp r6, r7 + be 4 + halt + + ld.w 8[r29], r6 + movhi hi(0xF56DF77F), r0, r7 + movea lo(0xF56DF77F), r7, r7 + cmp r6, r7 + be 4 + halt + + ld.w 12[r29], r6 + movhi hi(0x1111111E), r0, r7 + movea lo(0x1111111E), r7, r7 + cmp r6, r7 + be 4 + halt + +# Regression test for issue found in wild with sprintf and memmove +movbsu2: + # Copy from rom. + movhi hi(_rom_title), r0, r30 + movea lo(_rom_title), r30, r30 + + # Destination at 0x0500ff04 + movhi hi(0x0500ff04), r0, r29 + movea lo(0x0500ff04), r29, r29 + + # Clear dst to zeros + st.w r0, 0[r29] + st.w r0, 4[r29] + st.w r0, 8[r29] + st.w r0, 12[r29] + + # Copied inputs from emulator, but both should mask to bit 0 + movhi hi(0x2807f820), r0, r26 + movea lo(0x2807f820), r26, r26 + movhi hi(0x3801f480), r0, r27 + movea lo(0x3801f480), r27, r27 + movea 64, r0, r28 + + + # Execute + movbsu + + # 0 bits left + cmp 0, r28 + be 4 + halt + + # Dst offset now 4 + cmp 0, r26 + be 4 + halt + + # Src offset now 1 + cmp 0, r27 + be 4 + halt + + ld.w -8[r29], r6 + ld.w -8[r30], r7 + cmp r6, r7 + be 4 + halt + + ld.w -4[r29], r6 + ld.w -4[r30], r7 + cmp r6, r7 + be 4 + halt + +caxi: + movhi 0x500, r0, r6 + movea 0x10, r6, r6 + # Success + mov 13, r1 + st.w r1, 0[r6] + mov 7, r30 + caxi 0[r6], r1 + be 4 + halt + ld.w 0[r6], r7 + cmp r7, r30 + be 4 + halt + # Fail + st.w r0, 0[r6] + mov 7, r30 + caxi 0[r6], r1 + bne 4 + halt + ld.w 0[r6], r7 + cmp r7, r30 + bne 4 + halt + + mov 0, r10 # Loop start + movea 16, r0, r11 # Loop end +setf: + cmp r11, r10 + be setf_done + + ldsr r10, psw + + # Just check that the four flags match + # TODO: Check all conditions + setf z, r6 # Zero + setf n, r7 # Sign + setf v, r8 # OV + setf c, r9 # Carry + shl 1, r9 + or r8, r9 + shl 1, r9 + or r7, r9 + shl 1, r9 + or r6, r9 + cmp r9, r10 + be 4 + halt + + add 1, r10 # Inc loop + br setf + +setf_done: + +xb: + movhi hi(0x12345678), r0, r1 + movea lo(0x12345678), r1, r1 + xb r1 + movhi hi(0x12347856), r0, r6 + movea lo(0x12347856), r6, r6 + cmp r1, r6 + be 4 + halt + +xh: + movhi hi(0x12345678), r0, r1 + movea lo(0x12345678), r1, r1 + xh r1 + movhi hi(0x56781234), r0, r6 + movea lo(0x56781234), r6, r6 + cmp r1, r6 + be 4 + halt + +rev: + movhi hi(0x12345678), r0, r1 + movea lo(0x12345678), r1, r1 + rev r1, r1 + movhi hi(0x1E6A2C48), r0, r6 + movea lo(0x1E6A2C48), r6, r6 + cmp r1, r6 + be 4 + halt + + +skip: +done: + br 0 + + .section ".rom_header","ax" + .align 1 + +.global _rom_title + +/* Rom info table (07FFFDE0h) */ +_rom_title: + .ascii "Emulator Gauntlet " /* Simulation Title */ + .byte 0x00,0x00,0x00,0x00,0x00 /* Reserved */ + .ascii "PREACT" /* Manufacture/Simulation ID */ + .byte 0x00 /* Rom Version */ + + +.section ".interrupt_handlers", "ax" + /* INTKEY (7FFFE00h) - Controller Interrupt */ + .fill 0x10 + + /* INTTIM (7FFFE10h) - Timer Interrupt */ + .fill 0x10 + + /* INTCRO (7FFFE20h) - Expansion Port Interrupt */ + .fill 0x10 + + /* INTCOM (7FFFE30h) - Link Port Interrupt */ + .fill 0x10 + + /* INTVPU (7FFFE40h) - Video Retrace Interrupt */ + .fill 0x10 + + /* Unused vectors (7FFFE50h-7FFFF5Fh) */ + .fill 0x110 + + /* (7FFFF60h) - Float exception */ + .fill 0x10 + + /* Unused vector */ + .fill 0x10 + + /* (7FFFF80h) - Divide by zero exception */ + .fill 0x10 + + /* (7FFFF90h) - Invalid Opcode exception */ + reti + .fill 0x0E + + /* (7FFFFA0h) - Trap 0 exception */ + mov 0xc, r6 # Magic number to prove trap was hit + movhi hi(return_from_trap), r0, r1 + movea lo(return_from_trap), r1, r1 + jmp [r1] + .fill 0x04 + + /* (7FFFFB0h) - Trap 1 exception */ + mov 0x8, r6 # Magic number to prove trap was hit + movhi hi(return_from_trap2), r0, r1 + movea lo(return_from_trap2), r1, r1 + jmp [r1] + .fill 0x04 + + /* (7FFFFC0h) - Trap Address exception */ + .fill 0x10 + + /* (7FFFFD0h) - NMI/Duplex exception */ + .fill 0x10 + + /* Unused vector */ + .fill 0x10 + + /* Reset Vector (7FFFFF0h) - This is how the ROM boots */ + movhi hi(start), r0, r1 + movea lo(start), r1, r1 + jmp [r1] + nop + nop + nop diff --git a/makefile b/makefile new file mode 100644 index 0000000..657074b --- /dev/null +++ b/makefile @@ -0,0 +1,46 @@ +# Set the project name here +NAME = gauntlet + +OUTPUTDIR = output +TOOLCHAIN_ARCH := v810 +TOOLCHAIN_DIR := $(HOME)/llvm-v810 + +# The rest of the Makefile should not need changing ... +BINDIR = $(TOOLCHAIN_DIR)/bin +INCDIR = $(TOOLCHAIN_DIR)/include +LIBDIR = $(TOOLCHAIN_DIR)/lib + +AS = $(BINDIR)/llvm-mc +CC = $(BINDIR)/clang +LD = $(BINDIR)/ld.lld +OBJCOPY = $(BINDIR)/llvm-objcopy + +ASFLAGS += --triple v810-unknown-vb -mcpu=vb --filetype=obj -g +LDFLAGS += -target v810-unknown-vb -mcpu=vb --ld-path=$(LD) -L$(LIBDIR) -Tvb.ld -nolibc -flto + +SFILES := $(foreach dir,./,$(notdir $(wildcard $(dir)/*.s))) + +SOBJS := $(OUTPUTDIR)/$(SFILES:.s=.o) + +OFILES := $(SOBJS) +ELFFILES := $(OUTPUTDIR)/$(NAME).elf +VBFILES := $(OUTPUTDIR)/$(NAME).vb + +.PHONY: all clean distclean + +all: $(VBFILES) + +$(VBFILES): $(ELFFILES) + @$(OBJCOPY) -S -O binary $< $@ + +$(ELFFILES): $(OFILES) + @$(CC) $(OFILES) $(LDFLAGS) -o $@ + +$(SOBJS): $(SFILES) + @$(AS) $(ASFLAGS) -o $@ $< + +clean: +# @rm -f $(OFILES) $(VBFILES) $(ELFFILES) + @rm -f output/* + +distclean: clean diff --git a/vb.ld b/vb.ld new file mode 100644 index 0000000..a9be021 --- /dev/null +++ b/vb.ld @@ -0,0 +1,98 @@ +OUTPUT_FORMAT("elf32-v810", "elf32-v810", "elf32-v810") +OUTPUT("a.elf") /* force elf format output */ +OUTPUT_ARCH(v810) +TARGET(elf32-v810) +ENTRY(start) +SEARCH_DIR(.); + +MEMORY { + ram (!r): ORIGIN = 0x05000000, LENGTH = 64k /*64k*/ + rom (rx): ORIGIN = 0x07000000, LENGTH = 16M +} + +__text_vma = 0x07000000; +__data_vma = 0x05000000; + +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + .text __text_vma : { + *(.text) + *(.text.*) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + *(.gnu.linkonce.t*) + } >rom = 0xFF + + .rodata : { + *(.rodata) + *all.rodata*(*) + *(.roda) + *(.rodata.*) + *(.gnu.linkonce.r*) + /* SORT(CONSTRUCTORS) */ + } >rom = 0xFF + + /* C++ Constructor/Destructor table */ + /* + .ctors : { + ___ctors = .; + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend(.ctors)) + ___ctors_end = .; + } >rom = 0xFF + + .dtors : { + ___dtors = .; + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + ___dtors_end = .; + } >rom = 0xFF + */ + + /* Stop empty section from causing a compiler error */ + /DISCARD/ : { + *(.comment) + } + + /* Place orphan ROM data here */ + /* . = .; */ + + /* Ram memory */ + + __data_lma = .; + .data __data_vma : AT(__data_lma) { + *(.data) + *(.data.*) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.d*) + /* CONSTRUCTORS */ + } >ram = 0xFF + + __data_end = .; + + .bss : { + *(.dynbss) + *(.bss) + *(.sdata) + *(.sbss) + *(COMMON) + } >ram = 0xFF + /* These must appear regardless of . */ + + + /* Compute the vector address */ + /* Prevent overlaps with vbvectors */ + __sections_size = SIZEOF(.text) + SIZEOF(.rodata) + SIZEOF(.data); + __rom_size = 1 << LOG2CEIL(__sections_size + 0x220); + __rom_end = ORIGIN(rom) + __rom_size; + + /* Place interupt and reset vector at end of rom */ + + .vbvectors 0x07FFFDE0 : AT(__rom_end - 0x220) { + KEEP (*(.vbvectors)) + } >rom = 0xFF +}