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pvbemu/src/core/cpu.c

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Laying the groundwork for the CPU
2020-08-06 01:40:23 +00:00
/* This file is included through vue.c and cannot be built directly. */
#ifdef VUEAPI
/*****************************************************************************
* Constants *
*****************************************************************************/
/* Stages */
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#define CPU_FATAL -1
#define CPU_FETCH 0
#define CPU_EXECUTE 1
#define CPU_EXCEPTION 2
#define CPU_HALT 3
#define CPU_CLEAR 4
#define CPU_DUMP 5
#define CPU_RESTORE 6
Laying the groundwork for the CPU
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Implementing instruction decoder
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/* Intermediate instruction IDs */
#define BITSTRING -2
#define FLOATENDO -3
/* Opcode lookup table */
static const int8_t LOOKUP_OPCODE[] = {
VUE_MOV_REG, 1, VUE_ADD_REG, 1, VUE_SUB , 1, VUE_CMP_REG, 1,
VUE_SHL_REG, 1, VUE_SHR_REG, 1, VUE_JMP , 1, VUE_SAR_REG, 1,
VUE_MUL , 1, VUE_DIV , 1, VUE_MULU , 1, VUE_DIVU , 1,
VUE_OR , 1, VUE_AND , 1, VUE_XOR , 1, VUE_NOT , 1,
Implementing disassembler interface
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VUE_MOV_IMM,-2, VUE_ADD_IMM,-2, VUE_SETF , 2, VUE_CMP_IMM,-2,
Implementing instruction decoder
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VUE_SHL_IMM, 2, VUE_SHR_IMM, 2, VUE_CLI , 2, VUE_SAR_IMM, 2,
VUE_TRAP , 2, VUE_RETI , 2, VUE_HALT , 2, VUE_ILLEGAL, 0,
VUE_LDSR , 2, VUE_STSR , 2, VUE_SEI , 2, BITSTRING , 2,
VUE_BCOND , 3, VUE_BCOND , 3, VUE_BCOND , 3, VUE_BCOND , 3,
VUE_BCOND , 3, VUE_BCOND , 3, VUE_BCOND , 3, VUE_BCOND , 3,
Implementing disassembler interface
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VUE_MOVEA ,-5, VUE_ADDI ,-5, VUE_JR , 4, VUE_JAL , 4,
Implementing instruction decoder
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VUE_ORI , 5, VUE_ANDI , 5, VUE_XORI , 5, VUE_MOVHI , 5,
VUE_LD_B , 6, VUE_LD_H , 6, VUE_ILLEGAL, 0, VUE_LD_W , 6,
VUE_ST_B , 6, VUE_ST_H , 6, VUE_ILLEGAL, 0, VUE_ST_W , 6,
VUE_IN_B , 6, VUE_IN_H , 6, VUE_CAXI , 6, VUE_IN_W , 6,
VUE_OUT_B , 6, VUE_OUT_H , 6, FLOATENDO , 7, VUE_OUT_W , 6
};
/* Bit string lookup table */
static const int8_t LOOKUP_BITSTRING[] = {
VUE_SCH0BSU, VUE_SCH0BSD, VUE_SCH1BSU, VUE_SCH1BSD,
VUE_ILLEGAL, VUE_ILLEGAL, VUE_ILLEGAL, VUE_ILLEGAL,
VUE_ORBSU , VUE_ANDBSU , VUE_XORBSU , VUE_MOVBSU ,
VUE_ORNBSU , VUE_ANDNBSU, VUE_XORNBSU, VUE_XORNBSU
};
/* Floating-point and Nintendo lookup table */
static const int8_t LOOKUP_FLOATENDO[] = {
VUE_CMPF_S , VUE_ILLEGAL, VUE_CVT_WS , VUE_CVT_SW ,
VUE_ADDF_S , VUE_SUBF_S , VUE_MULF_S , VUE_DIVF_S ,
VUE_XB , VUE_XH , VUE_REV , VUE_TRNC_SW,
VUE_MPYHW , VUE_ILLEGAL, VUE_ILLEGAL, VUE_ILLEGAL
};
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/* Instruction cycle counts */
static const int8_t CYCLES[] = {
1, 1, 28, 1, 1, 1, 1, 1, 1, 26, 12, 1, 1, 10, 14, 16,
38, 44, 36, 1, 5, 5, 5, 3, 3, 3, 5, 5, 5, 8, 1, 1,
1, 1, 1, 9, 13, 30, 13, 1, 1, 1, 1, 1, 1, 4, 4, 4,
10, 22, 1, 1, 1, 1, 1, 1, 12, 1, 1, 1, 1, 1, 4, 4,
4, 8, 1, 28, 15, 14, 6, 1, 1, 1, 1, 1
};
Implementing instruction decoder
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/*****************************************************************************
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* Instruction Functions *
*****************************************************************************/
/* JMP */
static void cpuJMP(VUE *vue) {
vue->cpu.pc = vue->cpu.program[vue->cpu.inst.reg1] - 2;
}
/* MOVEA */
static void cpuMOVEA(VUE *vue) {
vue->cpu.program[vue->cpu.inst.reg2] =
vue->cpu.program[vue->cpu.inst.reg1] + vue->cpu.inst.imm;
}
/* MOVHI */
static void cpuMOVHI(VUE *vue) {
vue->cpu.program[vue->cpu.inst.reg2] =
vue->cpu.program[vue->cpu.inst.reg1] + (vue->cpu.inst.imm << 16);
}
/*****************************************************************************
* Stage Functions *
Implementing instruction decoder
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*****************************************************************************/
/* Decode an instruction from its binary encoding */
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static void cpuDecode(VUE_INSTRUCTION *inst) {
Revising instruction decoder, jump history
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int8_t extend; /* Sign-extend the immediate operand */
int32_t x; /* Working variable */
Implementing instruction decoder
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/* Configure instance fields */
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inst->opcode = inst->bits >> 26 & 63;
Implementing disassembler interface
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x = inst->opcode << 1;
inst->id = LOOKUP_OPCODE[x ];
extend = LOOKUP_OPCODE[x + 1];
inst->format = extend < 0 ? -extend : extend;
Revising instruction decoder, jump history
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inst->size = inst->format < 4 ? 2 : 4;
Implementing instruction decoder
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/* Decode by format */
switch (inst->format) {
Revising instruction decoder, jump history
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case 1:
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inst->reg2 = inst->bits >> 21 & 31;
inst->reg1 = inst->bits >> 16 & 31;
Revising instruction decoder, jump history
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break;
case 2:
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x = inst->bits >> 16 & 31;
inst->reg2 = inst->bits >> 21 & 31;
Revising instruction decoder, jump history
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inst->imm = extend < 0 ? SIGN_EXTEND(5, x) : x;
if (inst->id == BITSTRING)
inst->id = x >= 16 ? VUE_ILLEGAL : LOOKUP_BITSTRING[x];
break;
case 3:
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x = inst->bits >> 16 & 0x1FF;
Revising instruction decoder, jump history
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inst->opcode = 0x20;
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inst->cond = inst->bits >> 25 & 15;
Revising instruction decoder, jump history
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inst->disp = SIGN_EXTEND(9, x);
break;
case 4:
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x = inst->bits & 0x3FFFFFF;
Revising instruction decoder, jump history
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inst->disp = SIGN_EXTEND(26, x);
break;
case 5:
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x = inst->bits & 0xFFFF;
inst->reg2 = inst->bits >> 21 & 31;
inst->reg1 = inst->bits >> 16 & 31;
Revising instruction decoder, jump history
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inst->imm = extend < 0 ? SIGN_EXTEND(16, x) : x;
break;
case 6:
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x = inst->bits & 0xFFFF;
inst->reg2 = inst->bits >> 21 & 31;
inst->reg1 = inst->bits >> 16 & 31;
Revising instruction decoder, jump history
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inst->disp = SIGN_EXTEND(16, x);
break;
case 7:
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inst->reg2 = inst->bits >> 21 & 31;
inst->reg1 = inst->bits >> 16 & 31;
inst->subopcode = inst->bits >> 10 & 63;
Revising instruction decoder, jump history
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inst->id = inst->subopcode >= 16 ? VUE_ILLEGAL :
LOOKUP_FLOATENDO[inst->subopcode];
break;
Implementing instruction decoder
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}
}
Additional work on emulation/CPU logic, implementing in C code
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/* Check for an exception or interrupt */
static vbool cpuTestException(VUE *vue) {
int32_t level; /* Interrupt level */
/* Check for an interrupt */
if (vue->cpu.irq != 0 && (vue->cpu.exception.code |
vue->cpu.psw_id | vue->cpu.psw_ep | vue->cpu.psw_np) == 0) {
for (level = 4; level >= 0; level--)
if ((vue->cpu.irq >> level & 1) != 0)
break;
vue->cpu.exception.code = 0xFE00 | level << 4;
}
/* There is no exception */
if (vue->cpu.exception.code == 0) /* No further processing */
return vue->cpu.stage == CPU_HALT && vue->cpu.cycles == 0;
/* An exception has occurred */
vue->cpu.cycles = 0;
vue->cpu.stage = CPU_EXCEPTION;
return VUE_FALSE;
}
/* Operations for execute stage */
static vbool cpuExecute(VUE *vue) {
/* Application callback */
if (vue->onExecute != NULL) {
vue->breakCode = vue->onExecute(vue, &vue->cpu.inst);
if (vue->breakCode != 0)
return VUE_TRUE;
}
/* Determine the default number of cycles for the instruction */
if (vue->cpu.inst.id >= 0 && vue->cpu.inst.id <= 75)
vue->cpu.cycles = CYCLES[vue->cpu.inst.id];
/* Processing by instruction ID */
switch (vue->cpu.inst.id) {
/*case VUE_ADD_IMM: cpuADD_IMM(vue); break;*/
/*case VUE_ADD_REG: cpuADD_REG(vue); break;*/
/*case VUE_ADDF_S : cpuADDF_S (vue); break;*/
/*case VUE_ADDI : cpuADDI (vue); break;*/
/*case VUE_AND : cpuAND (vue); break;*/
/*case VUE_ANDBSU : cpuANDBSU (vue); break;*/
/*case VUE_ANDI : cpuANDI (vue); break;*/
/*case VUE_ANDNBSU: cpuANDNBSU(vue); break;*/
/*case VUE_BCOND : cpuBCOND (vue); break;*/
/*case VUE_CAXI : cpuCAXI (vue); break;*/
/*case VUE_CLI : cpuCLI (vue); break;*/
/*case VUE_CMP_IMM: cpuCMP_IMM(vue); break;*/
/*case VUE_CMP_REG: cpuCMP_REG(vue); break;*/
/*case VUE_CMPF_S : cpuCMPF_S (vue); break;*/
/*case VUE_CVT_SW : cpuCVT_SW (vue); break;*/
/*case VUE_CVT_WS : cpuCVT_WS (vue); break;*/
/*case VUE_DIV : cpuDIV (vue); break;*/
/*case VUE_DIVF_S : cpuDIVF_S (vue); break;*/
/*case VUE_DIVU : cpuDIVU (vue); break;*/
/*case VUE_HALT : cpuHALT (vue); break;*/
/*case VUE_IN_B : cpuIN_B (vue); break;*/
/*case VUE_IN_H : cpuIN_H (vue); break;*/
/*case VUE_IN_W : cpuIN_W (vue); break;*/
/*case VUE_JAL : cpuJAL (vue); break;*/
case VUE_JMP : cpuJMP (vue); break;
/*case VUE.JR : cpuJR (vue); break;*/
/*case VUE.LD_B : cpuLD_B (vue); break;*/
/*case VUE.LD_H : cpuLD_H (vue); break;*/
/*case VUE.LD_W : cpuLD_W (vue); break;*/
/*case VUE.LDSR : cpuLDSR (vue); break;*/
/*case VUE.MOV_IMM: cpuMOV_IMM(vue); break;*/
/*case VUE.MOV_REG: cpuMOV_REG(vue); break;*/
/*case VUE.MOVBSU : cpuMOVBSU (vue); break;*/
case VUE_MOVEA : cpuMOVEA (vue); break;
case VUE_MOVHI : cpuMOVHI (vue); break;
/*case VUE.MPYHW : cpuMPYHW (vue); break;*/
/*case VUE.MUL : cpuMUL (vue); break;*/
/*case VUE.MULF_S : cpuMULF_S (vue); break;*/
/*case VUE.MULU : cpuMULU (vue); break;*/
/*case VUE.NOT : cpuNOT (vue); break;*/
/*case VUE.NOTBSU : cpuNOTBSU (vue); break;*/
/*case VUE.OR : cpuOR (vue); break;*/
/*case VUE.ORBSU : cpuORBSU (vue); break;*/
/*case VUE.ORI : cpuORI (vue); break;*/
/*case VUE.ORNBSU : cpuORNBSU (vue); break;*/
/*case VUE.OUT_B : cpuOUT_B (vue); break;*/
/*case VUE.OUT_H : cpuOUT_H (vue); break;*/
/*case VUE.OUT_W : cpuOUT_W (vue); break;*/
/*case VUE.RETI : cpuRETI (vue); break;*/
/*case VUE.REV : cpuREV (vue); break;*/
/*case VUE.SAR_IMM: cpuSAR_IMM(vue); break;*/
/*case VUE.SAR_REG: cpuSAR_REG(vue); break;*/
/*case VUE.SCH0BSD: cpuSCH0BSD(vue); break;*/
/*case VUE.SCH0BSU: cpuSCH0BSU(vue); break;*/
/*case VUE.SCH1BSD: cpuSCH1BSD(vue); break;*/
/*case VUE.SCH1BSU: cpuSCH1BSU(vue); break;*/
/*case VUE.SEI : cpuSEI (vue); break;*/
/*case VUE.SETF : cpuSETF (vue); break;*/
/*case VUE.SHL_IMM: cpuSHL_IMM(vue); break;*/
/*case VUE.SHL_REG: cpuSHL_REG(vue); break;*/
/*case VUE.SHR_IMM: cpuSHR_IMM(vue); break;*/
/*case VUE.SHR_REG: cpuSHR_REG(vue); break;*/
/*case VUE.ST_B : cpuST_B (vue); break;*/
/*case VUE.ST_H : cpuST_H (vue); break;*/
/*case VUE.ST_W : cpuST_W (vue); break;*/
/*case VUE.STSR : cpuSTSR (vue); break;*/
/*case VUE.SUB : cpuSUB (vue); break;*/
/*case VUE.SUBF_S : cpuSUBF_S (vue); break;*/
/*case VUE.TRAP : cpuTRAP (vue); break;*/
/*case VUE.TRNC_SW: cpuTRNC_SW(vue); break;*/
/*case VUE.XB : cpuXB (vue); break;*/
/*case VUE.XH : cpuXH (vue); break;*/
/*case VUE.XOR : cpuXOR (vue); break;*/
/*case VUE.XORBSU : cpuXORBSU (vue); break;*/
/*case VUE.XORI : cpuXORI (vue); break;*/
/*case VUE.XORNBSU: cpuXORNBSU(vue); break;*/
default: /* Invalid instruction */
vue->cpu.exception.code = 0xFF90;
vue->cpu.inst.size = 0;
}
/* Common processing */
vue->cpu.pc += vue->cpu.inst.size;
vue->cpu.program[0] = 0;
cpuTestException(vue);
if (vue->cpu.stage == CPU_EXECUTE)
vue->cpu.stage = CPU_FETCH;
return VUE_FALSE;
}
/* Determine the size of an instruction given its opcode */
static int32_t cpuSize(int32_t opcode) {
int32_t ret = LOOKUP_OPCODE[opcode << 1 | 1];
return (ret < 0 ? -ret : ret) < 4 ? 2 : 4;
}
/* Operations for fetch stage */
static vbool cpuFetch(VUE *vue) {
/* Read the bits from the bus */
vue->cpu.access.address = vue->cpu.pc + (vue->cpu.fetch << 1);
vue->cpu.access.fetch = vue->cpu.fetch;
vue->cpu.access.type = VUE_U16;
vue->cpu.access.value = vueRead(vue, vue->cpu.access.address, VUE_U16);
/* Application callback */
if (vue->onRead != NULL) {
vue->breakCode = vue->onRead(vue, &vue->cpu.access);
if (vue->breakCode != 0)
return VUE_TRUE;
}
/* First unit */
if (vue->cpu.fetch == 0) {
vue->cpu.inst.bits = vue->cpu.access.value << 16;
if (cpuSize(vue->cpu.access.value >> 10 & 0x3F) == 4) {
vue->cpu.fetch = 1;
return VUE_FALSE;
}
}
/* Second unit */
else {
vue->cpu.inst.bits |= vue->cpu.access.value & 0xFFFF;
vue->cpu.fetch = 0;
}
/* Decode the instruction and advance to execute stage */
cpuDecode(&vue->cpu.inst);
vue->cpu.stage = CPU_EXECUTE;
return VUE_FALSE;
}
Laying the groundwork for the CPU
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/* Read a system register */
Laying groundwork for emulation, re-implementing memory bus
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static int32_t cpuGetSystemRegister(VUE *vue, int32_t index) {
Laying the groundwork for the CPU
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switch (index) {
case VUE_ADTRE: return vue->cpu.adtre;
case VUE_EIPC : return vue->cpu.eipc;
case VUE_EIPSW: return vue->cpu.eipsw;
case VUE_FEPC : return vue->cpu.fepc;
case VUE_FEPSW: return vue->cpu.fepsw;
case VUE_ECR : return vue->cpu.ecr_fecc << 16 | vue->cpu.ecr_eicc;
case VUE_PIR : return 0x00005346;
case VUE_TKCW : return 0x000000E0;
case VUE_CHCW : return vue->cpu.chcw_ice << 1;
case 29 : return vue->cpu.sr29;
case 30 : return 0x00000004;
case 31 : return vue->cpu.sr31;
case VUE_PSW : return
vue->cpu.psw_i << 16 | vue->cpu.psw_fov << 6 |
vue->cpu.psw_np << 15 | vue->cpu.psw_fud << 5 |
vue->cpu.psw_ep << 14 | vue->cpu.psw_fpr << 4 |
vue->cpu.psw_ae << 13 | vue->cpu.psw_cy << 3 |
vue->cpu.psw_id << 12 | vue->cpu.psw_ov << 2 |
vue->cpu.psw_fro << 9 | vue->cpu.psw_s << 1 |
vue->cpu.psw_fiv << 8 | vue->cpu.psw_z |
vue->cpu.psw_fzd << 7
;
/* Remaining cases to encourage tableswitch */
case 8: case 9: case 10: case 11: case 12: case 13: case 14:
case 15: case 16: case 17: case 18: case 19: case 20: case 21:
case 22: case 23: case 26: case 27: case 28:
return 0;
}
return 1; /* Unreachable */
}
Additional work on emulation/CPU logic, implementing in C code
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/* Operations for exception stage */
static vbool cpuException(VUE *vue) {
vbool isIRQ; /* The exception is an interrupt */
int32_t psw; /* Current value of PSW */
/* Application callback */
if (vue->onException != NULL) {
vue->breakCode = vue->onException(vue, &vue->cpu.exception);
if (vue->breakCode != 0)
return VUE_TRUE;
}
/* Configure working variables */
vue->cpu.exception.code &= 0xFFFF;
isIRQ = (vue->cpu.exception.code & 0xFF00) == 0xFE00;
psw = cpuGetSystemRegister(vue, VUE_PSW);
/* Fatal exception */
if (vue->cpu.psw_np != 0) {
vueWrite(vue, 0x00000000, VUE_S32, 0xFFFF0000|vue->cpu.exception.code);
vueWrite(vue, 0x00000004, VUE_S32, psw);
vueWrite(vue, 0x00000008, VUE_S32, vue->cpu.pc);
vue->cpu.stage = CPU_FATAL;
return VUE_TRUE;
}
/* Duplexed exception */
if (vue->cpu.psw_ep != 0) {
vue->cpu.ecr_fecc = vue->cpu.exception.code;
vue->cpu.fepc = vue->cpu.pc;
vue->cpu.fepsw = psw;
vue->cpu.psw_np = 1;
vue->cpu.pc = 0xFFFFFFD0;
}
/* Regular exception */
else {
vue->cpu.ecr_eicc = vue->cpu.exception.code;
vue->cpu.eipc = vue->cpu.pc;
vue->cpu.eipsw = psw;
vue->cpu.psw_ep = 1;
vue->cpu.pc = 0xFFFF0000 | (vue->cpu.exception.code & 0xFFF0);
if (vue->cpu.pc == (int32_t) 0xFFFFFF70) /* FIV */
vue->cpu.pc = 0xFFFFFF60;
}
/* Interrupt */
if (isIRQ) {
psw = vue->cpu.exception.code >> 4 & 15;
vue->cpu.psw_i = psw < 15 ? psw : 15;
}
/* Common processing */
vue->cpu.cycles = 0; /* TODO: Determine the actual number */
vue->cpu.exception.code = 0;
vue->cpu.psw_ae = 0;
vue->cpu.psw_id = 1;
vue->cpu.stage = CPU_FETCH;
return VUE_FALSE;
}
/* Process the simulation */
static void cpuEmulate(VUE *vue, int32_t cycles) {
/* The CPU is in permanent halt */
if (vue->cpu.stage == CPU_FATAL)
return;
vue->cpu.cycles = 0; /* DEBUG: Stop processing after execute */
/* Process for the given number of cycles */
for (;;) {
/* The next event occurs after the given number of cycles */
if (vue->cpu.cycles > cycles) {
vue->cpu.cycles -= cycles;
return;
}
/* Processing by stage */
switch (vue->cpu.stage) {
case CPU_EXCEPTION: if (cpuException (vue)) return; break;
case CPU_EXECUTE : if (cpuExecute (vue)) return; break;
case CPU_FETCH : if (cpuFetch (vue)) return; break;
case CPU_HALT : if (cpuTestException(vue)) return; break;
}
}
}
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/* Write a system register */
Laying groundwork for emulation, re-implementing memory bus
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static int32_t cpuSetSystemRegister(VUE *vue, int32_t index, int32_t value,
Laying the groundwork for the CPU
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vbool debug) {
switch (index) {
case VUE_ADTRE: return vue->cpu.adtre = value & 0xFFFFFFFE;
case VUE_EIPC : return vue->cpu.eipc = value & 0xFFFFFFFE;
case VUE_EIPSW: return vue->cpu.eipsw = value & 0x000FF3FF;
case VUE_FEPC : return vue->cpu.fepc = value & 0xFFFFFFFE;
case VUE_FEPSW: return vue->cpu.fepsw = value & 0x000FF3FF;
case 29 : return vue->cpu.sr29 = value;
case 31 : return vue->cpu.sr31 =
debug || value >= 0 ? value : -value;
case VUE_CHCW :
vue->cpu.chcw_cen = value >> 20 & 0x00000FFF;
vue->cpu.chcw_cec = value >> 8 & 0x00000FFF;
vue->cpu.chcw_sa = value >> 8 & 0x00FFFFFF;
vue->cpu.chcw_icr = value >> 5 & 1;
vue->cpu.chcw_icd = value >> 4 & 1;
vue->cpu.chcw_ice = value >> 1 & 1;
vue->cpu.chcw_icc = value & 1;
/* Only one of ICC, ICD or ICR is set */
value &= 0x00000031;
if ((value & (value - 1)) == 0) {
/* Clear */
/* Dump */
/* Restore */
}
return vue->cpu.chcw_ice << 1;
Introducing CPU register lists
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case VUE_ECR:
if (debug) {
vue->cpu.ecr_fecc = value >> 16 & 0xFFFF;
vue->cpu.ecr_eicc = value & 0xFFFF;
}
return vue->cpu.ecr_fecc << 16 | vue->cpu.ecr_eicc;
Laying the groundwork for the CPU
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case VUE_PSW :
vue->cpu.psw_i = value >> 16 & 15;
vue->cpu.psw_np = value >> 15 & 1;
vue->cpu.psw_ep = value >> 14 & 1;
vue->cpu.psw_ae = value >> 13 & 1;
vue->cpu.psw_id = value >> 12 & 1;
vue->cpu.psw_fro = value >> 9 & 1;
vue->cpu.psw_fiv = value >> 8 & 1;
vue->cpu.psw_fzd = value >> 7 & 1;
vue->cpu.psw_fov = value >> 6 & 1;
vue->cpu.psw_fud = value >> 5 & 1;
vue->cpu.psw_fpr = value >> 4 & 1;
vue->cpu.psw_cy = value >> 3 & 1;
vue->cpu.psw_ov = value >> 2 & 1;
vue->cpu.psw_s = value >> 1 & 1;
vue->cpu.psw_z = value & 1;
return value & 0x000FF3FF;
/* Remaining cases to encourage tableswitch */
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case 6: case 7: case 8: case 9: case 10: case 11: case 12:
case 13: case 14: case 15: case 16: case 17: case 18: case 19:
case 20: case 21: case 22: case 23: case 26: case 27: case 28:
case 30:
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return 0;
}
return 1; /* Unreachable */
}
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/* System reset */
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static void cpuReset(VUE *vue) {
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int32_t x;
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/* Configure instance fields */
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vue->cpu.cycles = 0;
vue->cpu.exception.code = 0;
vue->cpu.fetch = 0;
vue->cpu.irq = 0;
vue->cpu.stage = CPU_FETCH;
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/* Clear all registers (hardware only sets ECR, PC and PSW) */
for (x = 0; x < 32; x++) {
vue->cpu.program[x] = 0;
cpuSetSystemRegister(vue, x, 0, VUE_TRUE);
}
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/* Configure jump history */
for (x = 0; x < 3; x++)
vue->cpu.jumpFrom[x] = vue->cpu.jumpTo[x] = 0xFFFFFFF0;
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/* Configure registers */
vue->cpu.ecr_eicc = 0xFFF0;
vue->cpu.pc = 0xFFFFFFF0;
vue->cpu.psw_np = 1;
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}
/* Test a condition */
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static int8_t cpuTestCondition(VUE *vue, int32_t condition) {
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switch (condition) {
case 0: return vue->cpu.psw_ov;
case 1: return vue->cpu.psw_cy;
case 2: return vue->cpu.psw_z;
case 3: return vue->cpu.psw_cy | vue->cpu.psw_z;
case 4: return vue->cpu.psw_s;
case 5: return 1;
case 6: return vue->cpu.psw_ov | vue->cpu.psw_s;
case 7: return (vue->cpu.psw_ov ^ vue->cpu.psw_s) | vue->cpu.psw_z;
}
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return cpuTestCondition(vue, condition & 7) ^ 1;
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}
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/* Determine the number of CPU cycles until something can happen */
static int32_t cpuUntil(VUE *vue, int32_t cycles) {
if (vue->cpu.stage == CPU_FATAL || vue->cpu.stage == CPU_HALT)
return cycles;
return cycles < 0 ? vue->cpu.cycles :
cycles < vue->cpu.cycles ? cycles : vue->cpu.cycles;
}
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#endif