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pvbemu/core/cpu.c

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/* This file is included into vb.c and cannot be compiled on its own. */
#ifdef VBAPI
/********************************* Constants *********************************/
/* Operations states */
#define CPU_FETCH 0
#define CPU_EXECUTE 1
#define CPU_EXCEPTION 2
#define CPU_HALTED 3
#define CPU_FATAL 4
/* Instruction IDs */
#define CPU_ILLEGAL -1
#define CPU_ADD_IMM 0
#define CPU_ADD_REG 1
#define CPU_ADDF_S 2
#define CPU_ADDI 3
#define CPU_AND 4
#define CPU_ANDBSU 5
#define CPU_ANDI 6
#define CPU_ANDNBSU 7
#define CPU_BCOND 8
#define CPU_CAXI 9
#define CPU_CLI 10
#define CPU_CMP_IMM 11
#define CPU_CMP_REG 12
#define CPU_CMPF_S 13
#define CPU_CVT_SW 14
#define CPU_CVT_WS 15
#define CPU_DIV 16
#define CPU_DIVF_S 17
#define CPU_DIVU 18
#define CPU_HALT 19
#define CPU_IN_B 20
#define CPU_IN_H 21
#define CPU_IN_W 22
#define CPU_JAL 23
#define CPU_JMP 24
#define CPU_JR 25
#define CPU_LD_B 26
#define CPU_LD_H 27
#define CPU_LD_W 28
#define CPU_LDSR 29
#define CPU_MOV_IMM 30
#define CPU_MOV_REG 31
#define CPU_MOVBSU 32
#define CPU_MOVEA 33
#define CPU_MOVHI 34
#define CPU_MPYHW 35
#define CPU_MUL 36
#define CPU_MULF_S 37
#define CPU_MULU 38
#define CPU_NOT 39
#define CPU_NOTBSU 40
#define CPU_OR 41
#define CPU_ORBSU 42
#define CPU_ORI 43
#define CPU_ORNBSU 44
#define CPU_OUT_B 45
#define CPU_OUT_H 46
#define CPU_OUT_W 47
#define CPU_RETI 48
#define CPU_REV 49
#define CPU_SAR_IMM 50
#define CPU_SAR_REG 51
#define CPU_SCH0BSD 52
#define CPU_SCH0BSU 53
#define CPU_SCH1BSD 54
#define CPU_SCH1BSU 55
#define CPU_SEI 56
#define CPU_SETF 57
#define CPU_SHL_IMM 58
#define CPU_SHL_REG 59
#define CPU_SHR_IMM 60
#define CPU_SHR_REG 61
#define CPU_ST_B 62
#define CPU_ST_H 63
#define CPU_ST_W 64
#define CPU_STSR 65
#define CPU_SUB 66
#define CPU_SUBF_S 67
#define CPU_TRAP 68
#define CPU_TRNC_SW 69
#define CPU_XB 70
#define CPU_XH 71
#define CPU_XOR 72
#define CPU_XORBSU 73
#define CPU_XORI 74
#define CPU_XORNBSU 75
#define CPU_BITSTRING 76
#define CPU_FLOATENDO 77
/* Mapping for opcodes to operation IDs */
static const int8_t CPU_OPCODES[] = {
CPU_MOV_REG, CPU_ADD_REG, CPU_SUB , CPU_CMP_REG ,
CPU_SHL_REG, CPU_SHR_REG, CPU_JMP , CPU_SAR_REG ,
CPU_MUL , CPU_DIV , CPU_MULU , CPU_DIVU ,
CPU_OR , CPU_AND , CPU_XOR , CPU_NOT ,
CPU_MOV_IMM, CPU_ADD_IMM, CPU_SETF , CPU_CMP_IMM ,
CPU_SHL_IMM, CPU_SHR_IMM, CPU_CLI , CPU_SAR_IMM ,
CPU_TRAP , CPU_RETI , CPU_HALT , CPU_ILLEGAL ,
CPU_LDSR , CPU_STSR , CPU_SEI , CPU_BITSTRING,
CPU_BCOND , CPU_BCOND , CPU_BCOND , CPU_BCOND ,
CPU_BCOND , CPU_BCOND , CPU_BCOND , CPU_BCOND ,
CPU_MOVEA , CPU_ADDI , CPU_JR , CPU_JAL ,
CPU_ORI , CPU_ANDI , CPU_XORI , CPU_MOVHI ,
CPU_LD_B , CPU_LD_H , CPU_ILLEGAL , CPU_LD_W ,
CPU_ST_B , CPU_ST_H , CPU_ILLEGAL , CPU_ST_W ,
CPU_IN_B , CPU_IN_H , CPU_CAXI , CPU_IN_W ,
CPU_OUT_B , CPU_OUT_H , CPU_FLOATENDO, CPU_OUT_W
};
/* Mapping for bit string sub-opcodes */
static const int8_t CPU_BITSTRINGS[] = {
CPU_SCH0BSU, CPU_SCH0BSD, CPU_SCH1BSU, CPU_SCH1BSD,
CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL,
CPU_ORBSU , CPU_ANDBSU , CPU_XORBSU , CPU_MOVBSU ,
CPU_ORNBSU , CPU_ANDNBSU, CPU_XORNBSU, CPU_NOTBSU ,
CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL,
CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL,
CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL,
CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL
};
/* Mapping for floating-point/Nintendo sub-opcodes */
static const int8_t CPU_FLOATENDOS[] = {
CPU_CMPF_S , CPU_ILLEGAL, CPU_CVT_WS , CPU_CVT_SW ,
CPU_ADDF_S , CPU_SUBF_S , CPU_MULF_S , CPU_DIVF_S ,
CPU_XB , CPU_XH , CPU_REV , CPU_TRNC_SW,
CPU_MPYHW , CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL,
CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL,
CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL,
CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL,
CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL,
CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL,
CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL,
CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL,
CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL,
CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL,
CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL,
CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL,
CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL
};
/* Instruction sizes by opcode */
static const uint8_t CPU_SIZES[] = {
2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2, 2, 4, 4, 4, 4, 4, 4, 4, 4,
4, 4, 2, 4, 4, 4, 2, 4, 4, 4, 4, 4, 4, 4, 4, 4
};
/***************************** Utility Functions *****************************/
/* Read a data unit from the bus */
static int cpuRead(VB *sim, uint32_t address, int8_t type) {
/* TODO: Determine clock count here */
sim->cpu.access.clocks = 0;
/* Not using a breakpoint callback */
if (sim->onRead == NULL) {
sim->cpu.access.value = busRead(sim, address, type, 0);
return 0;
}
/* Invoke the breakpoint callback */
sim->cpu.access.address = address;
sim->cpu.access.type = type;
return sim->onRead(sim, &sim->cpu.access);
}
/* Read a data unit from the bus for the purpose of an instruction fetch */
static int cpuReadFetch(VB *sim, uint32_t address) {
/* TODO: Determine clock count here */
sim->cpu.access.clocks = 0;
/* Not using a breakpoint callback */
if (sim->onFetch == NULL) {
sim->cpu.access.value = busRead(sim, address, VB_U16, 0);
return 0;
}
/* Invoke the breakpoint callback */
sim->cpu.access.address = address;
sim->cpu.access.type = VB_U16;
return sim->onFetch(sim, sim->cpu.fetch, &sim->cpu.access);
}
/* Write a data unit to the bus */
static int cpuWrite(VB *sim, uint32_t address, int8_t type, int32_t value) {
/* TODO: Determine clock count here */
sim->cpu.access.clocks = 0;
sim->cpu.access.type = type;
/* Using a breakpoint callback */
if (sim->onWrite != NULL) {
sim->cpu.access.address = address;
sim->cpu.access.value = value;
if (sim->onWrite(sim, &sim->cpu.access))
return 1;
}
/* Write the value if the operation wasn't cancelled */
if (sim->cpu.access.type != VB_CANCEL)
busWrite(sim, address, type, value, 0);
return 0;
}
/**************************** Instruction Helpers ****************************/
/* Add two numbers and update the flags */
static int32_t cpuAdd(VB *sim, int32_t left, int32_t right) {
int32_t result = left + right;
sim->cpu.clocks = 1;
sim->cpu.psw.cy = (uint32_t) result < (uint32_t) left;
sim->cpu.psw.ov = (~(left ^ right) & (left ^ result)) >> 31 & 1;
sim->cpu.psw.s = result < 0;
sim->cpu.psw.z = result == 0;
return result;
}
/* Bit string search */
static int cpuBitSearch(VB *sim, int32_t bit, int32_t dir) {
int32_t offset; /* Bit offset in source word */
int32_t value; /* Alias of source word */
/* Read the source word */
if (sim->cpu.busWait == 0) {
/* Initialize state */
sim->cpu.program[30] &= 0xFFFFFFFC;
sim->cpu.program[27] &= 0x0000001F;
sim->cpu.psw.z = 1;
/* The bit string is of zero length */
if (sim->cpu.program[28] == 0) {
sim->cpu.clocks = dir == 1 ? 13 : 15;
return 0;
}
/* Read the data unit from the bus */
if (cpuRead(sim, sim->cpu.program[30], VB_S32))
return 1;
/* Update state */
sim->cpu.busWait = 1;
sim->cpu.clocks = sim->cpu.access.clocks;
/* Wait for the bus access to complete */
if (sim->cpu.clocks > 0)
return 0;
}
/* Update state */
sim->cpu.busWait = 0;
sim->cpu.substring = 0;
/* Search the bit string */
for (
offset = sim->cpu.program[27], value = sim->cpu.access.value;
sim->cpu.program[28] != 0 && (offset & 31) == offset;
offset += dir, sim->cpu.program[28]--, sim->cpu.program[29]++
) {
/* The current bit does not match */
if ((value >> offset & 1) != bit)
continue;
/* The current bit matches */
sim->cpu.program[27] = offset;
sim->cpu.clocks = dir == 1 ? 45 : 50;
sim->cpu.psw.z = 0;
return 0;
}
/* No bit in the current word matches */
sim->cpu.program[27] = offset & 31;
if (sim->cpu.program[27] != offset)
sim->cpu.program[30] += (uint32_t) dir << 2;
if (sim->cpu.program[28] != 0) {
sim->cpu.substring = 1;
sim->cpu.clocks = 5;
} else sim->cpu.clocks = dir == 1 ? 46 : 51;
return 0;
}
/* Bit string bitwise operation */
static int cpuBitString(VB *sim, VB_INSTRUCTION *inst) {
uint64_t bits; /* Shift register */
int32_t dest; /* Destination word value */
int32_t mask; /* Bit mask */
int32_t src; /* Source word value */
/* Initial invocation */
if (sim->cpu.busWait == 0) {
/* Initialize state */
sim->cpu.program[30] &= 0xFFFFFFFC;
sim->cpu.program[29] &= 0xFFFFFFFC;
sim->cpu.program[27] &= 0x0000001F;
sim->cpu.program[26] &= 0x0000001F;
/* The bit string is of zero length */
if (sim->cpu.program[28] == 0) {
sim->cpu.clocks = 20;
return 0;
}
/* Read the data unit from the bus */
if (cpuRead(sim, sim->cpu.program[30], VB_S32))
return 1;
/* Update state */
inst->aux[0] = sim->cpu.access.value;
sim->cpu.busWait = 1;
sim->cpu.clocks = sim->cpu.access.clocks;
/* Wait for the bus access to complete */
if (sim->cpu.clocks > 0)
return 0;
}
/* Read the next source word */
if (sim->cpu.busWait == 1) {
/* Read the data unit from the bus */
if (cpuRead(sim, sim->cpu.program[30] + 4, VB_S32))
return 1;
/* Update state */
inst->aux[1] = sim->cpu.access.value;
sim->cpu.busWait = 2;
sim->cpu.clocks = sim->cpu.access.clocks;
/* Wait for the bus access to complete */
if (sim->cpu.clocks > 0)
return 0;
}
/* Read the destination word */
if (sim->cpu.busWait == 2) {
/* Read the data unit from the bus */
if (cpuRead(sim, sim->cpu.program[29], VB_S32))
return 1;
/* Update state */
sim->cpu.busWait = 3;
sim->cpu.clocks = sim->cpu.access.clocks;
/* Wait for the bus access to complete */
if (sim->cpu.clocks > 0)
return 0;
}
/* Compute and store the destination word */
if (sim->cpu.busWait == 3) {
bits = ((uint64_t) inst->aux[1] << 32 | (uint32_t) inst->aux[0]);
dest = sim->cpu.access.value;
src = sim->cpu.program[27] <= sim->cpu.program[26] ?
bits << (sim->cpu.program[26] - sim->cpu.program[27]) :
bits >> (sim->cpu.program[27] - sim->cpu.program[26])
;
/* Perform the operation */
switch (inst->bits[0] & 7) {
case 0 : dest |= src; break; /* ORBSU */
case 1 : dest &= src; break; /* ANDBSU */
case 2 : dest ^= src; break; /* XORBSU */
case 3 : dest = src; break; /* MOVBSU */
case 4 : dest |= ~src; break; /* ORNBSU */
case 5 : dest &= ~src; break; /* ANDNBSU */
case 6 : dest ^= ~src; break; /* XORNBSU */
default: dest = ~src; break; /* NOTBSU */
}
/* Incorporate only the bits occupied by the bit string */
mask = (uint32_t) 0xFFFFFFFF << sim->cpu.program[26];
if ((uint32_t)sim->cpu.program[28] < (uint32_t)32-sim->cpu.program[26])
mask &= (1 << (sim->cpu.program[28] + sim->cpu.program[26])) - 1;
dest = (dest & mask) | (sim->cpu.access.value & ~mask);
/* Write the data unit to the bus */
if (cpuWrite(sim, sim->cpu.program[29], VB_S32, dest))
return 1;
/* Update state */
sim->cpu.busWait = 4;
sim->cpu.clocks = sim->cpu.access.clocks;
/* Wait for the bus access to complete */
if (sim->cpu.clocks > 0)
return 0;
}
/* Working variables */
mask = 32 - sim->cpu.program[26]; /* Bits processed this invocation */
if ((uint32_t) sim->cpu.program[28] < (uint32_t) mask)
mask = sim->cpu.program[28];
dest = sim->cpu.program[26] + mask; /* New destination bit offset */
src = sim->cpu.program[27] + mask; /* New source bit offset */
/* Update state */
sim->cpu.busWait = 0;
sim->cpu.substring = mask != sim->cpu.program[28];
sim->cpu.program[26] = dest & 31;
sim->cpu.program[27] = src & 31;
sim->cpu.program[28] -= mask;
if (dest >= 32)
sim->cpu.program[29] += 4;
if (src >= 32)
sim->cpu.program[30] += 4;
if (sim->cpu.substring) {
sim->cpu.busWait = 1;
sim->cpu.clocks = 6;
inst->aux[0] = inst->aux[1];
} else {
sim->cpu.busWait = 0;
sim->cpu.clocks = 36;
}
return 0;
}
/* Common processing for most bitwise operations */
static int32_t cpuBitwise(VB *sim, int32_t result) {
sim->cpu.clocks = 1;
sim->cpu.psw.ov = 0;
sim->cpu.psw.s = result < 0;
sim->cpu.psw.z = result == 0;
return result;
}
/* Test a condition code */
static int cpuCondition(VB *sim, int cond) {
/* Falsey condition */
if (cond > 7)
return !cpuCondition(sim, cond & 7);
/* Truthy condition */
switch (cond) {
case 0: return sim->cpu.psw.ov; /* V */
case 1: return sim->cpu.psw.cy; /* L */
case 2: return sim->cpu.psw.z; /* Z */
case 3: return sim->cpu.psw.cy | sim->cpu.psw.z; /* NH */
case 4: return sim->cpu.psw.s; /* N */
case 5: return 1; /* T */
case 6: return sim->cpu.psw.ov ^ sim->cpu.psw.s; /* LT */
default:return(sim->cpu.psw.ov^sim->cpu.psw.s)|sim->cpu.psw.z; /* LE */
}
}
/* Check for a floating-point reserved operand */
static int cpuFloatReserved(VB *sim, int32_t bits) {
uint8_t e = bits >> 23; /* Exponent field */
/* Not reserved */
if (e != 0xFF && (e != 0x00 || (bits & 0x007FFFFF) == 0))
return 0;
/* Reserved */
sim->cpu.causeCode = 0xFF60;
sim->cpu.psw.fro = 1;
return 1;
}
/* Convert a 32-bit integer to the represented floating-point value */
static double cpuFloatOperand(VB *sim, int32_t bits) {
return cpuFloatReserved(sim, bits) ? 0 : (double) *(float *) &bits;
}
/* Convert a floating-point result to bits as a 32-bit integer */
static int32_t cpuFloatResult(VB *sim, double resultd) {
float resultf; /* 32-bit conversion of result */
int32_t ret; /* Output value */
/* Overflow */
if (resultd < -FLT_MAX || resultd > FLT_MAX) {
sim->cpu.causeCode = 0xFF64;
sim->cpu.psw.fov = 1;
return 0;
}
/* Underflow */
if (resultd > -FLT_MIN && resultd < FLT_MIN) {
sim->cpu.psw.fud = 1;
ret = 0;
}
/* Normalized */
else {
resultf = (float) resultd;
ret = *(int32_t *) &resultf;
if (ret == INT32_MIN)
ret = 0; /* Prevent negative zero */
/* Precision degradation */
if (resultf != resultd)
sim->cpu.psw.fpr = 1;
}
/* Update state */
sim->cpu.psw.cy = ret < 0;
sim->cpu.psw.ov = 0;
sim->cpu.psw.s = ret < 0;
sim->cpu.psw.z = ret == 0;
return ret;
}
/* Convert a floating-point value to a word value */
static void cpuFloatToWord(VB *sim, VB_INSTRUCTION *inst, int truncate) {
int32_t bits = sim->cpu.program[inst->bits[0] & 0x1F];
int32_t result; /* Output value */
int32_t x; /* Working variable */
int32_t y; /* Working variable */
/* Zero */
if ((bits & 0x7FFFFFFF) == 0)
result = 0;
/* Minimum value */
else if (bits == (int32_t) 0xCF000000)
result = INT32_MIN;
/* Conversion */
else {
x = bits >> 23 & 0xFF; /* Exponent field */
/* Reserved operand */
if (x == 0xFF || x == 0x00) {
sim->cpu.causeCode = 0xFF60;
sim->cpu.psw.fro = 1;
return;
}
/* Invalid operation */
if (x >= 158) {
sim->cpu.causeCode = 0xFF70;
sim->cpu.psw.fiv = 1;
return;
}
/* Parse significand bits */
result = (bits & 0x007FFFFF) | 0x00800000;
/* Left shift */
if (x >= 150)
result <<= x - 150;
/* Right shift */
else {
y = result; /* Significant bits */
x = 150 - x; /* Number of bits to shift */
result >>= x; /* Update state */
/* Precision degradation */
if ((y & ((1 << x) - 1)) != 0) {
sim->cpu.psw.fpr = 1;
/* Apply rounding */
if (!truncate)
result += y >> (x - 1) & 1;
}
}
/* Incorporate sign */
if (bits < 0)
result = -result;
}
/* Update state */
sim->cpu.program[inst->bits[0] >> 5 & 0x1F] = result;
sim->cpu.psw.ov = 0;
sim->cpu.psw.s = result < 0;
sim->cpu.psw.z = result == 0;
sim->cpu.clocks = 14;
}
/* Perform a jump */
static void cpuJump(VB *sim, VB_INSTRUCTION *inst, uint32_t address) {
sim->cpu.pc = address & 0xFFFFFFFE;
sim->cpu.clocks = 3;
inst->size = 0;
}
/* Perform an input or load */
static int cpuLoad(VB *sim,VB_INSTRUCTION *inst,uint8_t type,uint32_t clocks) {
/* Initiate the read */
if (sim->cpu.busWait == 0) {
/* Read the data unit from the bus */
if (cpuRead(
sim,
sim->cpu.program[inst->bits[0] & 0x1F] +
SignExtend((int32_t) inst->bits[1], 16),
type
)) return 1;
/* Update state */
sim->cpu.busWait = 1;
sim->cpu.clocks = sim->cpu.access.clocks;
/* Wait for the bus access to complete */
if (sim->cpu.clocks > 0)
return 0;
}
/* Complete the read */
sim->cpu.busWait = 0;
sim->cpu.clocks = clocks;
sim->cpu.program[inst->bits[0] >> 5 & 0x1F] = sim->cpu.access.value;
return 0;
}
/* Specify a new value for a system register */
static uint32_t cpuSetSystemRegister(VB *sim,int id,uint32_t value,int debug) {
switch (id) {
case VB_ADTRE: return sim->cpu.adtre = value & 0xFFFFFFFE;
case VB_EIPC : return sim->cpu.eipc = value & 0xFFFFFFFE;
case VB_EIPSW: return sim->cpu.eipsw = value & 0x000FF3FF;
case VB_FEPC : return sim->cpu.fepc = value & 0xFFFFFFFE;
case VB_FEPSW: return sim->cpu.fepsw = value & 0x000FF3FF;
case VB_PIR : return 0x00005346;
case VB_TKCW : return 0x000000E0;
case 29 : return sim->cpu.sr29 = value & 0x00000001;
case 30 : return 0x00000004;
case 31 :
if (!debug && (int32_t) value < 0)
value = ~value + 1;
return sim->cpu.sr31 = value;
case VB_CHCW :
sim->cpu.chcw.ice = value >> 1 & 1;
/* TODO: Perform dump/restore operations */
return value & 0x00000002;
case VB_ECR :
if (debug) {
sim->cpu.ecr.fecc = value >> 16;
sim->cpu.ecr.eicc = value;
return value;
}
return vbGetSystemRegister(sim, id);
case VB_PSW :
sim->cpu.psw.i = value >> 16 & 15;
sim->cpu.psw.np = value >> 15 & 1;
sim->cpu.psw.ep = value >> 14 & 1;
sim->cpu.psw.ae = value >> 13 & 1;
sim->cpu.psw.id = value >> 12 & 1;
sim->cpu.psw.fro = value >> 9 & 1;
sim->cpu.psw.fiv = value >> 8 & 1;
sim->cpu.psw.fzd = value >> 7 & 1;
sim->cpu.psw.fov = value >> 6 & 1;
sim->cpu.psw.fud = value >> 5 & 1;
sim->cpu.psw.fpr = value >> 4 & 1;
sim->cpu.psw.cy = value >> 3 & 1;
sim->cpu.psw.ov = value >> 2 & 1;
sim->cpu.psw.s = value >> 1 & 1;
sim->cpu.psw.z = value & 1;
return value & 0x000FF3FF;
}
return 0;
}
/* Perform a right shift */
static int cpuShiftRight(VB *sim, int32_t value, int bits, int arithmetic) {
if (bits != 0) {
sim->cpu.psw.cy = (value >> (bits - 1)) & 1;
value = value >> bits & (((uint32_t) 1 << (32 - bits)) - 1);
if (arithmetic)
value = SignExtend(value, 32 - bits);
} else sim->cpu.psw.cy = 0;
return cpuBitwise(sim, value);
}
/* Perform an output or store */
static int cpuStore(VB *sim,VB_INSTRUCTION *inst,uint8_t type,uint32_t clocks){
/* Initiate the write */
if (sim->cpu.busWait == 0) {
/* Read the data unit from the bus */
if (cpuWrite(
sim,
sim->cpu.program[inst->bits[0] & 0x1F] +
SignExtend((int32_t) inst->bits[1], 16),
type,
sim->cpu.program[inst->bits[0] >> 5 & 0x1F]
)) return 1;
/* Update state */
sim->cpu.busWait = 1;
sim->cpu.clocks = sim->cpu.access.clocks;
/* Wait for the bus access to complete */
if (sim->cpu.clocks > 0)
return 0;
}
/* Complete the write */
sim->cpu.busWait = 0;
sim->cpu.clocks = clocks;
return 0;
}
/* Subtract two numbers and update the flags */
static int32_t cpuSubtract(VB *sim, int32_t left, int32_t right) {
int32_t result = left - right;
sim->cpu.clocks = 1;
sim->cpu.psw.cy = (uint32_t) result > (uint32_t) left;
sim->cpu.psw.ov = ((left ^ right) & (left ^ result)) >> 31 & 1;
sim->cpu.psw.s = result < 0;
sim->cpu.psw.z = result == 0;
return result;
}
/************************ Instruction Implementations ************************/
/* Add Immediate */
static void cpuADD_IMM(VB *sim, VB_INSTRUCTION *inst) {
int32_t *reg2 = &sim->cpu.program[inst->bits[0] >> 5 & 0x1F];
int32_t right = inst->bits[0] & 0x1F;
*reg2 = cpuAdd(sim, *reg2, SignExtend(right, 5));
}
/* Add Register */
static void cpuADD_REG(VB *sim, VB_INSTRUCTION *inst) {
int32_t *reg2 = &sim->cpu.program[inst->bits[0] >> 5 & 0x1F];
*reg2 = cpuAdd(sim, *reg2, sim->cpu.program[inst->bits[0] & 0x1F]);
}
/* Add Floating Short */
static void cpuADDF_S(VB *sim, VB_INSTRUCTION *inst) {
int32_t *reg2 = &sim->cpu.program[inst->bits[0] >> 5 & 0x1F];
double left = cpuFloatOperand(sim, *reg2);
double right = cpuFloatOperand(sim,sim->cpu.program[inst->bits[0]&0x1F]);
int32_t result; /* Output bits */
/* Perform the operation */
if (sim->cpu.causeCode == 0)
result = cpuFloatResult(sim, left + right);
if (sim->cpu.causeCode != 0)
return;
/* Update state */
*reg2 = result;
sim->cpu.clocks = 28;
}
/* Add Immediate */
static void cpuADDI(VB *sim, VB_INSTRUCTION *inst) {
int32_t right = inst->bits[1];
sim->cpu.program[inst->bits[0] >> 5 & 0x1F] = cpuAdd(sim,
sim->cpu.program[inst->bits[0] & 0x1F], SignExtend(right, 16));
}
/* And */
static void cpuAND(VB *sim, VB_INSTRUCTION *inst) {
int32_t *reg2 = &sim->cpu.program[inst->bits[0] >> 5 & 0x1F];
*reg2 = cpuBitwise(sim, *reg2 & sim->cpu.program[inst->bits[0] & 0x1F]);
}
/* And Bit String Upward */
#define cpuANDBSU(sim, inst) cpuBitString(sim, inst)
/* And Immediate */
static void cpuANDI(VB *sim, VB_INSTRUCTION *inst) {
sim->cpu.program[inst->bits[0] >> 5 & 0x1F] = cpuBitwise(sim,
sim->cpu.program[inst->bits[0] & 0x1F] & inst->bits[1]);
}
/* And Not Bit String Upward */
#define cpuANDNBSU(sim, inst) cpuBitString(sim, inst)
/* Conditional Branch */
static void cpuBCOND(VB *sim, VB_INSTRUCTION *inst) {
int32_t disp; /* Target address displacement */
/* Branch to the target address */
if (cpuCondition(sim, inst->bits[0] >> 9 & 15)) {
disp = inst->bits[0] & 0x1FF;
cpuJump(sim, inst, sim->cpu.pc + SignExtend(disp, 9));
}
/* Do not branch */
else sim->cpu.clocks = 1;
}
/* Compare And Exchahge Interlocked */
static int cpuCAXI(VB *sim, VB_INSTRUCTION *inst) {
int32_t *reg2; /* Program register reg2 */
/* Read the lock word */
if (sim->cpu.busWait == 0) {
/* Compute the address of the lock word */
inst->aux[0] = sim->cpu.program[inst->bits[0] & 0x1F] +
SignExtend((int32_t) inst->bits[1], 16);
/* Read the data unit from the bus */
if (cpuRead(sim, inst->aux[0], VB_S32))
return 1;
/* Update state */
sim->cpu.busWait = 1;
sim->cpu.clocks = sim->cpu.access.clocks;
/* Wait for the bus access to complete */
if (sim->cpu.clocks > 0)
return 0;
}
/* Compare and exchange */
if (sim->cpu.busWait == 1) {
/* Process the lock word */
reg2 = &sim->cpu.program[inst->bits[0] >> 5 & 0x1F];
cpuSubtract(sim, *reg2, sim->cpu.access.value);
*reg2 = sim->cpu.access.value;
/* Store the exchange value to the bus */
if (cpuWrite(sim, inst->aux[0], VB_S32,
sim->cpu.psw.z ? sim->cpu.program[30] : sim->cpu.access.value))
return 1;
/* Update state */
sim->cpu.clocks = sim->cpu.access.clocks;
sim->cpu.busWait = 2;
/* Wait for the bus access to complete */
if (sim->cpu.clocks > 0)
return 0;
}
/* Update state */
sim->cpu.busWait = 0;
sim->cpu.clocks = 26;
return 0;
}
/* Clear Interrupt Disable Flag */
static void cpuCLI(VB *sim) {
sim->cpu.psw.id = 0;
sim->cpu.clocks = 12;
}
/* Compare Immediate */
static void cpuCMP_IMM(VB *sim, VB_INSTRUCTION *inst) {
int32_t right = inst->bits[0] & 0x1F;
cpuSubtract(sim, sim->cpu.program[inst->bits[0] >> 5 & 0x1F],
SignExtend(right, 5));
}
/* Compare Register */
static void cpuCMP_REG(VB *sim, VB_INSTRUCTION *inst) {
cpuSubtract(sim, sim->cpu.program[inst->bits[0] >> 5 & 0x1F],
sim->cpu.program[inst->bits[0] & 0x1F]);
}
/* Compare Floating Short */
static void cpuCMPF_S(VB *sim, VB_INSTRUCTION *inst) {
double left =cpuFloatOperand(sim,sim->cpu.program[inst->bits[0]>>5&0x1F]);
double right=cpuFloatOperand(sim,sim->cpu.program[inst->bits[0] &0x1F]);
/* Perform the operation */
if (sim->cpu.causeCode == 0)
cpuFloatResult(sim, left - right);
if (sim->cpu.causeCode != 0)
return;
/* Update state */
sim->cpu.clocks = 10;
}
/* Convert Short Floating to Word Integer */
#define cpuCVT_SW(sim, inst) cpuFloatToWord(sim, inst, 0)
/* Convert Word Integer to Short Floating */
static void cpuCVT_WS(VB *sim, VB_INSTRUCTION *inst) {
int32_t value = sim->cpu.program[inst->bits[0] & 0x1F];
float result = (float) value;
sim->cpu.program[inst->bits[0] >> 5 & 0x1F] = *(int32_t *) &result;
if (result != value)
sim->cpu.psw.fpr = 1;
sim->cpu.psw.cy = result < 0;
sim->cpu.psw.ov = 0;
sim->cpu.psw.s = result < 0;
sim->cpu.psw.z = result == 0;
sim->cpu.clocks = 16;
}
/* Divide */
static void cpuDIV(VB *sim, VB_INSTRUCTION *inst) {
int32_t right = sim->cpu.program[inst->bits[0] & 0x1F];
int32_t *r30; /* Program register r30 */
int32_t *reg2; /* Program register reg2 */
/* Zero division */
if (right == 0) {
sim->cpu.causeCode = 0xFF80;
return;
}
/* Special case */
reg2 = &sim->cpu.program[inst->bits[0] >> 5 & 0x1F];
if (*reg2 == INT32_MIN && right == -1) {
sim->cpu.program[30] = 0;
sim->cpu.psw.ov = 1;
}
/* Perform the operation */
else {
r30 = &sim->cpu.program[30];
*r30 = *reg2 % right;
if ((*r30 ^ *reg2) < 0)
*r30 = -*r30;
*reg2 /= right;
sim->cpu.psw.ov = 0;
}
/* Update state */
sim->cpu.psw.s = *reg2 < 0;
sim->cpu.psw.z = *reg2 == 0;
sim->cpu.clocks = 38;
}
/* Divide Floating Short */
static void cpuDIVF_S(VB *sim, VB_INSTRUCTION *inst) {
int32_t *reg2 = &sim->cpu.program[inst->bits[0] >> 5 & 0x1F];
double left = cpuFloatOperand(sim, *reg2);
double right = cpuFloatOperand(sim,sim->cpu.program[inst->bits[0]&0x1F]);
int32_t result; /* Output bits */
/* Reserved operand */
if (sim->cpu.causeCode != 0)
return;
/* Zero division */
if (right == 0) {
/* Invalid operation */
if (left == 0) {
sim->cpu.causeCode = 0xFF70;
sim->cpu.psw.fiv = 1;
}
/* Zero division */
else {
sim->cpu.causeCode = 0xFF68;
sim->cpu.psw.fzd = 1;
}
return;
}
/* Perform the operation */
result = cpuFloatResult(sim, left / right);
if (sim->cpu.causeCode != 0)
return;
/* Update state */
*reg2 = result;
sim->cpu.clocks = 44;
}
/* Divide Unsigned */
static void cpuDIVU(VB *sim, VB_INSTRUCTION *inst) {
uint32_t right = sim->cpu.program[inst->bits[0] & 0x1F];
uint32_t *reg2; /* Program register reg2 */
/* Zero division */
if (right == 0) {
sim->cpu.causeCode = 0xFF80;
return;
}
/* Perform the operation */
reg2 = (uint32_t *) &sim->cpu.program[inst->bits[0] >> 5 & 0x1F];
sim->cpu.program[30] = *reg2 % right;
*reg2 /= right;
/* Update state */
sim->cpu.psw.ov = 0;
sim->cpu.psw.s = *reg2 >> 31 & 1;
sim->cpu.psw.z = *reg2 == 0;
sim->cpu.clocks = 36;
}
/* Halt */
static void cpuHALT(VB *sim) {
sim->cpu.state = CPU_HALTED;
/* sim->cpu.clocks = ? */
}
/* Input Byte */
#define cpuIN_B(sim, inst) cpuLoad(sim, inst, VB_U8, 5)
/* Input Halfword */
#define cpuIN_H(sim, inst) cpuLoad(sim, inst, VB_U16, 5)
/* Input Word */
#define cpuIN_W(sim, inst) cpuLoad(sim, inst, VB_S32, 5)
/* Jump and Link */
static void cpuJAL(VB *sim, VB_INSTRUCTION *inst) {
int32_t disp = ((int32_t) inst->bits[0]<<16 | inst->bits[1]) & 0x03FFFFFF;
sim->cpu.program[31] = sim->cpu.pc + 4;
cpuJump(sim, inst, sim->cpu.pc + SignExtend(disp, 26));
}
/* Jump Register */
#define cpuJMP(sim,inst) cpuJump(sim,inst,sim->cpu.program[inst->bits[0]&0x1F])
/* Jump Relative */
static void cpuJR(VB *sim, VB_INSTRUCTION *inst) {
int32_t disp = ((int32_t) inst->bits[0]<<16 | inst->bits[1]) & 0x03FFFFFF;
cpuJump(sim, inst, sim->cpu.pc + SignExtend(disp, 26));
}
/* Load Byte */
#define cpuLD_B(sim, inst) cpuLoad(sim, inst, VB_S8, 5)
/* Load Halfword */
#define cpuLD_H(sim, inst) cpuLoad(sim, inst, VB_S16, 5)
/* Load Word */
#define cpuLD_W(sim, inst) cpuLoad(sim, inst, VB_S32, 5)
/* Load to System Register */
static void cpuLDSR(VB *sim, VB_INSTRUCTION *inst) {
cpuSetSystemRegister(sim, inst->bits[0] & 0x1F,
sim->cpu.program[inst->bits[0] >> 5 & 0x1F], 0);
sim->cpu.clocks = 8;
}
/* Move Immediate */
static void cpuMOV_IMM(VB *sim, VB_INSTRUCTION *inst) {
int32_t value = inst->bits[0] & 0x1F;
sim->cpu.program[inst->bits[0] >> 5 & 0x1F] = SignExtend(value, 5);
sim->cpu.clocks = 1;
}
/* Move Register */
static void cpuMOV_REG(VB *sim, VB_INSTRUCTION *inst) {
sim->cpu.program[inst->bits[0] >> 5 & 0x1F] =
sim->cpu.program[inst->bits[0] & 0x1F];
sim->cpu.clocks = 1;
}
/* Move Bit String Upward */
#define cpuMOVBSU(sim, inst) cpuBitString(sim, inst)
/* Add */
static void cpuMOVEA(VB *sim, VB_INSTRUCTION *inst) {
int32_t right = inst->bits[1];
sim->cpu.program[inst->bits[0] >> 5 & 0x1F] =
sim->cpu.program[inst->bits[0] & 0x1F] + SignExtend(right, 16);
sim->cpu.clocks = 1;
}
/* Add */
static void cpuMOVHI(VB *sim, VB_INSTRUCTION *inst) {
sim->cpu.program[inst->bits[0] >> 5 & 0x1F] =
sim->cpu.program[inst->bits[0] & 0x1F] + ((int32_t)inst->bits[1]<<16);
sim->cpu.clocks = 1;
}
/* Multiply Halfword */
static void cpuMPYHW(VB *sim, VB_INSTRUCTION *inst) {
int32_t right = sim->cpu.program[inst->bits[0] & 0x1F] & 0x0001FFFF;
sim->cpu.program[inst->bits[0] >> 5 & 0x1F] *= SignExtend(right, 17);
sim->cpu.clocks = 9;
}
/* Multiply */
static void cpuMUL(VB *sim, VB_INSTRUCTION *inst) {
int32_t *reg2 = &sim->cpu.program[inst->bits[0] >> 5 & 0x1F];
int64_t result = (int64_t) *reg2 *
sim->cpu.program[inst->bits[0] & 0x1F];
sim->cpu.program[30] = result >> 32;
*reg2 = result;
sim->cpu.psw.ov = *reg2 != result;
sim->cpu.psw.s = *reg2 < 0;
sim->cpu.psw.z = *reg2 == 0;
sim->cpu.clocks = 13;
}
/* Multiply Floating Short */
static void cpuMULF_S(VB *sim, VB_INSTRUCTION *inst) {
int32_t *reg2 = &sim->cpu.program[inst->bits[0] >> 5 & 0x1F];
double left = cpuFloatOperand(sim, *reg2);
double right = cpuFloatOperand(sim,sim->cpu.program[inst->bits[0]&0x1F]);
int32_t result; /* Output bits */
/* Perform the operation */
if (sim->cpu.causeCode == 0)
result = cpuFloatResult(sim, left * right);
if (sim->cpu.causeCode != 0)
return;
/* Update state */
*reg2 = result;
sim->cpu.clocks = 30;
}
/* Multiply Unsigned */
static void cpuMULU(VB *sim, VB_INSTRUCTION *inst) {
uint32_t *reg2 = (uint32_t *) &sim->cpu.program[inst->bits[0]>>5&0x1F];
uint64_t result = (uint64_t) *reg2 *
(uint32_t) sim->cpu.program[inst->bits[0] & 0x1F];
sim->cpu.program[30] = result >> 32;
*reg2 = result;
sim->cpu.psw.ov = *reg2 != result;
sim->cpu.psw.s = *reg2 >> 31 & 1;
sim->cpu.psw.z = *reg2 == 0;
sim->cpu.clocks = 13;
}
/* Not */
static void cpuNOT(VB *sim, VB_INSTRUCTION *inst) {
sim->cpu.program[inst->bits[0] >> 5 & 0x1F] =
cpuBitwise(sim, ~sim->cpu.program[inst->bits[0] & 0x1F]);
}
/* Not Bit String Upward */
#define cpuNOTBSU(sim, inst) cpuBitString(sim, inst)
/* Or */
static void cpuOR(VB *sim, VB_INSTRUCTION *inst) {
int32_t *reg2 = &sim->cpu.program[inst->bits[0] >> 5 & 0x1F];
*reg2 = cpuBitwise(sim, *reg2 | sim->cpu.program[inst->bits[0] & 0x1F]);
}
/* Or Bit String Upward */
#define cpuORBSU(sim, inst) cpuBitString(sim, inst)
/* Or Immediate */
static void cpuORI(VB *sim, VB_INSTRUCTION *inst) {
sim->cpu.program[inst->bits[0] >> 5 & 0x1F] = cpuBitwise(sim,
sim->cpu.program[inst->bits[0] & 0x1F] | inst->bits[1]);
}
/* Or Not Bit String Upward */
#define cpuORNBSU(sim, inst) cpuBitString(sim, inst)
/* Output Byte */
#define cpuOUT_B(sim, inst) cpuStore(sim, inst, VB_U8, 4)
/* Output Halfword */
#define cpuOUT_H(sim, inst) cpuStore(sim, inst, VB_U16, 4)
/* Output Word */
#define cpuOUT_W(sim, inst) cpuStore(sim, inst, VB_S32, 4)
/* Return from Trap or Interrupt */
static void cpuRETI(VB *sim, VB_INSTRUCTION *inst) {
/* Duplexed exception */
if (sim->cpu.psw.np) {
sim->cpu.pc = sim->cpu.fepc;
cpuSetSystemRegister(sim, VB_PSW, sim->cpu.fepsw, 0);
}
/* Non-duplexed exception */
else {
sim->cpu.pc = sim->cpu.eipc;
cpuSetSystemRegister(sim, VB_PSW, sim->cpu.eipsw, 0);
}
/* Update state */
sim->cpu.clocks = 10;
inst->size = 0;
}
/* Reverse Bits in Word */
static void cpuREV(VB *sim, VB_INSTRUCTION *inst) {
int32_t value = sim->cpu.program[inst->bits[0] & 0x1F];
value = (value >> 16 & 0x0000FFFF) | (value << 16 & (int32_t) 0xFFFF0000);
value = (value >> 8 & 0x00FF00FF) | (value << 8 & (int32_t) 0xFF00FF00);
value = (value >> 4 & 0x0F0F0F0F) | (value << 4 & (int32_t) 0xF0F0F0F0);
value = (value >> 2 & 0x33333333) | (value << 2 & (int32_t) 0xCCCCCCCC);
sim->cpu.program[inst->bits[0] >> 5 & 0x1F] =
(value >> 1 & 0x55555555) | (value << 1 & (int32_t) 0xAAAAAAAA);
sim->cpu.clocks = 22;
}
/* Shift Arithmetic Right by Immediate */
static void cpuSAR_IMM(VB *sim, VB_INSTRUCTION *inst) {
int32_t *reg2 = &sim->cpu.program[inst->bits[0] >> 5 & 0x1F];
*reg2 = cpuShiftRight(sim, *reg2, inst->bits[0] & 0x1F, 1);
}
/* Shift Arithmetic Right by Register */
static void cpuSAR_REG(VB *sim, VB_INSTRUCTION *inst) {
int32_t *reg2 = &sim->cpu.program[inst->bits[0] >> 5 & 0x1F];
*reg2 = cpuShiftRight(sim, *reg2,
sim->cpu.program[inst->bits[0] & 0x1F] & 0x1F, 1);
}
/* Search Bit 0 Downward */
#define cpuSCH0BSD(sim) cpuBitSearch(sim, 0, -1)
/* Search Bit 0 Upward */
#define cpuSCH0BSU(sim) cpuBitSearch(sim, 0, 1)
/* Search Bit 1 Downward */
#define cpuSCH1BSD(sim) cpuBitSearch(sim, 1, -1)
/* Search Bit 1 Upward */
#define cpuSCH1BSU(sim) cpuBitSearch(sim, 1, 1)
/* Set Interrupt Disable Flag */
static void cpuSEI(VB *sim) {
sim->cpu.psw.id = 1;
sim->cpu.clocks = 12;
}
/* Set Flag Condition */
static void cpuSETF(VB *sim, VB_INSTRUCTION *inst) {
sim->cpu.program[inst->bits[0] >> 5 & 0x1F] =
cpuCondition(sim, inst->bits[0] & 15);
sim->cpu.clocks = 1;
}
/* Shift Logical Left by Immediate */
static void cpuSHL_IMM(VB *sim, VB_INSTRUCTION *inst) {
int32_t *reg2 = &sim->cpu.program[inst->bits[0] >> 5 & 0x1F];
int32_t bits = inst->bits[0] & 0x1F;
sim->cpu.psw.cy = bits == 0 ? 0 : *reg2 >> (32 - bits) & 1;
*reg2 = cpuBitwise(sim, *reg2 << bits);
}
/* Shift Logical Left by Register */
static void cpuSHL_REG(VB *sim, VB_INSTRUCTION *inst) {
int32_t *reg2 = &sim->cpu.program[inst->bits[0] >> 5 & 0x1F];
int32_t bits = sim->cpu.program[inst->bits[0] & 0x1F] & 0x1F;
sim->cpu.psw.cy = bits == 0 ? 0 : *reg2 >> (32 - bits) & 1;
*reg2 = cpuBitwise(sim, *reg2 << bits);
}
/* Shift Logical Right by Immediate */
static void cpuSHR_IMM(VB *sim, VB_INSTRUCTION *inst) {
int32_t *reg2 = &sim->cpu.program[inst->bits[0] >> 5 & 0x1F];
*reg2 = cpuShiftRight(sim, *reg2, inst->bits[0] & 0x1F, 0);
}
/* Shift Logical Right by Register */
static void cpuSHR_REG(VB *sim, VB_INSTRUCTION *inst) {
int32_t *reg2 = &sim->cpu.program[inst->bits[0] >> 5 & 0x1F];
*reg2 = cpuShiftRight(sim, *reg2,
sim->cpu.program[inst->bits[0] & 0x1F] & 0x1F, 0);
}
/* Store Byte */
#define cpuST_B(sim, inst) cpuStore(sim, inst, VB_S8, 4)
/* Store Halfword */
#define cpuST_H(sim, inst) cpuStore(sim, inst, VB_S16, 4)
/* Store Word */
#define cpuST_W(sim, inst) cpuStore(sim, inst, VB_S32, 4)
/* Store Contents of System Register */
static void cpuSTSR(VB *sim, VB_INSTRUCTION *inst) {
sim->cpu.program[inst->bits[0] >> 5 & 0x1F] =
vbGetSystemRegister(sim, inst->bits[0] & 0x1F);
sim->cpu.clocks = 8;
}
/* Subtract */
static void cpuSUB(VB *sim, VB_INSTRUCTION *inst) {
int32_t *reg2 = &sim->cpu.program[inst->bits[0] >> 5 & 0x1F];
*reg2 = cpuSubtract(sim, *reg2, sim->cpu.program[inst->bits[0] & 0x1F]);
}
/* Subtract Floating Short */
static void cpuSUBF_S(VB *sim, VB_INSTRUCTION *inst) {
int32_t *reg2 = &sim->cpu.program[inst->bits[0] >> 5 & 0x1F];
double left = cpuFloatOperand(sim, *reg2);
double right = cpuFloatOperand(sim,sim->cpu.program[inst->bits[0]&0x1F]);
int32_t result; /* Output bits */
/* Perform the operation */
if (sim->cpu.causeCode == 0)
result = cpuFloatResult(sim, left - right);
if (sim->cpu.causeCode != 0)
return;
/* Update state */
*reg2 = result;
sim->cpu.clocks = 28;
}
/* Trap */
static void cpuTRAP(VB *sim, VB_INSTRUCTION *inst) {
sim->cpu.causeCode = 0xFFA0 + (inst->bits[0] & 0x1F);
sim->cpu.clocks = 15;
sim->cpu.pc += 2;
}
/* Truncate Short Floating to Word Integer */
#define cpuTRNC_SW(sim, inst) cpuFloatToWord(sim, inst, 1)
/* Exchange Byte */
static void cpuXB(VB *sim, VB_INSTRUCTION *inst) {
int32_t *reg2 = &sim->cpu.program[inst->bits[0] >> 5 & 0x1F];
*reg2 =
(*reg2 >> 8 & (int32_t) 0x000000FF) |
(*reg2 << 8 & (int32_t) 0x0000FF00) |
(*reg2 & (int32_t) 0xFFFF0000)
;
sim->cpu.clocks = 6;
}
/* Exchange Halfword */
static void cpuXH(VB *sim, VB_INSTRUCTION *inst) {
int32_t *reg2 = &sim->cpu.program[inst->bits[0] >> 5 & 0x1F];
*reg2 = (*reg2 >> 16 & 0x0000FFFF) | *reg2 << 16;
sim->cpu.clocks = 1;
}
/* Exclusive Or */
static void cpuXOR(VB *sim, VB_INSTRUCTION *inst) {
int32_t *reg2 = &sim->cpu.program[inst->bits[0] >> 5 & 0x1F];
*reg2 = cpuBitwise(sim, *reg2 ^ sim->cpu.program[inst->bits[0] & 0x1F]);
}
/* Exclusive Or Bit String Upward */
#define cpuXORBSU(sim, inst) cpuBitString(sim, inst)
/* Exclusive Or Immediate */
static void cpuXORI(VB *sim, VB_INSTRUCTION *inst) {
sim->cpu.program[inst->bits[0] >> 5 & 0x1F] = cpuBitwise(sim,
sim->cpu.program[inst->bits[0] & 0x1F] ^ inst->bits[1]);
}
/* Exclusive Or Not Bit String Upward */
#define cpuXORNBSU(sim, inst) cpuBitString(sim, inst)
/***************************** Module Functions ******************************/
/* Check for interrupts */
static int cpuCheckIRQs(VB *sim) {
int x; /* Iterator */
/* Interrupts are masked */
if (sim->cpu.psw.np || sim->cpu.psw.ep || sim->cpu.psw.id)
return 0;
/* Check for interrupts */
for (x = 4; x >= sim->cpu.psw.i; x--) {
/* The interrupt request line is low */
if (!sim->cpu.irq[x])
continue;
/* Cause a pending HALT instruction to complete */
if (sim->cpu.state == CPU_HALTED)
sim->cpu.pc += 2;
/* Trigger an interrupt */
sim->cpu.causeCode = 0xFE00 | x << 4;
sim->cpu.state = CPU_EXCEPTION;
return 1;
}
/* No interrupt */
return 0;
}
/* Perform instruction execute operations */
static int cpuExecute(VB *sim) {
int broke; /* Application break occurred */
VB_INSTRUCTION *inst; /* Shorthand reference */
/* Check for address trap */
if (sim->cpu.psw.ae && sim->cpu.adtre == sim->cpu.pc) {
sim->cpu.causeCode = 0xFFC0;
sim->cpu.state = CPU_EXCEPTION;
return 0;
}
/* Prepare state */
sim->cpu.causeCode = 0;
inst = &sim->cpu.inst;
/* Check for application break */
if (sim->onExecute != NULL && sim->onExecute(sim, inst))
return 1;
/* Processing by ID */
broke = 0;
switch (inst->id) {
case CPU_ADD_IMM: cpuADD_IMM(sim, inst); break;
case CPU_ADD_REG: cpuADD_REG(sim, inst); break;
case CPU_ADDF_S : cpuADDF_S (sim, inst); break;
case CPU_ADDI : cpuADDI (sim, inst); break;
case CPU_AND : cpuAND (sim, inst); break;
case CPU_ANDBSU : broke = cpuANDBSU (sim, inst); break;
case CPU_ANDI : cpuANDI (sim, inst); break;
case CPU_ANDNBSU: broke = cpuANDNBSU(sim, inst); break;
case CPU_BCOND : cpuBCOND (sim, inst); break;
case CPU_CAXI : broke = cpuCAXI (sim, inst); break;
case CPU_CLI : cpuCLI (sim ); break;
case CPU_CMP_IMM: cpuCMP_IMM(sim, inst); break;
case CPU_CMP_REG: cpuCMP_REG(sim, inst); break;
case CPU_CMPF_S : cpuCMPF_S (sim, inst); break;
case CPU_CVT_SW : cpuCVT_SW (sim, inst); break;
case CPU_CVT_WS : cpuCVT_WS (sim, inst); break;
case CPU_DIV : cpuDIV (sim, inst); break;
case CPU_DIVF_S : cpuDIVF_S (sim, inst); break;
case CPU_DIVU : cpuDIVU (sim, inst); break;
case CPU_HALT : cpuHALT (sim ); break;
case CPU_IN_B : broke = cpuIN_B (sim, inst); break;
case CPU_IN_H : broke = cpuIN_H (sim, inst); break;
case CPU_IN_W : broke = cpuIN_W (sim, inst); break;
case CPU_JAL : cpuJAL (sim, inst); break;
case CPU_JMP : cpuJMP (sim, inst); break;
case CPU_JR : cpuJR (sim, inst); break;
case CPU_LD_B : broke = cpuLD_B (sim, inst); break;
case CPU_LD_H : broke = cpuLD_H (sim, inst); break;
case CPU_LD_W : broke = cpuLD_W (sim, inst); break;
case CPU_LDSR : cpuLDSR (sim, inst); break;
case CPU_MOV_IMM: cpuMOV_IMM(sim, inst); break;
case CPU_MOV_REG: cpuMOV_REG(sim, inst); break;
case CPU_MOVBSU : broke = cpuMOVBSU (sim, inst); break;
case CPU_MOVEA : cpuMOVEA (sim, inst); break;
case CPU_MOVHI : cpuMOVHI (sim, inst); break;
case CPU_MPYHW : cpuMPYHW (sim, inst); break;
case CPU_MUL : cpuMUL (sim, inst); break;
case CPU_MULF_S : cpuMULF_S (sim, inst); break;
case CPU_MULU : cpuMULU (sim, inst); break;
case CPU_NOT : cpuNOT (sim, inst); break;
case CPU_NOTBSU : broke = cpuNOTBSU (sim, inst); break;
case CPU_OR : cpuOR (sim, inst); break;
case CPU_ORBSU : broke = cpuORBSU (sim, inst); break;
case CPU_ORI : cpuORI (sim, inst); break;
case CPU_ORNBSU : broke = cpuORNBSU (sim, inst); break;
case CPU_OUT_B : broke = cpuOUT_B (sim, inst); break;
case CPU_OUT_H : broke = cpuOUT_H (sim, inst); break;
case CPU_OUT_W : broke = cpuOUT_W (sim, inst); break;
case CPU_RETI : cpuRETI (sim, inst); break;
case CPU_REV : cpuREV (sim, inst); break;
case CPU_SAR_IMM: cpuSAR_IMM(sim, inst); break;
case CPU_SAR_REG: cpuSAR_REG(sim, inst); break;
case CPU_SCH0BSD: cpuSCH0BSD(sim ); break;
case CPU_SCH0BSU: cpuSCH0BSU(sim ); break;
case CPU_SCH1BSD: cpuSCH1BSD(sim ); break;
case CPU_SCH1BSU: cpuSCH1BSU(sim ); break;
case CPU_SEI : cpuSEI (sim ); break;
case CPU_SETF : cpuSETF (sim, inst); break;
case CPU_SHL_IMM: cpuSHL_IMM(sim, inst); break;
case CPU_SHL_REG: cpuSHL_REG(sim, inst); break;
case CPU_SHR_IMM: cpuSHR_IMM(sim, inst); break;
case CPU_SHR_REG: cpuSHR_REG(sim, inst); break;
case CPU_ST_B : broke = cpuST_B (sim, inst); break;
case CPU_ST_H : broke = cpuST_H (sim, inst); break;
case CPU_ST_W : broke = cpuST_W (sim, inst); break;
case CPU_STSR : cpuSTSR (sim, inst); break;
case CPU_SUB : cpuSUB (sim, inst); break;
case CPU_SUBF_S : cpuSUBF_S (sim, inst); break;
case CPU_TRAP : cpuTRAP (sim, inst); break;
case CPU_TRNC_SW: cpuTRNC_SW(sim, inst); break;
case CPU_XB : cpuXB (sim, inst); break;
case CPU_XH : cpuXH (sim, inst); break;
case CPU_XOR : cpuXOR (sim, inst); break;
case CPU_XORBSU : broke = cpuXORBSU (sim, inst); break;
case CPU_XORI : cpuXORI (sim, inst); break;
case CPU_XORNBSU: broke = cpuXORNBSU(sim, inst); break;
default: /* CPU_ILLEGAL */ sim->cpu.causeCode = 0xFF90;
}
/* Instructions cannot modify r0 */
sim->cpu.program[0] = 0x00000000;
/* An application break was requested */
if (broke)
return 1;
/* Post-instruction tasks */
if (sim->cpu.causeCode == 0 && sim->cpu.busWait == 0) {
/* Advance to next instruction */
if (sim->cpu.state != CPU_HALTED && !sim->cpu.substring)
sim->cpu.pc += inst->size;
/* Check for interrupts */
cpuCheckIRQs(sim);
}
/* An exception or interrupt occurred */
if (sim->cpu.causeCode != 0) {
sim->cpu.state = CPU_EXCEPTION;
sim->cpu.substring = 0;
}
/* Switch to fetch mode */
else if (sim->cpu.state != CPU_HALTED &&
sim->cpu.busWait == 0 && !sim->cpu.substring) {
sim->cpu.state = CPU_FETCH;
}
return 0;
}
/* Enter an exception state */
static int cpuException(VB *sim) {
uint16_t causeCode = sim->cpu.causeCode;
int irq = causeCode < 0xFF00;
/* Fatal exception */
if (sim->cpu.psw.np) {
/* Write the cause code for debugging */
if (sim->cpu.busWait == 0) {
if (cpuWrite(sim, 0x00000000, VB_S32, 0xFFFF0000 | causeCode))
return 1;
/* Update state */
sim->cpu.busWait = 1;
sim->cpu.clocks = sim->cpu.access.clocks;
/* Wait for the bus access to complete */
if (sim->cpu.clocks > 0)
return 0;
}
/* Write PSW for debugging */
if (sim->cpu.busWait == 1) {
if (cpuWrite(sim, 0x00000000, VB_S32,
vbGetSystemRegister(sim, VB_PSW)))
return 1;
/* Update state */
sim->cpu.busWait = 2;
sim->cpu.clocks = sim->cpu.access.clocks;
/* Wait for the bus access to complete */
if (sim->cpu.clocks > 0)
return 0;
}
/* Write PC for debugging */
if (sim->cpu.busWait == 2) {
if (cpuWrite(sim, 0x00000000, VB_S32, sim->cpu.pc))
return 1;
/* Update state */
sim->cpu.busWait = 3;
sim->cpu.clocks = sim->cpu.access.clocks;
/* Wait for the bus access to complete */
if (sim->cpu.clocks > 0)
return 0;
}
/* Update state */
sim->cpu.busWait = 0;
sim->cpu.causeCode = 0;
sim->cpu.state = CPU_FATAL;
return 0;
}
/* Duplexed exception */
if (sim->cpu.psw.ep) {
sim->cpu.ecr.fecc = causeCode;
sim->cpu.fepsw = vbGetSystemRegister(sim, VB_PSW);
sim->cpu.fepc = sim->cpu.pc;
sim->cpu.psw.np = 1;
sim->cpu.pc = 0xFFFFFFD0;
}
/* Exception or interrupt */
else {
sim->cpu.ecr.eicc = causeCode;
sim->cpu.eipsw = vbGetSystemRegister(sim, VB_PSW);
sim->cpu.eipc = sim->cpu.pc + (irq ? 2 : 0);
sim->cpu.psw.ep = 1;
sim->cpu.pc = (causeCode & 0x0040) != 0 ?
0xFFFFFF60 : ((uint32_t) 0xFFFF0000 | (causeCode & 0xFFF0));
}
/* Interrupt */
if (irq)
sim->cpu.psw.i += sim->cpu.psw.i == 15 ? 0 : 1;
/* Update state */
sim->cpu.causeCode = 0;
sim->cpu.state = CPU_FETCH;
sim->cpu.psw.id = 1;
sim->cpu.psw.ae = 0;
/* sim->cpu.clocks = ? */
/* Call the breakpoint handler if available */
return sim->onException != NULL && sim->onException(sim, causeCode);
}
/* Perform instruction fetch operations */
static int cpuFetch(VB *sim) {
VB_INSTRUCTION *inst; /* Reference to sim->cpu.inst */
uint8_t opcode; /* 6-bit instruction opcode */
/* Need to read a data unit */
if (sim->cpu.busWait == 0) {
/* Read the data unit from the bus */
if (cpuReadFetch(sim, sim->cpu.pc + (sim->cpu.fetch << 1)))
return 1;
/* Update state */
sim->cpu.busWait = 1;
sim->cpu.clocks = sim->cpu.access.clocks;
/* Wait for the bus access to complete */
if (sim->cpu.clocks > 0)
return 0;
}
/* Update state */
inst = &sim->cpu.inst;
inst->bits[sim->cpu.fetch] = sim->cpu.access.value;
sim->cpu.busWait = 0;
/* Working variables */
opcode = inst->bits[0] >> 10 & 0x3F;
/* First fetch */
if (sim->cpu.fetch == 0) {
/* Update state */
inst->size = CPU_SIZES[opcode];
/* A second fetch is needed */
if (inst->size == 4) {
sim->cpu.fetch = 1;
return 0;
}
}
/* Determine the internal ID of the instruction */
inst->id = CPU_OPCODES[opcode];
switch (inst->id) {
case CPU_BITSTRING: inst->id=CPU_BITSTRINGS[inst->bits[0]&0x1F]; break;
case CPU_FLOATENDO: inst->id=CPU_FLOATENDOS[inst->bits[1]>>10&0x3F];
}
/* Update state */
sim->cpu.fetch = 0;
sim->cpu.state = CPU_EXECUTE;
return 0;
}
/* Process the simulation for some number of clocks */
static int cpuEmulate(VB *sim, uint32_t clocks) {
/* Fatal halt: cannot break */
if (sim->cpu.state == CPU_FATAL)
return 0;
/* Process all clocks */
do {
/* The next operation is after the remaining clocks */
if (clocks < sim->cpu.clocks) {
sim->cpu.clocks -= clocks;
return 0;
}
/* Update remaining clocks */
clocks -= sim->cpu.clocks;
sim->cpu.clocks = 0;
/* Processing by operations state */
switch (sim->cpu.state) {
case CPU_EXCEPTION: if ( cpuException(sim)) return 1; break;
case CPU_EXECUTE : if ( cpuExecute (sim)) return 1; break;
case CPU_FATAL : return 0;
case CPU_FETCH : if ( cpuFetch (sim)) return 1; break;
case CPU_HALTED : if (!cpuCheckIRQs(sim)) return 0; break;
}
} while (clocks > 0);
/* No break occurred */
return 0;
}
/* Simulate a hardware reset */
static void cpuReset(VB *sim) {
int x; /* Iterator */
/* Registers */
vbSetProgramCounter(sim, 0xFFFFFFF0);
vbSetSystemRegister(sim, VB_ECR, 0x0000FFF0);
vbSetSystemRegister(sim, VB_PSW, 0x00008000);
/* Cache */
vbSetSystemRegister(sim, VB_CHCW, 0x00000000);
/* Other state */
for (x = 0; x < 5; x++)
sim->cpu.irq[x] = 0;
/* Other registers (the hardware does not do this) */
for (x = 0; x < 32; x++)
sim->cpu.program[x] = 0x00000000;
sim->cpu.adtre = 0x00000000;
sim->cpu.eipc = 0x00000000;
sim->cpu.eipsw = 0x00000000;
sim->cpu.fepc = 0x00000000;
sim->cpu.fepsw = 0x00000000;
sim->cpu.sr29 = 0x00000000;
sim->cpu.sr31 = 0x00000000;
}
/* Determine the number of clocks before a break condititon could occur */
static uint32_t cpuUntil(VB *sim, uint32_t clocks) {
/* Cannot break */
if (
sim->cpu.state == CPU_HALTED ||
sim->cpu.state == CPU_FATAL || (
sim->onException == NULL &&
sim->onExecute == NULL &&
sim->onFetch == NULL &&
sim->onRead == NULL &&
sim->onWrite == NULL
)) return clocks;
/* Will not break before next operation */
return sim->cpu.clocks < clocks ? sim->cpu.clocks : clocks;
}
#endif /* WSAPI */
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