269 lines
9.8 KiB
C
269 lines
9.8 KiB
C
/* This file is included through vue.c and cannot be built directly. */
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#ifdef VUEAPI
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/*****************************************************************************
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* Constants *
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*****************************************************************************/
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/* Stages */
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#define CPU_FETCH 0
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#define CPU_EXECUTE 1
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#define CPU_HALT 2
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#define CPU_EXCEPTION 3
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#define CPU_FATAL 4
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#define CPU_CLEAR 5
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#define CPU_DUMP 6
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#define CPU_RESTORE 7
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/* Intermediate instruction IDs */
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#define BITSTRING -2
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#define FLOATENDO -3
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/* Opcode lookup table */
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static const int8_t LOOKUP_OPCODE[] = {
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VUE_MOV_REG, 1, VUE_ADD_REG, 1, VUE_SUB , 1, VUE_CMP_REG, 1,
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VUE_SHL_REG, 1, VUE_SHR_REG, 1, VUE_JMP , 1, VUE_SAR_REG, 1,
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VUE_MUL , 1, VUE_DIV , 1, VUE_MULU , 1, VUE_DIVU , 1,
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VUE_OR , 1, VUE_AND , 1, VUE_XOR , 1, VUE_NOT , 1,
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-VUE_MOV_IMM, 2,-VUE_ADD_IMM, 2, VUE_SETF , 2,-VUE_CMP_IMM, 2,
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VUE_SHL_IMM, 2, VUE_SHR_IMM, 2, VUE_CLI , 2, VUE_SAR_IMM, 2,
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VUE_TRAP , 2, VUE_RETI , 2, VUE_HALT , 2, VUE_ILLEGAL, 0,
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VUE_LDSR , 2, VUE_STSR , 2, VUE_SEI , 2, BITSTRING , 2,
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VUE_BCOND , 3, VUE_BCOND , 3, VUE_BCOND , 3, VUE_BCOND , 3,
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VUE_BCOND , 3, VUE_BCOND , 3, VUE_BCOND , 3, VUE_BCOND , 3,
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-VUE_MOVEA , 5,-VUE_ADDI , 5, VUE_JR , 4, VUE_JAL , 4,
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VUE_ORI , 5, VUE_ANDI , 5, VUE_XORI , 5, VUE_MOVHI , 5,
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VUE_LD_B , 6, VUE_LD_H , 6, VUE_ILLEGAL, 0, VUE_LD_W , 6,
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VUE_ST_B , 6, VUE_ST_H , 6, VUE_ILLEGAL, 0, VUE_ST_W , 6,
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VUE_IN_B , 6, VUE_IN_H , 6, VUE_CAXI , 6, VUE_IN_W , 6,
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VUE_OUT_B , 6, VUE_OUT_H , 6, FLOATENDO , 7, VUE_OUT_W , 6
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};
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/* Bit string lookup table */
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static const int8_t LOOKUP_BITSTRING[] = {
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VUE_SCH0BSU, VUE_SCH0BSD, VUE_SCH1BSU, VUE_SCH1BSD,
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VUE_ILLEGAL, VUE_ILLEGAL, VUE_ILLEGAL, VUE_ILLEGAL,
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VUE_ORBSU , VUE_ANDBSU , VUE_XORBSU , VUE_MOVBSU ,
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VUE_ORNBSU , VUE_ANDNBSU, VUE_XORNBSU, VUE_XORNBSU
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};
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/* Floating-point and Nintendo lookup table */
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static const int8_t LOOKUP_FLOATENDO[] = {
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VUE_CMPF_S , VUE_ILLEGAL, VUE_CVT_WS , VUE_CVT_SW ,
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VUE_ADDF_S , VUE_SUBF_S , VUE_MULF_S , VUE_DIVF_S ,
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VUE_XB , VUE_XH , VUE_REV , VUE_TRNC_SW,
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VUE_MPYHW , VUE_ILLEGAL, VUE_ILLEGAL, VUE_ILLEGAL
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};
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/*****************************************************************************
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* Module Functions *
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*****************************************************************************/
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/* Decode an instruction from its binary encoding */
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static void cpuDecode(VUE_INST *inst, int32_t bits) {
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int8_t extend; /* Sign-extend the immediate operand */
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int32_t x; /* Working variable */
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/* Configure instance fields */
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inst->bits = bits;
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inst->opcode = bits >> 26 & 63;
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x = inst->opcode << 1 | 1;
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extend = LOOKUP_OPCODE[x];
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inst->format = LOOKUP_OPCODE[x + 1];
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inst->id = extend < 0 ? -extend : extend;
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inst->size = inst->format < 4 ? 2 : 4;
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/* Decode by format */
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switch (inst->format) {
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case 1:
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inst->reg2 = bits >> 21 & 31;
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inst->reg1 = bits >> 16 & 31;
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break;
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case 2:
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x = bits >> 16 & 31;
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inst->reg2 = bits >> 21 & 31;
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inst->imm = extend < 0 ? SIGN_EXTEND(5, x) : x;
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if (inst->id == BITSTRING)
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inst->id = x >= 16 ? VUE_ILLEGAL : LOOKUP_BITSTRING[x];
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break;
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case 3:
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x = bits >> 16 & 0x1FF;
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inst->opcode = 0x20;
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inst->cond = bits >> 25 & 15;
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inst->disp = SIGN_EXTEND(9, x);
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break;
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case 4:
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x = bits & 0x3FFFFFF;
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inst->disp = SIGN_EXTEND(26, x);
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break;
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case 5:
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x = bits & 0xFFFF;
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inst->reg2 = bits >> 21 & 31;
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inst->reg1 = bits >> 16 & 31;
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inst->imm = extend < 0 ? SIGN_EXTEND(16, x) : x;
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break;
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case 6:
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x = bits & 0xFFFF;
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inst->reg2 = bits >> 21 & 31;
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inst->reg1 = bits >> 16 & 31;
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inst->disp = SIGN_EXTEND(16, x);
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break;
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case 7:
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inst->reg2 = bits >> 21 & 31;
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inst->reg1 = bits >> 16 & 31;
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inst->subopcode = bits >> 10 & 63;
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inst->id = inst->subopcode >= 16 ? VUE_ILLEGAL :
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LOOKUP_FLOATENDO[inst->subopcode];
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break;
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}
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}
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/* Read a system register */
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static int32_t cpuGetSystemRegister(VUE *vue, int index) {
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switch (index) {
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case VUE_ADTRE: return vue->cpu.adtre;
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case VUE_EIPC : return vue->cpu.eipc;
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case VUE_EIPSW: return vue->cpu.eipsw;
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case VUE_FEPC : return vue->cpu.fepc;
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case VUE_FEPSW: return vue->cpu.fepsw;
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case VUE_ECR : return vue->cpu.ecr_fecc << 16 | vue->cpu.ecr_eicc;
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case VUE_PIR : return 0x00005346;
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case VUE_TKCW : return 0x000000E0;
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case VUE_CHCW : return vue->cpu.chcw_ice << 1;
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case 29 : return vue->cpu.sr29;
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case 30 : return 0x00000004;
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case 31 : return vue->cpu.sr31;
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case VUE_PSW : return
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vue->cpu.psw_i << 16 | vue->cpu.psw_fov << 6 |
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vue->cpu.psw_np << 15 | vue->cpu.psw_fud << 5 |
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vue->cpu.psw_ep << 14 | vue->cpu.psw_fpr << 4 |
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vue->cpu.psw_ae << 13 | vue->cpu.psw_cy << 3 |
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vue->cpu.psw_id << 12 | vue->cpu.psw_ov << 2 |
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vue->cpu.psw_fro << 9 | vue->cpu.psw_s << 1 |
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vue->cpu.psw_fiv << 8 | vue->cpu.psw_z |
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vue->cpu.psw_fzd << 7
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;
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/* Remaining cases to encourage tableswitch */
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case 8: case 9: case 10: case 11: case 12: case 13: case 14:
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case 15: case 16: case 17: case 18: case 19: case 20: case 21:
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case 22: case 23: case 26: case 27: case 28:
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return 0;
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}
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return 1; /* Unreachable */
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}
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/* Write a system register */
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static int32_t cpuSetSystemRegister(VUE *vue, int index, int32_t value,
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vbool debug) {
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switch (index) {
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case VUE_ADTRE: return vue->cpu.adtre = value & 0xFFFFFFFE;
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case VUE_EIPC : return vue->cpu.eipc = value & 0xFFFFFFFE;
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case VUE_EIPSW: return vue->cpu.eipsw = value & 0x000FF3FF;
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case VUE_FEPC : return vue->cpu.fepc = value & 0xFFFFFFFE;
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case VUE_FEPSW: return vue->cpu.fepsw = value & 0x000FF3FF;
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case 29 : return vue->cpu.sr29 = value;
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case 31 : return vue->cpu.sr31 =
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debug || value >= 0 ? value : -value;
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case VUE_CHCW :
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vue->cpu.chcw_cen = value >> 20 & 0x00000FFF;
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vue->cpu.chcw_cec = value >> 8 & 0x00000FFF;
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vue->cpu.chcw_sa = value >> 8 & 0x00FFFFFF;
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vue->cpu.chcw_icr = value >> 5 & 1;
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vue->cpu.chcw_icd = value >> 4 & 1;
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vue->cpu.chcw_ice = value >> 1 & 1;
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vue->cpu.chcw_icc = value & 1;
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/* Only one of ICC, ICD or ICR is set */
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value &= 0x00000031;
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if ((value & (value - 1)) == 0) {
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/* Clear */
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/* Dump */
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/* Restore */
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}
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return vue->cpu.chcw_ice << 1;
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case VUE_ECR:
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if (debug) {
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vue->cpu.ecr_fecc = value >> 16 & 0xFFFF;
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vue->cpu.ecr_eicc = value & 0xFFFF;
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}
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return vue->cpu.ecr_fecc << 16 | vue->cpu.ecr_eicc;
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case VUE_PSW :
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vue->cpu.psw_i = value >> 16 & 15;
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vue->cpu.psw_np = value >> 15 & 1;
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vue->cpu.psw_ep = value >> 14 & 1;
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vue->cpu.psw_ae = value >> 13 & 1;
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vue->cpu.psw_id = value >> 12 & 1;
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vue->cpu.psw_fro = value >> 9 & 1;
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vue->cpu.psw_fiv = value >> 8 & 1;
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vue->cpu.psw_fzd = value >> 7 & 1;
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vue->cpu.psw_fov = value >> 6 & 1;
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vue->cpu.psw_fud = value >> 5 & 1;
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vue->cpu.psw_fpr = value >> 4 & 1;
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vue->cpu.psw_cy = value >> 3 & 1;
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vue->cpu.psw_ov = value >> 2 & 1;
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vue->cpu.psw_s = value >> 1 & 1;
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vue->cpu.psw_z = value & 1;
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return value & 0x000FF3FF;
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/* Remaining cases to encourage tableswitch */
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case 6: case 7: case 8: case 9: case 10: case 11: case 12:
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case 13: case 14: case 15: case 16: case 17: case 18: case 19:
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case 20: case 21: case 22: case 23: case 26: case 27: case 28:
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case 30:
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return 0;
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}
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return 1; /* Unreachable */
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}
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/* Perform a system reset */
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static void cpuReset(VUE *vue) {
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int x;
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/* Configure instance fields */
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vue->cpu.cycles = 0; /* Duration of first fetch */
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vue->cpu.fetch = 0;
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vue->cpu.stage = CPU_FETCH;
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/* Clear all registers (hardware only sets ECR, PC and PSW) */
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for (x = 0; x < 32; x++) {
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vue->cpu.program[x] = 0;
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cpuSetSystemRegister(vue, x, 0, VUE_TRUE);
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}
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/* Configure jump history */
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for (x = 0; x < 3; x++)
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vue->cpu.jumpFrom[x] = vue->cpu.jumpTo[x] = 0xFFFFFFF0;
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/* Configure registers */
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vue->cpu.ecr_eicc = 0xFFF0;
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vue->cpu.pc = 0xFFFFFFF0;
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vue->cpu.psw_np = 1;
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}
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/* Test a condition */
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static int8_t cpuTest(VUE *vue, int condition) {
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switch (condition) {
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case 0: return vue->cpu.psw_ov;
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case 1: return vue->cpu.psw_cy;
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case 2: return vue->cpu.psw_z;
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case 3: return vue->cpu.psw_cy | vue->cpu.psw_z;
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case 4: return vue->cpu.psw_s;
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case 5: return 1;
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case 6: return vue->cpu.psw_ov | vue->cpu.psw_s;
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case 7: return (vue->cpu.psw_ov ^ vue->cpu.psw_s) | vue->cpu.psw_z;
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}
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return cpuTest(vue, condition & 7) ^ 1;
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}
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#endif
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