547 lines
18 KiB
JavaScript
547 lines
18 KiB
JavaScript
// Machine code to human readable text converter
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class Disassembler {
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//////////////////////////////// Constants ////////////////////////////////
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// Default settings
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static DEFAULTS = {
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condCL : "L", // Use C/NC or L/NL for conditions
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condEZ : "E", // Use E/NE or Z/NZ for conditions
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condNames : true, // Use condition names
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condUppercase: false, // Condition names uppercase
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hexPrefix : "0x", // Hexadecimal prefix
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hexSuffix : "", // Hexadecimal suffix
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hexUppercase : true, // Hexadecimal uppercase
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instUppercase: true, // Mnemonics uppercase
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jumpAddress : true, // Jump/branch shows target address
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memInside : false, // Use [reg1 + disp] notation
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opDestFirst : false, // Destination operand first
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proNames : true, // Use program register names
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proUppercase : false, // Program register names uppercase
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splitBcond : false, // BCOND condition as an operand
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splitSetf : true, // SETF condition as an operand
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sysNames : true, // Use system register names
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sysUppercase : false // System register names uppercase
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};
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/////////////////////////// Disassembly Lookup ////////////////////////////
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// Opcode descriptors
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static OPDEFS = [
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[ "MOV" , [ "opReg1" , "opReg2" ] ], // 000000
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[ "ADD" , [ "opReg1" , "opReg2" ] ],
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[ "SUB" , [ "opReg1" , "opReg2" ] ],
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[ "CMP" , [ "opReg1" , "opReg2" ] ],
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[ "SHL" , [ "opReg1" , "opReg2" ] ],
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[ "SHR" , [ "opReg1" , "opReg2" ] ],
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[ "JMP" , [ "opReg1Ind" ] ],
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[ "SAR" , [ "opReg1" , "opReg2" ] ],
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[ "MUL" , [ "opReg1" , "opReg2" ] ],
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[ "DIV" , [ "opReg1" , "opReg2" ] ],
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[ "MULU" , [ "opReg1" , "opReg2" ] ],
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[ "DIVU" , [ "opReg1" , "opReg2" ] ],
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[ "OR" , [ "opReg1" , "opReg2" ] ],
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[ "AND" , [ "opReg1" , "opReg2" ] ],
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[ "XOR" , [ "opReg1" , "opReg2" ] ],
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[ "NOT" , [ "opReg1" , "opReg2" ] ],
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[ "MOV" , [ "opImm5S", "opReg2" ] ], // 010000
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[ "ADD" , [ "opImm5S", "opReg2" ] ],
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null, // SETF: special
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[ "CMP" , [ "opImm5S", "opReg2" ] ],
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[ "SHL" , [ "opImm5U", "opReg2" ] ],
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[ "SHR" , [ "opImm5U", "opReg2" ] ],
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[ "CLI" , [ ] ],
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[ "SAR" , [ "opImm5U", "opReg2" ] ],
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[ "TRAP" , [ "opImm5U" ] ],
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[ "RETI" , [ ] ],
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[ "HALT" , [ ] ],
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null, // Invalid
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[ "LDSR" , [ "opReg2" , "opSys" ] ],
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[ "STSR" , [ "opSys" , "opReg2" ] ],
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[ "SEI" , [ ] ],
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null, // Bit string: special
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null, // BCOND: special // 100000
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null, // BCOND: special
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null, // BCOND: special
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null, // BCOND: special
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null, // BCOND: special
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null, // BCOND: special
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null, // BCOND: special
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null, // BCOND: special
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[ "MOVEA", [ "opImm16U" , "opReg1", "opReg2" ] ],
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[ "ADDI" , [ "opImm16S" , "opReg1", "opReg2" ] ],
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[ "JR" , [ "opDisp26" ] ],
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[ "JAL" , [ "opDisp26" ] ],
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[ "ORI" , [ "opImm16U" , "opReg1", "opReg2" ] ],
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[ "ANDI" , [ "opImm16U" , "opReg1", "opReg2" ] ],
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[ "XORI" , [ "opImm16U" , "opReg1", "opReg2" ] ],
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[ "MOVHI", [ "opImm16U" , "opReg1", "opReg2" ] ],
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[ "LD.B" , [ "opReg1Disp", "opReg2" ] ], // 110000
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[ "LD.H" , [ "opReg1Disp", "opReg2" ] ],
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null, // Invalid
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[ "LD.W" , [ "opReg1Disp", "opReg2" ] ],
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[ "ST.B" , [ "opReg2" , "opReg1Disp" ] ],
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[ "ST.H" , [ "opReg2" , "opReg1Disp" ] ],
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null, // Invalid
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[ "ST.W" , [ "opReg2" , "opReg1Disp" ] ],
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[ "IN.B" , [ "opReg1Disp", "opReg2" ] ],
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[ "IN.H" , [ "opReg1Disp", "opReg2" ] ],
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[ "CAXI" , [ "opReg1Disp", "opReg2" ] ],
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[ "IN.W" , [ "opReg1Disp", "opReg2" ] ],
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[ "OUT.B", [ "opReg2" , "opReg1Disp" ] ],
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[ "OUT.H", [ "opReg2" , "opReg1Disp" ] ],
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null, // Floating-point/Nintendo: special
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[ "OUT.W", [ "opReg2" , "opReg1Disp" ] ]
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];
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// Bit string sub-opcode descriptors
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static BITSTRING = [
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"SCH0BSU", "SCH0BSD", "SCH1BSU", "SCH1BSD",
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null , null , null , null ,
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"ORBSU" , "ANDBSU" , "XORBSU" , "MOVBSU" ,
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"ORNBSU" , "ANDNBSU", "XORNBSU", "NOTBSU" ,
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null , null , null , null ,
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null , null , null , null ,
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null , null , null , null ,
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null , null , null , null
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];
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// Floating-point/Nintendo sub-opcode descriptors
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static FLOATENDO = [
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[ "CMPF.S" , [ "opReg1", "opReg2" ] ],
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null, // Invalid
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[ "CVT.WS" , [ "opReg1", "opReg2" ] ],
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[ "CVT.SW" , [ "opReg1", "opReg2" ] ],
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[ "ADDF.S" , [ "opReg1", "opReg2" ] ],
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[ "SUBF.S" , [ "opReg1", "opReg2" ] ],
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[ "MULF.S" , [ "opReg1", "opReg2" ] ],
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[ "DIVF.S" , [ "opReg1", "opReg2" ] ],
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[ "XB" , [ "opReg2" ] ],
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[ "XH" , [ "opReg2" ] ],
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[ "REV" , [ "opReg1", "opReg2" ] ],
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[ "TRNC.SW", [ "opReg1", "opReg2" ] ],
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[ "MPYHW" , [ "opReg1", "opReg2" ] ],
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null, null, null,
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null, null, null, null, null, null, null, null,
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null, null, null, null, null, null, null, null,
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null, null, null, null, null, null, null, null,
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null, null, null, null, null, null, null, null,
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null, null, null, null, null, null, null, null,
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null, null, null, null, null, null, null, null
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];
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// Condition mnemonics
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static CONDITIONS = [
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"V" , "C" , "E" , "NH", "N", "T", "LT", "LE",
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"NV", "NC", "NE", "H" , "P", "F", "GE", "GT"
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];
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// Program register names
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static REG_PROGRAM = [
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"r0" , "r1" , "hp" , "sp" , "gp" , "tp" , "r6" , "r7" ,
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"r8" , "r9" , "r10", "r11", "r12", "r13", "r14", "r15",
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"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
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"r24", "r25", "r26", "r27", "r28", "r29", "r30", "lp"
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];
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// System register names
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static REG_SYSTEM = [
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"EIPC", "EIPSW", "FEPC", "FEPSW", "ECR", "PSW", "PIR", "TKCW",
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"8" , "9" , "10" , "11" , "12" , "13" , "14" , "15" ,
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"16" , "17" , "18" , "19" , "20" , "21" , "22" , "23" ,
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"CHCW", "ADTRE", "26" , "27" , "28" , "29" , "30" , "31"
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];
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// Other register names
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static REG_OTHER = [ "PC", "PSW" ];
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///////////////////////////// Static Methods //////////////////////////////
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// Determine the bounds of a data buffer to represent all lines of output
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static dataBounds(address, line, length) {
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let before = 10; // Number of lines before the first line of output
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let max = 4; // Maximum number of bytes that can appear on a line
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// The reference line is before the preferred earliest line
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if (line < -before) {
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length = (length - line) * max;
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}
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// The reference line is before the first line
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else if (line < 0) {
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address -= (line + before) * max;
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length = (length + before) * max;
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}
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// The reference line is at or after the first line
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else {
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address -= (line + before) * max;
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length = (Math.max(length, line) + before) * max;
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}
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return {
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address: (address & ~1) >>> 0,
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length : length
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};
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}
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///////////////////////// Initialization Methods //////////////////////////
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constructor() {
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Object.assign(this, Disassembler.DEFAULTS);
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}
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///////////////////////////// Public Methods //////////////////////////////
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// Disassemble a region of memory
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disassemble(data, dataAddress, refAddress, refLine, length, pc = null) {
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let pcOffset = pc === null ? -1 : pc - dataAddress >>> 0;
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// Locate the offset of the first line of output in the buffer
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let offset = 0;
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for (let
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addr = dataAddress,
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circle = refLine > 0 ? new Array(refLine) : null,
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index = 0,
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more = [],
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remain = null
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;;) {
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// Determine the size of the current line
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if (more.length == 0)
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this.more(more, data, offset);
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let size = more.shift();
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// The current line contains the reference address
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if (refAddress - addr >>> 0 < size) {
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// The next item in the buffer is the first line of output
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if (refLine > 0) {
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offset = circle[index];
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break;
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}
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// This line is the first line of output
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if (refLine == 0)
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break;
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// Count more lines for the first line of output
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remain = refLine;
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}
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// Record the offset of the current instruction
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if (refLine > 0) {
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circle[index] = offset;
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index = (index + 1) % circle.length;
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}
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// Advance to the next line
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let sizeToPC = pcOffset - offset >>> 0;
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if (offset != pcOffset && sizeToPC < size) {
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size = sizeToPC;
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more.splice();
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}
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addr = addr + size >>> 0;
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offset += size;
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if (remain !== null && ++remain == 0)
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break; // The next line is the first line of output
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}
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// Process all lines of output
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let lines = new Array(length);
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for (let
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addr = dataAddress + offset,
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more = [],
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x = 0;
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x < length; x++
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) {
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// Determine the size of the current line
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if (more.length == 0)
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this.more(more, data, offset, pcOffset);
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let size = more.shift();
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// Add the line to the response
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lines[x] = this.format({
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rawAddress: addr,
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rawBytes : data.slice(offset, offset + size)
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});
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// Advance to the next line
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let sizeToPC = pcOffset - offset >>> 0;
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if (offset != pcOffset && sizeToPC < size) {
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size = sizeToPC;
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more.splice();
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}
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addr = addr + size >>> 0;
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offset += size;
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}
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return lines;
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}
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/////////////////////////// Formatting Methods ////////////////////////////
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// Format a line as human-readable text
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format(line) {
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let canReverse = true;
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let opcode = line.rawBytes[1] >>> 2;
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let opdef;
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let code = [
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line.rawBytes[1] << 8 | line.rawBytes[0],
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line.rawBytes.length == 2 ? null :
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line.rawBytes[3] << 8 | line.rawBytes[2]
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];
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// BCOND
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if ((opcode & 0b111000) == 0b100000) {
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let cond = code[0] >>> 9 & 15;
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opdef =
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cond == 13 ? [ "NOP", [ ] ] :
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this.splitBcond ? [ "BCOND", [ "opBCond", "opDisp9" ] ] :
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[
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cond == 5 ? "BR" : "B" + this.condition(cond, true),
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[ "opDisp9" ]
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]
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;
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canReverse = false;
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}
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// Processing by opcode
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else switch (opcode) {
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// SETF
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case 0b010010:
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opdef = !this.splitSetf ?
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[
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"SETF" + Disassembler.CONDITIONS[code[0] & 15],
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[ "opReg2" ]
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] :
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[ "SETF", [ "opCond", "opReg2" ] ]
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;
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break;
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// Bit string
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case 0b011111:
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opdef = Disassembler.BITSTRING[code[0] & 31];
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if (opdef != null)
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opdef = [ opdef, [] ];
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break;
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// Floating-point/Nintendo
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case 0b111110:
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opdef = Disassembler.FLOATENDO[code[1] >>> 10];
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break;
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// All others
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default: opdef = Disassembler.OPDEFS[opcode];
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}
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// The opcode is undefined
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if (opdef == null)
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opdef = [ "---", [] ];
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// Format the line's display text
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line.address = this.hex(line.rawAddress, 8, false);
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line.bytes = new Array(line.rawBytes.length);
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line.mnemonic = this.instUppercase ? opdef[0] : opdef[0].toLowerCase();
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line.operands = new Array(opdef[1].length);
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for (let x = 0; x < line.bytes.length; x++)
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line.bytes[x] = this.hex(line.rawBytes[x], 2, false);
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for (let x = 0; x < line.operands.length; x++)
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line.operands[x] = this[opdef[1][x]](line, code);
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if (this.opDestFirst && canReverse)
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line.operands.reverse();
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return line;
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}
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// Format a condition operand in a BCOND instruction
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opBCond(line, code) {
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return this.condition(code[0] >>> 9 & 15);
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}
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// Format a condition operand in a SETF instruction
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opCond(line, code) {
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return this.condition(code[0] & 15);
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}
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// Format a 9-bit displacement operand
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opDisp9(line, code) {
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let disp = code[0] << 23 >> 23;
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return this.jump(line.rawAddress, disp);
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}
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// Format a 26-bit displacement operand
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opDisp26(line, code) {
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let disp = (code[0] << 16 | code[1]) << 6 >> 6;
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return this.jump(line.rawAddress, disp);
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}
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// Format a 5-bit signed immediate operand
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opImm5S(line, code) {
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return (code[0] & 31) << 27 >> 27;
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}
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// Format a 5-bit unsigned immediate operand
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opImm5U(line, code) {
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return code[0] & 31;
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}
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// Format a 16-bit signed immediate operand
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opImm16S(line, code) {
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let ret = code[1] << 16 >> 16;
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return (
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ret < -256 ? "-" + this.hex(-ret) :
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ret > 256 ? this.hex( ret) :
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ret
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);
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}
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// Format a 16-bit unsigned immediate operand
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opImm16U(line, code) {
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return this.hex(code[1], 4);
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}
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// Format a Reg1 operand
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opReg1(line, code) {
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return this.programRegister(code[0] & 31);
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}
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// Format a disp[reg1] operand
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opReg1Disp(line, code) {
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let disp = code[1] << 16 >> 16;
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let reg1 = this.programRegister(code[0] & 31);
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// Do not print the displacement
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if (disp == 0)
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return "[" + reg1 + "]";
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// Format the displacement amount
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disp =
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disp < -256 ? "-" + this.hex(-disp) :
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disp > 256 ? this.hex( disp) :
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disp.toString()
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;
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// [reg1 + disp] notation
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if (this.memInside) {
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return "[" + reg1 + (disp.startsWith("-") ?
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" - " + disp.substring(1) :
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" + " + disp
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) + "]";
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}
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// disp[reg1] notation
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return disp + "[" + reg1 + "]";
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}
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// Format a [Reg1] operand
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opReg1Ind(line, code) {
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return "[" + this.programRegister(code[0] & 31) + "]";
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}
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// Format a Reg2 operand
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opReg2(line, code) {
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return this.programRegister(code[0] >> 5 & 31);
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}
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// Format a system register operand
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opSys(line, code) {
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return this.systemRegister(code[0] & 31);
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}
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///////////////////////////// Private Methods /////////////////////////////
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// Select the mnemonic for a condition
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condition(index, forceUppercase = false) {
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if (!this.condNames)
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return index.toString();
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let ret =
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index == 1 ? this.condCL :
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index == 2 ? this.condEZ :
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index == 9 ? "N" + this.condCL :
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index == 10 ? "N" + this.condEZ :
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Disassembler.CONDITIONS[index]
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;
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if (!forceUppercase && !this.condUppercase)
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ret = ret.toLowerCase();
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return ret;
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}
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// Format a number as a hexadecimal string
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hex(value, digits = null, decorated = true) {
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value = value.toString(16);
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if (this.hexUppercase)
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value = value.toUpperCase();
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if (digits != null)
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value = value.padStart(digits, "0");
|
|
if (decorated) {
|
|
value = this.hexPrefix + value + this.hexSuffix;
|
|
if (this.hexPrefix == "" && "0123456789".indexOf(value[0]) == -1)
|
|
value = "0" + value;
|
|
}
|
|
return value;
|
|
}
|
|
|
|
// Format a jump or branch destination
|
|
jump(address, disp) {
|
|
return (
|
|
this.jumpAddress ?
|
|
this.hex(address + disp >>> 0, 8, false) :
|
|
disp < -256 ? "-" + this.hex(-disp) :
|
|
disp > 256 ? "+" + this.hex( disp) :
|
|
disp.toString()
|
|
);
|
|
}
|
|
|
|
// Determine the number of bytes in the next line(s) of disassembly
|
|
more(more, data, offset) {
|
|
|
|
// Error checking
|
|
if (offset + 1 >= data.length)
|
|
throw new Error("Disassembly error: Unexpected EoF");
|
|
|
|
// Determine the instruction's size from its opcode
|
|
let opcode = data[offset + 1] >>> 2;
|
|
more.push(
|
|
opcode < 0b101000 || // 16-bit instruction
|
|
opcode == 0b110010 || // Illegal opcode
|
|
opcode == 0b110110 // Illegal opcode
|
|
? 2 : 4);
|
|
}
|
|
|
|
// Format a program register
|
|
programRegister(index) {
|
|
let ret = this.proNames ?
|
|
Disassembler.REG_PROGRAM[index] : "r" + index;
|
|
if (this.proUppercase)
|
|
ret = ret.toUpperCase();
|
|
return ret;
|
|
}
|
|
|
|
// Format a system register
|
|
systemRegister(index) {
|
|
let ret = this.sysNames ?
|
|
Disassembler.REG_SYSTEM[index] : index.toString();
|
|
if (!this.sysUppercase && this.sysNames)
|
|
ret = ret.toLowerCase();
|
|
return ret;
|
|
}
|
|
|
|
}
|
|
|
|
export { Disassembler };
|