1140 lines
33 KiB
Java
1140 lines
33 KiB
Java
package vue;
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// Java imports
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import java.util.*;
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// CPU state
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class CPU {
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// Private fields
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private JavaVue vue; // Emulation state
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// Package fields
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Access access; // Access state
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int cycles; // Cycles until next stage
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int exception; // Exception code
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int fetch; // Fetch unit index
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Instruction inst; // Instruction state
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int irq; // Interrupt lines
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int[] jumpFrom; // Source PCs of most recent jumps
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int[] jumpTo; // Destination PCs of most recent jumps
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int stage; // Current processing stage
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// Program registers
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int[] program;
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// System registers
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int adtre; // Address Trap Register for Execution
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int eipc; // Exception/interrupt PC
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int eipsw; // Exception/interrupt PSW
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int fepc; // Duplexed exception PC
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int fepsw; // Duplexed exception PSW
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int pc; // Program Counter
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int sr29; // System register 29
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int sr31; // System register 31
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// Program Status Word
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int psw_ae; // Address Trap Enable
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int psw_ep; // Exception Pending
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int psw_id; // Interrupt Disable
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int psw_cy; // Carry
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int psw_fiv; // Floating Reserved Operand
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int psw_fov; // Floating Overflow
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int psw_fpr; // Floating Precision
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int psw_fro; // Floating Reserved Operand
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int psw_fud; // Floating Underflow
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int psw_fzd; // Floating Zero Divide
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int psw_i; // Interrupt Level
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int psw_np; // NMI Pending
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int psw_ov; // Overflow
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int psw_s; // Sign
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int psw_z; // Zero
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// Cache Control Word
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int chcw_cec; // Clear Entry Count
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int chcw_cen; // Clear Entry Number
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int chcw_icc; // Instruction Cache Clear
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int chcw_icd; // Instruction Cache Dump
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int chcw_ice; // Instruction Cache Enable
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int chcw_icr; // Instruction Cache Restore
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int chcw_sa; // Spill-Out Base Address
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// Exception Cause Register
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int ecr_eicc; // Exception/Interrupt Cause Code
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int ecr_fecc; // Fatal Error Cause Code
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///////////////////////////////////////////////////////////////////////////
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// Constants //
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///////////////////////////////////////////////////////////////////////////
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// Stages
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static final int FATAL = -1;
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static final int FETCH = 0;
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static final int EXECUTE = 1;
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static final int EXCEPTION = 2;
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static final int HALT = 3;
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static final int CLEAR = 4;
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static final int DUMP = 5;
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static final int RESTORE = 6;
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// Instruction cycle counts
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private static final byte[] CYCLES = {
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1, 1, 28, 1, 1, 1, 1, 1, 1, 26, 12, 1, 1, 10, 14, 16,
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38, 44, 36, 1, 5, 5, 5, 3, 3, 3, 5, 5, 5, 8, 1, 1,
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1, 1, 1, 9, 13, 30, 13, 1, 1, 1, 1, 1, 1, 4, 4, 4,
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10, 22, 1, 1, 1, 1, 1, 1, 12, 1, 1, 1, 1, 1, 4, 4,
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4, 8, 1, 28, 15, 14, 6, 1, 1, 1, 1, 1
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};
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///////////////////////////////////////////////////////////////////////////
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// Constructors //
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///////////////////////////////////////////////////////////////////////////
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// Default constructor
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CPU(JavaVue vue) {
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access = new Access();
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inst = new Instruction();
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jumpFrom = new int[3];
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jumpTo = new int[3];
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program = new int[32];
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this.vue = vue;
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}
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///////////////////////////////////////////////////////////////////////////
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// Package Methods //
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///////////////////////////////////////////////////////////////////////////
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// Process the simulation
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void emulate(int cycles) {
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// The CPU is in fatal halt status
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if (stage == FATAL)
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return;
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// Process for the given number of cycles
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for (;;) {
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// The next stage occurs after the given number of cycles
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if (this.cycles > cycles) {
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this.cycles -= cycles;
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return;
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}
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// Processing by stage
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cycles -= this.cycles;
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this.cycles = 0;
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switch (stage) {
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case EXCEPTION: if (exception()) return; break;
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case EXECUTE : if (execute ()) return; break;
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case FETCH : if (fetch ()) return; break;
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case HALT : testException(); return;
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}
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}
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}
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// Read a system register
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int getSystemRegister(int index) {
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switch (index) {
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case Vue.ADTRE: return adtre;
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case Vue.EIPC : return eipc;
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case Vue.EIPSW: return eipsw;
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case Vue.FEPC : return fepc;
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case Vue.FEPSW: return fepsw;
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case Vue.ECR : return ecr_fecc << 16 | ecr_eicc;
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case Vue.PIR : return 0x00005346;
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case Vue.TKCW : return 0x000000E0;
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case Vue.CHCW : return chcw_ice << 1;
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case 29 : return sr29;
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case 30 : return 0x00000004;
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case 31 : return sr31;
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case Vue.PSW : return
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psw_i << 16 | psw_fro << 9 | psw_fpr << 4 |
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psw_np << 15 | psw_fiv << 8 | psw_cy << 3 |
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psw_ep << 14 | psw_fzd << 7 | psw_ov << 2 |
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psw_ae << 13 | psw_fov << 6 | psw_s << 1 |
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psw_id << 12 | psw_fud << 5 | psw_z
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;
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// Remaining cases to encourage tableswitch
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case 8: case 9: case 10: case 11: case 12: case 13: case 14:
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case 15: case 16: case 17: case 18: case 19: case 20: case 21:
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return 0;
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}
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return 1; // Unreachable
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}
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// System reset
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void reset() {
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// Configure instance fields
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cycles = 0;
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exception = 0;
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fetch = -1;
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irq = 0;
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stage = FETCH;
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// Clear all registers (hardware only sets ECR, PC and PSW)
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for (int x = 0; x < 32; x++) {
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program[x] = 0;
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setSystemRegister(x, 0, true);
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}
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// Configure jump histories
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Arrays.fill(jumpFrom, 0xFFFFFFF0);
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Arrays.fill(jumpTo , 0xFFFFFFF0);
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// Configure registers
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ecr_eicc = 0xFFF0;
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pc = 0xFFFFFFF0;
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psw_np = 1;
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}
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// Write a system register
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int setSystemRegister(int index, int value, boolean debug) {
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switch (index) {
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case Vue.ADTRE: return adtre = value & 0xFFFFFFFE;
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case Vue.EIPC : return eipc = value & 0xFFFFFFFE;
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case Vue.EIPSW: return eipsw = value & 0x000FF3FF;
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case Vue.FEPC : return fepc = value & 0xFFFFFFFE;
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case Vue.FEPSW: return fepsw = value & 0x000FF3FF;
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case 29 : return sr29 = value;
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case 31 : return sr31 = debug || value >= 0 ? value : -value;
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case Vue.ECR:
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if (debug) {
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ecr_fecc = value >> 16 & 0xFFFF;
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ecr_eicc = value & 0xFFFF;
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}
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return ecr_fecc << 16 | ecr_eicc;
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case Vue.CHCW :
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chcw_cen = value >> 20 & 0x00000FFF;
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chcw_cec = value >> 8 & 0x00000FFF;
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chcw_sa = value >> 8 & 0x00FFFFFF;
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chcw_icr = value >> 5 & 1;
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chcw_icd = value >> 4 & 1;
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chcw_ice = value >> 1 & 1;
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chcw_icc = value & 1;
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// Only one of ICC, ICD or ICR is set
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value &= 0x00000031;
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if ((value & value - 1) == 0) {
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// Clear
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// Dump
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// Restore
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}
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return chcw_ice << 1;
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case Vue.PSW :
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psw_i = value >> 16 & 15; psw_fov = value >> 6 & 1;
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psw_np = value >> 15 & 1; psw_fud = value >> 5 & 1;
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psw_ep = value >> 14 & 1; psw_fpr = value >> 4 & 1;
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psw_ae = value >> 13 & 1; psw_cy = value >> 3 & 1;
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psw_id = value >> 12 & 1; psw_ov = value >> 2 & 1;
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psw_fro = value >> 9 & 1; psw_s = value >> 1 & 1;
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psw_fiv = value >> 8 & 1; psw_z = value & 1;
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psw_fzd = value >> 7 & 1;
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return value & 0x000FF3FF;
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// Remaining cases to encourage tableswitch
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case 6: case 7: case 8: case 9: case 10: case 11: case 12:
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case 13: case 14: case 15: case 16: case 17: case 18: case 19:
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case 20: case 21: case 22: case 23: case 26: case 27: case 28:
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case 30:
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return 0;
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}
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return 1; // Unreachable
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}
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// Determine the number of CPU cycles until a breakpoint could trigger
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int until(int cycles) {
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return stage == FATAL || stage == HALT ?
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cycles : Math.min(cycles, this.cycles);
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}
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///////////////////////////////////////////////////////////////////////////
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// Private Methods //
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///////////////////////////////////////////////////////////////////////////
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// Operations for exception stage
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private boolean exception() {
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// Check for breakpoints
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if (vue.onBreakpoint(Breakpoint.EXCEPTION))
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return true;
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// Configure working variables
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exception &= 0xFFFF;
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boolean isIRQ = (exception & 0xFF00) == 0xFE00;
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int psw = getSystemRegister(Vue.PSW);
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// Fatal exception
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if (psw_np != 0) {
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vue.write(0x00000000, Vue.S32, 0xFFFF0000 | exception);
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vue.write(0x00000004, Vue.S32, psw);
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vue.write(0x00000008, Vue.S32, pc);
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stage = FATAL;
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return true;
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}
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// Duplexed exception
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if (psw_ep != 0) {
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ecr_fecc = exception;
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fepc = pc;
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fepsw = psw;
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psw_np = 1;
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pc = 0xFFFFFFD0;
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}
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// Regular exception
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else {
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ecr_eicc = exception;
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eipc = pc;
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eipsw = psw;
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psw_ep = 1;
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pc = 0xFFFF0000 | exception & 0xFFF0;
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if (pc == 0xFFFFFF70) // FIV
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pc = 0xFFFFFF60;
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}
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// Interrupt
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if (isIRQ) {
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psw_i = Math.min(15, exception >> 4 & 15);
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if (stage == HALT)
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pc += 2;
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}
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// Common processing
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cycles = 0; // TODO: Determine the actual number
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exception = 0;
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psw_ae = 0;
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psw_id = 1;
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stage = FETCH;
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return false;
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}
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// Operations for execute stage
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private boolean execute() {
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// Check for breakpoints
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if (vue.onBreakpoint(Breakpoint.EXECUTE))
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return true;
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// Processing by instruction ID
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switch (inst.id) {
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case Vue.ADD_IMM: ADD_IMM(); break;
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case Vue.ADD_REG: ADD_REG(); break;
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case Vue.ADDF_S : ADDF_S (); break;
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case Vue.ADDI : ADDI (); break;
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case Vue.AND : AND (); break;
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//case Vue.ANDBSU : ANDBSU (); break;
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case Vue.ANDI : ANDI (); break;
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//case Vue.ANDNBSU: ANDNBSU(); break;
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case Vue.BCOND : BCOND (); break;
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case Vue.CAXI : CAXI (); break;
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case Vue.CLI : CLI (); break;
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case Vue.CMP_IMM: CMP_IMM(); break;
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case Vue.CMP_REG: CMP_REG(); break;
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case Vue.CMPF_S : CMPF_S (); break;
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case Vue.CVT_SW : CVT_SW (); break;
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case Vue.CVT_WS : CVT_WS (); break;
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case Vue.DIV : DIV (); break;
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case Vue.DIVF_S : DIVF_S (); break;
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case Vue.DIVU : DIVU (); break;
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case Vue.HALT : HALT (); break;
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case Vue.IN_B : IN_B (); break;
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case Vue.IN_H : IN_H (); break;
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case Vue.IN_W : IN_W (); break;
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case Vue.JAL : JAL (); break;
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case Vue.JMP : JMP (); break;
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case Vue.JR : JR (); break;
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case Vue.LD_B : LD_B (); break;
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case Vue.LD_H : LD_H (); break;
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case Vue.LD_W : LD_W (); break;
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case Vue.LDSR : LDSR (); break;
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case Vue.MOV_IMM: MOV_IMM(); break;
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case Vue.MOV_REG: MOV_REG(); break;
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//case Vue.MOVBSU : MOVBSU (); break;
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case Vue.MOVEA : MOVEA (); break;
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case Vue.MOVHI : MOVHI (); break;
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case Vue.MPYHW : MPYHW (); break;
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case Vue.MUL : MUL (); break;
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case Vue.MULF_S : MULF_S (); break;
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case Vue.MULU : MULU (); break;
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case Vue.NOT : NOT (); break;
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//case Vue.NOTBSU : NOTBSU (); break;
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case Vue.OR : OR (); break;
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//case Vue.ORBSU : ORBSU (); break;
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case Vue.ORI : ORI (); break;
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//case Vue.ORNBSU : ORNBSU (); break;
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case Vue.OUT_B : OUT_B (); break;
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case Vue.OUT_H : OUT_H (); break;
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case Vue.OUT_W : OUT_W (); break;
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case Vue.RETI : RETI (); break;
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case Vue.REV : REV (); break;
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case Vue.SAR_IMM: SAR_IMM(); break;
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case Vue.SAR_REG: SAR_REG(); break;
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//case Vue.SCH0BSD: SCH0BSD(); break;
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//case Vue.SCH0BSU: SCH0BSU(); break;
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//case Vue.SCH1BSD: SCH1BSD(); break;
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//case Vue.SCH1BSU: SCH1BSU(); break;
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case Vue.SEI : SEI (); break;
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case Vue.SETF : SETF (); break;
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case Vue.SHL_IMM: SHL_IMM(); break;
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case Vue.SHL_REG: SHL_REG(); break;
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case Vue.SHR_IMM: SHR_IMM(); break;
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case Vue.SHR_REG: SHR_REG(); break;
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case Vue.ST_B : ST_B (); break;
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case Vue.ST_H : ST_H (); break;
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case Vue.ST_W : ST_W (); break;
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case Vue.STSR : STSR (); break;
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case Vue.SUB : SUB (); break;
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case Vue.SUBF_S : SUBF_S (); break;
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case Vue.TRAP : TRAP (); break;
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case Vue.TRNC_SW: TRNC_SW(); break;
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case Vue.XB : XB (); break;
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case Vue.XH : XH (); break;
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case Vue.XOR : XOR (); break;
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//case Vue.XORBSU : XORBSU (); break;
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case Vue.XORI : XORI (); break;
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//case Vue.XORNBSU: XORNBSU(); break;
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default: // Invalid instruction
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exception = 0xFF90;
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}
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// An application break was requested
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if (vue.breakCode != 0)
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return true;
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// Common processing
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if (exception == 0) {
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cycles += CYCLES[inst.id];
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pc += inst.size;
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}
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program[0] = 0;
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testException();
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if (stage == EXECUTE)
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stage = FETCH;
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return false;
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}
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// Operations for fetch stage
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private boolean fetch() {
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// Entering the fetch stage
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if (fetch == -1)
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fetch = 0;
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// Read the bits from the bus
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if (read(pc + (fetch << 1), Vue.U16, fetch))
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return true;
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// TODO: Determine how many cycles this takes
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// First unit
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if (fetch == 0) {
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inst.bits = access.value;
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if (Instruction.size(access.value >> 10) == 4) {
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fetch = 1;
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return false;
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}
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}
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// Second unit
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else {
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inst.bits |= access.value << 16;
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fetch = -1;
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}
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// Decode the instruction and advance to execute stage
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inst.decode(inst.bits);
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stage = EXECUTE;
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return false;
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}
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// Perform a bus read
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private boolean read(int address, int type, int fetch) {
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// Perform the operation
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access.address = address;
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access.fetch = fetch;
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access.type = type;
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access.value = vue.read(address, type);
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// Check for breakpoints
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return vue.onBreakpoint(Breakpoint.READ);
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}
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// Test a condition
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private int testCondition(int condition) {
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switch (condition) {
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case 0: return psw_ov;
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case 1: return psw_cy;
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case 2: return psw_z;
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case 3: return psw_cy | psw_z;
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case 4: return psw_s;
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case 5: return 1;
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case 6: return psw_ov ^ psw_s;
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case 7: return psw_ov ^ psw_s | psw_z;
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}
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return testCondition(condition & 7) ^ 1;
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}
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// Check for an exception or interrupt
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private boolean testException() {
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// Check for an interrupt
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if (irq != 0 && (exception | psw_id | psw_ep | psw_np) == 0) {
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int level;
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for (level = 4; level >= 0; level--)
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if ((irq >> level & 1) != 0)
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break;
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exception = 0xFE00 | level << 4;
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}
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// There is no exception
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if (exception == 0)
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return stage == HALT && cycles == 0; // No further processing
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// An exception has occurred
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cycles = 0;
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stage = EXCEPTION;
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return false;
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}
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// Perform a bus write
|
|
private boolean write(int address, int type, int value) {
|
|
|
|
// Prepare the operation
|
|
access.address = address;
|
|
access.fetch = -1;
|
|
access.type = type;
|
|
access.value = value;
|
|
|
|
// Check for breakpoints
|
|
if (vue.onBreakpoint(Breakpoint.WRITE))
|
|
return true;
|
|
|
|
// Perform the operation
|
|
if (access.type != Vue.CANCEL)
|
|
vue.write(access.address, access.type, access.value);
|
|
return false;
|
|
}
|
|
|
|
|
|
|
|
///////////////////////////////////////////////////////////////////////////
|
|
// Instruction Helpers //
|
|
///////////////////////////////////////////////////////////////////////////
|
|
|
|
// Integer addition
|
|
private int add(int left, int right) {
|
|
int result = left + right;
|
|
psw_cy = Integer.compareUnsigned(result, left) < 0 ? 1 : 0;
|
|
psw_s = result >>> 31;
|
|
psw_ov = (~(left ^ right) & (left ^ result)) >>> 31;
|
|
psw_z = result == 0 ? 1 : 0;
|
|
return result;
|
|
}
|
|
|
|
// Bitwise operation
|
|
private void bitwise(int result) {
|
|
program[inst.reg2] = result;
|
|
psw_ov = 0;
|
|
psw_s = result >>> 31;
|
|
psw_z = result == 0 ? 1 : 0;
|
|
}
|
|
|
|
// Convert a floating short to word
|
|
private void floatConvert(boolean round) {
|
|
|
|
// Reserved operand
|
|
if (floatReserved(false))
|
|
return;
|
|
|
|
// Determine the value to convert
|
|
float value = Float.intBitsToFloat(program[inst.reg1]);
|
|
value = (float) (round ? Math.round(value) :
|
|
value < 0 ? Math.ceil(value) : Math.floor(value));
|
|
|
|
// Invalid operation
|
|
if (value > 0x7FFFFFFF || value < 0x80000000) {
|
|
exception = 0xFF70;
|
|
return;
|
|
}
|
|
|
|
// Common processing
|
|
int result = (int) value;
|
|
if (result != value) // Precision degradation
|
|
psw_fpr = 1;
|
|
program[inst.reg2] = result;
|
|
psw_ov = 0;
|
|
psw_s = result >>> 31;
|
|
psw_z = result == 0 ? 1 : 0;
|
|
}
|
|
|
|
// Determine whether the floating-point operands are reserved values
|
|
private boolean floatReserved(boolean left) {
|
|
for (int x = left ? 0 : 1; x < 2; x++) {
|
|
int operand = program[x == 0 ? inst.reg2 : inst.reg1];
|
|
int exponent = operand & 0x7F800000;
|
|
|
|
// Check for a reserved operand
|
|
if (!(
|
|
exponent == 0x7F800000 || // Indefinite
|
|
exponent == 0 && (operand & 0x007FFFFF) != 0 // Denormal
|
|
)) continue;
|
|
|
|
// The value is a reserved operand
|
|
exception = 0xFF60;
|
|
psw_fro = 1;
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
// Floating-point result
|
|
private void floatResult(boolean compare, double full) {
|
|
|
|
// Overflow
|
|
if (full > Float.MAX_VALUE || full < -Float.MAX_VALUE) {
|
|
exception = 0xFF64;
|
|
psw_fov = 1;
|
|
return;
|
|
}
|
|
|
|
// Process the result
|
|
float result = (float) full;
|
|
int bits = Float.floatToRawIntBits(result);
|
|
|
|
// Underflow
|
|
if ((bits & 0x7F800000) == 0 && (bits & 0x007FFFFF) != 0) {
|
|
bits = 0;
|
|
result = 0;
|
|
psw_fud = 1;
|
|
}
|
|
|
|
// Operations other than compare
|
|
if (!compare) {
|
|
program[inst.reg2] = bits;
|
|
if (result != full) // Precision degradation
|
|
psw_fpr = 1;
|
|
}
|
|
|
|
// Common processing
|
|
psw_cy = psw_s = bits >>> 31;
|
|
psw_ov = 0;
|
|
psw_z = bits == 0 ? 1 : 0;
|
|
}
|
|
|
|
// Proxy for IN and LD
|
|
private void IN_LD(int type) {
|
|
if (!read(program[inst.reg1] + inst.disp, type, -1))
|
|
program[inst.reg2] = access.value;
|
|
}
|
|
|
|
// Transfer program to another address
|
|
private void jump(int address) {
|
|
if (address != pc) {
|
|
int level = psw_np != 0 ? 2 : psw_ep;
|
|
jumpFrom[level] = pc;
|
|
jumpTo [level] = address;
|
|
}
|
|
pc = address - inst.size;
|
|
}
|
|
|
|
// Proxy for OUT and ST
|
|
private void OUT_ST(int type) {
|
|
write(program[inst.reg1] + inst.disp, type, program[inst.reg2]);
|
|
}
|
|
|
|
// Arithmetic shift right
|
|
private void shiftArithmetic(int value, int bits) {
|
|
bits &= 31;
|
|
psw_cy = bits == 0 ? 0 : value >> bits - 1 & 1;
|
|
bitwise(value >> bits);
|
|
}
|
|
|
|
// Logical shift left
|
|
private void shiftLeft(int value, int bits) {
|
|
bits &= 31;
|
|
psw_cy = bits == 0 ? 0 : value >> 32 - bits & 1;
|
|
bitwise(value << bits);
|
|
}
|
|
|
|
// Logical shift right
|
|
private void shiftRight(int value, int bits) {
|
|
bits &= 31;
|
|
psw_cy = bits == 0 ? 0 : value >> bits - 1 & 1;
|
|
bitwise(value >>> bits);
|
|
}
|
|
|
|
// Integer subtraction
|
|
private int subtract(int left, int right) {
|
|
int result = left - right;
|
|
psw_cy = Integer.compareUnsigned(result, left) > 0 ? 1 : 0;
|
|
psw_s = result >>> 31;
|
|
psw_ov = ((left ^ right) & (left ^ result)) >>> 31;
|
|
psw_z = result == 0 ? 1 : 0;
|
|
return result;
|
|
}
|
|
|
|
|
|
|
|
///////////////////////////////////////////////////////////////////////////
|
|
// Instruction Methods //
|
|
///////////////////////////////////////////////////////////////////////////
|
|
|
|
// Add Immediate
|
|
private void ADD_IMM() {
|
|
program[inst.reg2] = add(program[inst.reg2], inst.imm);
|
|
}
|
|
|
|
// Add Register
|
|
private void ADD_REG() {
|
|
program[inst.reg2] = add(program[inst.reg2], program[inst.reg1]);
|
|
}
|
|
|
|
// Add Floating Short
|
|
private void ADDF_S() {
|
|
if (!floatReserved(true)) floatResult(false,
|
|
(double) Float.intBitsToFloat(program[inst.reg2]) +
|
|
(double) Float.intBitsToFloat(program[inst.reg1]));
|
|
}
|
|
|
|
// Add Immediate
|
|
private void ADDI() {
|
|
program[inst.reg2] = add(program[inst.reg1], inst.imm);
|
|
}
|
|
|
|
// And
|
|
private void AND() {
|
|
bitwise(program[inst.reg2] & program[inst.reg1]);
|
|
}
|
|
|
|
// And Immediate
|
|
private void ANDI() {
|
|
bitwise(program[inst.reg1] & inst.imm);
|
|
}
|
|
|
|
// Branch on Condition
|
|
private void BCOND() {
|
|
if (testCondition(inst.cond) == 0)
|
|
return;
|
|
cycles = 2;
|
|
jump(pc + inst.disp);
|
|
}
|
|
|
|
// Compare and Exchange Interlocked
|
|
private void CAXI() {
|
|
int address = program[inst.reg1] + inst.disp;
|
|
int left = program[inst.reg2];
|
|
|
|
// Retrieve the lock word
|
|
if (read(address, Vue.S32, -1))
|
|
return;
|
|
int lock = access.value;
|
|
|
|
// Compare and exchange
|
|
if (lock == left)
|
|
access.value = program[30];
|
|
if (write(address, Vue.S32, access.value))
|
|
return;
|
|
|
|
// Update CPU state
|
|
subtract(left, lock);
|
|
program[inst.reg2] = lock;
|
|
}
|
|
|
|
// Clear Interrupt Disable Flag
|
|
private void CLI() {
|
|
psw_id = 0;
|
|
}
|
|
|
|
// Compare Immediate
|
|
private void CMP_IMM() {
|
|
subtract(program[inst.reg2], inst.imm);
|
|
}
|
|
|
|
// Compare Register
|
|
private void CMP_REG() {
|
|
subtract(program[inst.reg2], program[inst.reg1]);
|
|
}
|
|
|
|
// Compare Floating Short
|
|
private void CMPF_S() {
|
|
if (!floatReserved(true)) floatResult(true,
|
|
(double) Float.intBitsToFloat(program[inst.reg2]) -
|
|
(double) Float.intBitsToFloat(program[inst.reg1]));
|
|
}
|
|
|
|
// Convert Short Floating to Word
|
|
private void CVT_SW() {
|
|
floatConvert(true);
|
|
}
|
|
|
|
// Convert Word Integer to Short
|
|
private void CVT_WS() {
|
|
int bits = program[inst.reg1];
|
|
float result = (float) bits;
|
|
program[inst.reg2] = Float.floatToRawIntBits(result);
|
|
if (result != bits) // Precision degradation
|
|
psw_fpr = 1;
|
|
psw_cy = psw_s = bits >>> 31;
|
|
psw_ov = 0;
|
|
psw_z = bits == 0 ? 1 : 0;
|
|
}
|
|
|
|
// Divide
|
|
private void DIV() {
|
|
int left = program[inst.reg2];
|
|
int right = program[inst.reg1];
|
|
|
|
// Zero division
|
|
if (right == 0) {
|
|
exception = 0xFF80;
|
|
return;
|
|
}
|
|
|
|
// Special case
|
|
if (left == 0x80000000 && right == 0xFFFFFFFF) {
|
|
program[30] = 0;
|
|
program[inst.reg2] = 0x80000000;
|
|
psw_ov = 1;
|
|
psw_s = 1;
|
|
psw_z = 0;
|
|
return;
|
|
}
|
|
|
|
// Regular case
|
|
int result = left / right;
|
|
program[30] = left % right;
|
|
program[inst.reg2] = result;
|
|
psw_ov = 0;
|
|
psw_s = result >>> 31;
|
|
psw_z = result == 0 ? 1 : 0;
|
|
}
|
|
|
|
// Divide Floating Short
|
|
private void DIVF_S() {
|
|
int left = program[inst.reg2];
|
|
int right = program[inst.reg1];
|
|
|
|
// Reserved operand
|
|
if (floatReserved(true))
|
|
return;
|
|
|
|
// An exception has occurred
|
|
if (right == 0) {
|
|
exception = left == 0 ? 0xFF70 : 0xFF68;
|
|
return;
|
|
}
|
|
|
|
// Perform the operation
|
|
floatResult(false,
|
|
(double) Float.intBitsToFloat(left) /
|
|
(double) Float.intBitsToFloat(right));
|
|
}
|
|
|
|
// Divide Unsigned
|
|
private void DIVU() {
|
|
long left = program[inst.reg2] & 0xFFFFFFFFL;
|
|
long right = program[inst.reg1] & 0xFFFFFFFFL;
|
|
|
|
// Zero division
|
|
if (right == 0) {
|
|
exception = 0xFF80;
|
|
return;
|
|
}
|
|
|
|
// Regular case
|
|
int result = (int) (left / right);
|
|
program[30] = (int) (left % right);
|
|
program[inst.reg2] = result;
|
|
psw_ov = 0;
|
|
psw_s = result >>> 31;
|
|
psw_z = result == 0 ? 1 : 0;
|
|
}
|
|
|
|
// Halt
|
|
private void HALT() {
|
|
stage = HALT;
|
|
inst.size = 0;
|
|
}
|
|
|
|
// Input Byte from Port
|
|
private void IN_B() {
|
|
IN_LD(Vue.U8);
|
|
}
|
|
|
|
// Input Halfword from Port
|
|
private void IN_H() {
|
|
IN_LD(Vue.U16);
|
|
}
|
|
|
|
// Input Word from Port
|
|
private void IN_W() {
|
|
IN_LD(Vue.S32);
|
|
}
|
|
|
|
// Jump and Link
|
|
private void JAL() {
|
|
program[31] = pc + 4;
|
|
jump(pc + inst.disp);
|
|
}
|
|
|
|
// Jump Register
|
|
private void JMP() {
|
|
jump(program[inst.reg1]);
|
|
}
|
|
|
|
// Jump Relative
|
|
private void JR() {
|
|
jump(pc + inst.disp);
|
|
}
|
|
|
|
// Load Byte
|
|
private void LD_B() {
|
|
IN_LD(Vue.S8);
|
|
}
|
|
|
|
// Load Halfword
|
|
private void LD_H() {
|
|
IN_LD(Vue.S16);
|
|
}
|
|
|
|
// Load Word
|
|
private void LD_W() {
|
|
IN_LD(Vue.S32);
|
|
}
|
|
|
|
// Load to System Register
|
|
private void LDSR() {
|
|
setSystemRegister(inst.imm & 31, program[inst.reg2], false);
|
|
}
|
|
|
|
// Move Immediate
|
|
private void MOV_IMM() {
|
|
program[inst.reg2] = inst.imm;
|
|
}
|
|
|
|
// Move Register
|
|
private void MOV_REG() {
|
|
program[inst.reg2] = program[inst.reg1];
|
|
}
|
|
|
|
// Add
|
|
private void MOVEA() {
|
|
program[inst.reg2] = program[inst.reg1] + inst.imm;
|
|
}
|
|
|
|
// Add
|
|
private void MOVHI() {
|
|
program[inst.reg2] = program[inst.reg1] + (inst.imm << 16);
|
|
}
|
|
|
|
// Multiply Halfword
|
|
private void MPYHW() {
|
|
program[inst.reg2] *= program[inst.reg1] << 15 >> 15;
|
|
}
|
|
|
|
// Multiply
|
|
private void MUL() {
|
|
long full = (long) program[inst.reg2] * (long) program[inst.reg1];
|
|
int result = (int) full;
|
|
program[30] = (int) (full >> 32);
|
|
program[inst.reg2] = result;
|
|
psw_ov = (long) result != full ? 1 : 0;
|
|
psw_s = result >>> 31;
|
|
psw_z = result == 0 ? 1 : 0;
|
|
}
|
|
|
|
// Multiply Floating Short
|
|
private void MULF_S() {
|
|
if (!floatReserved(true)) floatResult(false,
|
|
(double) Float.intBitsToFloat(program[inst.reg2]) *
|
|
(double) Float.intBitsToFloat(program[inst.reg1]));
|
|
}
|
|
|
|
// Multiply Unsigned
|
|
private void MULU() {
|
|
long full = (program[inst.reg2] & 0xFFFFFFFFL) *
|
|
(program[inst.reg1] & 0xFFFFFFFFL);
|
|
int result = (int) full;
|
|
program[30] = (int) (full >> 32);
|
|
program[inst.reg2] = result;
|
|
psw_ov = full > 0xFFFFFFFFL ? 1 : 0;
|
|
psw_s = result >>> 31;
|
|
psw_z = result == 0 ? 1 : 0;
|
|
}
|
|
|
|
// Not
|
|
private void NOT() {
|
|
bitwise(~program[inst.reg1]);
|
|
}
|
|
|
|
// Or
|
|
private void OR() {
|
|
bitwise(program[inst.reg2] | program[inst.reg1]);
|
|
}
|
|
|
|
// Or Immediate
|
|
private void ORI() {
|
|
bitwise(program[inst.reg1] | inst.imm);
|
|
}
|
|
|
|
// Output Byte to Port
|
|
private void OUT_B() {
|
|
OUT_ST(Vue.U8);
|
|
}
|
|
|
|
// Output Halfword to Port
|
|
private void OUT_H() {
|
|
OUT_ST(Vue.U16);
|
|
}
|
|
|
|
// Output Word to Port
|
|
private void OUT_W() {
|
|
OUT_ST(Vue.S32);
|
|
}
|
|
|
|
// Return from Trap or Interrupt
|
|
private void RETI() {
|
|
if (psw_np == 1) {
|
|
pc = fepc;
|
|
setSystemRegister(Vue.PSW, fepsw, false);
|
|
} else {
|
|
pc = eipc;
|
|
setSystemRegister(Vue.PSW, eipsw, false);
|
|
}
|
|
}
|
|
|
|
// Reverse Bits in Word
|
|
private void REV() {
|
|
int value = program[inst.reg1];
|
|
value = value >> 16 & 0x0000FFFF | value << 16;
|
|
value = value >> 8 & 0x00FF00FF | value << 8 & 0xFF00FF00;
|
|
value = value >> 4 & 0x0F0F0F0F | value << 4 & 0xF0F0F0F0;
|
|
value = value >> 2 & 0x33333333 | value << 2 & 0xCCCCCCCC;
|
|
value = value >> 1 & 0x55555555 | value << 1 & 0xAAAAAAAA;
|
|
program[inst.reg2] = value;
|
|
}
|
|
|
|
// Shift Arithmetic Right by Immediate
|
|
private void SAR_IMM() {
|
|
shiftArithmetic(program[inst.reg2], inst.imm);
|
|
}
|
|
|
|
// Shift Arithmetic Right by Register
|
|
private void SAR_REG() {
|
|
shiftArithmetic(program[inst.reg2], program[inst.reg1]);
|
|
}
|
|
|
|
// Set Interrupt Disable Flag
|
|
private void SEI() {
|
|
psw_id = 1;
|
|
}
|
|
|
|
// Set Flag Condition
|
|
private void SETF() {
|
|
program[inst.reg2] = testCondition(inst.imm & 15);
|
|
}
|
|
|
|
// Shift Logical Left by Immediate
|
|
private void SHL_IMM() {
|
|
shiftLeft(program[inst.reg2], inst.imm);
|
|
}
|
|
|
|
// Shift Logical Left by Register
|
|
private void SHL_REG() {
|
|
shiftLeft(program[inst.reg2], program[inst.reg1]);
|
|
}
|
|
|
|
// Shift Logical Right by Immediate
|
|
private void SHR_IMM() {
|
|
shiftRight(program[inst.reg2], inst.imm);
|
|
}
|
|
|
|
// Shift Logical Right by Register
|
|
private void SHR_REG() {
|
|
shiftRight(program[inst.reg2], program[inst.reg1]);
|
|
}
|
|
|
|
// Store Byte
|
|
private void ST_B() {
|
|
OUT_ST(Vue.S8);
|
|
}
|
|
|
|
// Store Halfword
|
|
private void ST_H() {
|
|
OUT_ST(Vue.S16);
|
|
}
|
|
|
|
// Store Word
|
|
private void ST_W() {
|
|
OUT_ST(Vue.S32);
|
|
}
|
|
|
|
// Store Contents of System Register
|
|
private void STSR() {
|
|
program[inst.reg2] = getSystemRegister(inst.imm & 31);
|
|
}
|
|
|
|
// Subtract
|
|
private void SUB() {
|
|
program[inst.reg2] = subtract(program[inst.reg2], program[inst.reg1]);
|
|
}
|
|
|
|
// Subtract Floating Short
|
|
private void SUBF_S() {
|
|
if (!floatReserved(true)) floatResult(false,
|
|
(double) Float.intBitsToFloat(program[inst.reg2]) -
|
|
(double) Float.intBitsToFloat(program[inst.reg1]));
|
|
}
|
|
|
|
// Trap
|
|
private void TRAP() {
|
|
exception = 0xFFA0 | inst.imm & 31;
|
|
pc += 2;
|
|
}
|
|
|
|
// Truncate Short Floating to Word
|
|
private void TRNC_SW() {
|
|
floatConvert(false);
|
|
}
|
|
|
|
// Exchange Byte
|
|
private void XB() {
|
|
int value = program[inst.reg2];
|
|
program[inst.reg2] = value & 0xFFFF0000 |
|
|
value >> 8 & 0xFF | (value & 0xFF) << 8;
|
|
}
|
|
|
|
// Exchange Halfword
|
|
private void XH() {
|
|
int value = program[inst.reg2];
|
|
program[inst.reg2] = value >> 16 & 0xFFFF | value << 16;
|
|
}
|
|
|
|
// Exclusive Or
|
|
private void XOR() {
|
|
bitwise(program[inst.reg2] ^ program[inst.reg1]);
|
|
}
|
|
|
|
// Exclusive Or Immediate
|
|
private void XORI() {
|
|
bitwise(program[inst.reg1] ^ inst.imm);
|
|
}
|
|
|
|
}
|