227 lines
7.6 KiB
Java
227 lines
7.6 KiB
Java
package vue;
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// Java imports
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import java.util.*;
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// CPU state
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class CPU {
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// Private fields
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private JavaVUE vue; // Emulation state
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// Package fields
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int cycles; // Cycles until next stage
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int fetch; // Fetch unit index
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int[] jumpFrom; // Source PCs of most recent jumps
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int[] jumpTo; // Destination PCs of most recent jumps
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int stage; // Current processing stage
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// Program registers
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int[] program;
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// System registers
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int adtre; // Address Trap Register for Execution
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int eipc; // Exception/interrupt PC
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int eipsw; // Exception/interrupt PSW
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int fepc; // Duplexed exception PC
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int fepsw; // Duplexed exception PSW
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int pc; // Program Counter
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int sr29; // System register 29
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int sr31; // System register 31
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// Program Status Word
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int psw_ae; // Address Trap Enable
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int psw_ep; // Exception Pending
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int psw_id; // Interrupt Disable
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int psw_cy; // Carry
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int psw_fiv; // Floating Reserved Operand
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int psw_fov; // Floating Overflow
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int psw_fpr; // Floating Precision
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int psw_fro; // Floating Reserved Operand
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int psw_fud; // Floating Underflow
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int psw_fzd; // Floating Zero Divide
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int psw_i; // Interrupt Level
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int psw_np; // NMI Pending
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int psw_ov; // Overflow
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int psw_s; // Sign
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int psw_z; // Zero
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// Cache Control Word
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int chcw_cec; // Clear Entry Count
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int chcw_cen; // Clear Entry Number
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int chcw_icc; // Instruction Cache Clear
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int chcw_icd; // Instruction Cache Dump
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int chcw_ice; // Instruction Cache Enable
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int chcw_icr; // Instruction Cache Restore
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int chcw_sa; // Spill-Out Base Address
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// Exception Cause Register
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int ecr_eicc; // Exception/Interrupt Cause Code
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int ecr_fecc; // Fatal Error Cause Code
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///////////////////////////////////////////////////////////////////////////
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// Constants //
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///////////////////////////////////////////////////////////////////////////
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// Stages
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static final int FETCH = 0;
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static final int EXECUTE = 1;
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static final int HALT = 2;
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static final int EXCEPTION = 3;
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static final int FATAL = 4;
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static final int CLEAR = 5;
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static final int DUMP = 6;
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static final int RESTORE = 7;
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///////////////////////////////////////////////////////////////////////////
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// Constructors //
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///////////////////////////////////////////////////////////////////////////
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// Default constructor
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CPU(JavaVUE vue) {
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jumpFrom = new int[3];
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jumpTo = new int[3];
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program = new int[32];
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this.vue = vue;
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}
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///////////////////////////////////////////////////////////////////////////
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// Package Methods //
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///////////////////////////////////////////////////////////////////////////
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// Read a system register
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int getSystemRegister(int index) {
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switch (index) {
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case VUE.ADTRE: return adtre;
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case VUE.EIPC : return eipc;
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case VUE.EIPSW: return eipsw;
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case VUE.FEPC : return fepc;
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case VUE.FEPSW: return fepsw;
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case VUE.ECR : return ecr_fecc << 16 | ecr_eicc;
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case VUE.PIR : return 0x00005346;
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case VUE.TKCW : return 0x000000E0;
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case VUE.CHCW : return chcw_ice << 1;
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case 29 : return sr29;
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case 30 : return 0x00000004;
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case 31 : return sr31;
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case VUE.PSW : return
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psw_i << 16 | psw_fro << 9 | psw_fpr << 4 |
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psw_np << 15 | psw_fiv << 8 | psw_cy << 3 |
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psw_ep << 14 | psw_fzd << 7 | psw_ov << 2 |
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psw_ae << 13 | psw_fov << 6 | psw_s << 1 |
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psw_id << 12 | psw_fud << 5 | psw_z
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;
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// Remaining cases to encourage tableswitch
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case 8: case 9: case 10: case 11: case 12: case 13: case 14:
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case 15: case 16: case 17: case 18: case 19: case 20: case 21:
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return 0;
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}
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return 1; // Unreachable
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}
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// System reset
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void reset() {
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// Configure instance fields
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cycles = 0; // Duration of first fetch
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fetch = 0;
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stage = FETCH;
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// Clear all registers (hardware only sets ECR, PC and PSW)
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for (int x = 0; x < 32; x++) {
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program[x] = 0;
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setSystemRegister(x, 0, true);
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}
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// Configure jump histories
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Arrays.fill(jumpFrom, 0xFFFFFFF0);
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Arrays.fill(jumpTo , 0xFFFFFFF0);
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// Configure registers
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ecr_eicc = 0xFFF0;
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pc = 0xFFFFFFF0;
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psw_np = 1;
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}
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// Write a system register
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int setSystemRegister(int index, int value, boolean debug) {
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switch (index) {
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case VUE.ADTRE: return adtre = value & 0xFFFFFFFE;
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case VUE.EIPC : return eipc = value & 0xFFFFFFFE;
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case VUE.EIPSW: return eipsw = value & 0x000FF3FF;
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case VUE.FEPC : return fepc = value & 0xFFFFFFFE;
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case VUE.FEPSW: return fepsw = value & 0x000FF3FF;
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case 29 : return sr29 = value;
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case 31 : return sr31 = debug || value >= 0 ? value : -value;
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case VUE.ECR:
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if (debug) {
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ecr_fecc = value >> 16 & 0xFFFF;
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ecr_eicc = value & 0xFFFF;
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}
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return ecr_fecc << 16 | ecr_eicc;
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case VUE.CHCW :
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chcw_cen = value >> 20 & 0x00000FFF;
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chcw_cec = value >> 8 & 0x00000FFF;
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chcw_sa = value >> 8 & 0x00FFFFFF;
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chcw_icr = value >> 5 & 1;
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chcw_icd = value >> 4 & 1;
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chcw_ice = value >> 1 & 1;
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chcw_icc = value & 1;
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// Only one of ICC, ICD or ICR is set
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value &= 0x00000031;
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if ((value & value - 1) == 0) {
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// Clear
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// Dump
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// Restore
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}
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return chcw_ice << 1;
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case VUE.PSW :
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psw_i = value >> 16 & 15; psw_fov = value >> 6 & 1;
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psw_np = value >> 15 & 1; psw_fud = value >> 5 & 1;
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psw_ep = value >> 14 & 1; psw_fpr = value >> 4 & 1;
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psw_ae = value >> 13 & 1; psw_cy = value >> 3 & 1;
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psw_id = value >> 12 & 1; psw_ov = value >> 2 & 1;
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psw_fro = value >> 9 & 1; psw_s = value >> 1 & 1;
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psw_fiv = value >> 8 & 1; psw_z = value & 1;
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psw_fzd = value >> 7 & 1;
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return value & 0x000FF3FF;
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// Remaining cases to encourage tableswitch
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case 6: case 7: case 8: case 9: case 10: case 11: case 12:
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case 13: case 14: case 15: case 16: case 17: case 18: case 19:
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case 20: case 21: case 22: case 23: case 26: case 27: case 28:
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case 30:
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return 0;
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}
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return 1; // Unreachable
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}
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// Test a condition
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int test(int condition) {
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switch (condition) {
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case 0: return psw_ov;
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case 1: return psw_cy;
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case 2: return psw_z;
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case 3: return psw_cy | psw_z;
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case 4: return psw_s;
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case 5: return 1;
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case 6: return psw_ov | psw_s;
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case 7: return psw_ov ^ psw_s | psw_z;
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}
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return test(condition & 7) ^ 1;
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}
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}
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