2024-10-14 20:07:00 +00:00
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#ifndef VBAPI
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#define VBAPI
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#endif
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#include <float.h>
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#include <vb.h>
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/*********************************** Types ***********************************/
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/* Simulation state */
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struct VB {
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/* Game Pak */
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struct {
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uint8_t *ram; /* Save RAM */
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uint8_t *rom; /* Program ROM */
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uint32_t ramMask; /* Size of SRAM - 1 */
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uint32_t romMask; /* Size of ROM - 1 */
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} cart;
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/* CPU */
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struct {
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/* Cache Control Word */
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struct {
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uint8_t ice; /* Instruction Cache Enable */
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} chcw;
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/* Exception Cause Register */
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struct {
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uint16_t eicc; /* Exception/Interrupt Cause Code */
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uint16_t fecc; /* Fatal Error Cause Code */
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} ecr;
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/* Program Status Word */
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struct {
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uint8_t ae; /* Address Trap Enable */
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uint8_t cy; /* Carry */
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uint8_t ep; /* Exception Pending */
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uint8_t fiv; /* Floating Invalid */
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uint8_t fov; /* Floating Overflow */
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uint8_t fpr; /* Floading Precision */
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uint8_t fro; /* Floating Reserved Operand */
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uint8_t fud; /* Floading Underflow */
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uint8_t fzd; /* Floating Zero Divide */
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uint8_t i; /* Interrupt Level */
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uint8_t id; /* Interrupt Disable */
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uint8_t np; /* NMI Pending */
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uint8_t ov; /* Overflow */
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uint8_t s; /* Sign */
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uint8_t z; /* Zero */
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} psw;
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/* Other registers */
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uint32_t adtre; /* Address Trap Register for Execution */
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uint32_t eipc; /* Exception/Interrupt PC */
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uint32_t eipsw; /* Exception/Interrupt PSW */
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uint32_t fepc; /* Fatal Error PC */
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uint32_t fepsw; /* Fatal Error PSW */
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uint32_t pc; /* Program Counter */
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int32_t program[32]; /* Program registers */
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uint32_t sr29; /* System register 29 */
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uint32_t sr31; /* System register 31 */
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/* Working data */
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union {
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struct {
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uint32_t dest;
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uint64_t src;
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} bs; /* Arithmetic bit strings */
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struct {
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uint32_t address;
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int32_t value;
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} data; /* Data accesses */
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} aux;
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/* Other state */
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uint32_t clocks; /* Master clocks to wait */
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uint16_t code[2]; /* Instruction code units */
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uint16_t exception; /* Exception cause code */
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int halt; /* CPU is halting */
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uint16_t irq; /* Interrupt request lines */
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int length; /* Instruction code length */
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uint32_t nextPC; /* Address of next instruction */
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int operation; /* Current operation ID */
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int step; /* Operation sub-task ID */
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} cpu;
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2024-10-15 19:11:29 +00:00
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/* VIP */
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struct {
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/* CTA */
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struct {
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uint8_t cta_l; /* Left column table index */
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uint8_t cta_r; /* Right column table index */
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} cta;
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2024-10-16 21:15:39 +00:00
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/* Display processor */
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struct {
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/* Hardware state */
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uint8_t disp; /* Display enabled */
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uint8_t fclk; /* Frame clock signal high */
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uint8_t l0bsy; /* Displaying left frame buffer 0 */
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uint8_t l1bsy; /* Displaying left frame buffer 1 */
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uint8_t lock; /* Lock CTA */
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uint8_t r0bsy; /* Displaying right frame buffer 0 */
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uint8_t r1bsy; /* Displaying right frame buffer 1*/
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uint8_t re; /* Memory refresh enabled */
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uint8_t scanrdy; /* Mirrors are stable */
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uint8_t synce; /* Servo enabled */
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/* Simulation state */
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uint8_t brt[4]; /* Precomputed brightness */
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int buffer; /* Index of frame buffer to display */
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uint32_t clocks; /* Master clocks to wait */
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int column; /* Index of column to display */
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uint32_t cta; /* Column table pointer in memory */
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uint32_t fbDest; /* Output frame pixel address */
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uint32_t fbSrc; /* Source frame buffer address */
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int32_t repeat; /* Current column table repeat value */
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int step; /* Processing phase */
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} dp;
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/* Pixel processor */
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struct {
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uint8_t f0bsy; /* Drawing into frame buffer 0 */
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uint8_t f1bsy; /* Drawing into frame buffer 1 */
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uint8_t overtime; /* Drawing extends into display interval */
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uint8_t sbcmp; /* Vertical output position compare */
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uint8_t sbcount; /* Current vertical output position */
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uint8_t sbout; /* Drawing specified vertical output position */
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uint8_t xpen; /* Drawing enabled */
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} xp;
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/* Control state */
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uint8_t bkcol; /* Backdrop color */
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uint8_t brtRest[4]; /* Brightness and REST */
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uint8_t frmcyc; /* Game frame control */
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uint8_t gplt[4][4]; /* Background palettes */
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uint16_t intenb; /* Interrupts enabled */
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uint16_t intpnd; /* Interrupts pending */
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uint8_t jplt[4][4]; /* Object palettes */
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uint16_t spt[4]; /* Object control */
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/* Output frame buffers [buffer index][0=left, 1=right][pixel index] */
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uint8_t frames[2][2][384 * 224];
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/* Other state */
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uint8_t ram[0x40000]; /* Video memory */
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2024-10-15 19:11:29 +00:00
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} vip;
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/* Other state */
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uint8_t wram[0x10000]; /* System RAM */
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/* Application data */
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vbOnException onException; /* CPU exception */
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vbOnExecute onExecute; /* CPU instruction execute */
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vbOnFetch onFetch; /* CPU instruction fetch */
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vbOnFrame onFrame; /* VIP frame ready */
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vbOnRead onRead; /* CPU instruction read */
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vbOnWrite onWrite; /* CPU instruction write */
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void *tag; /* User data */
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};
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/***************************** Library Functions *****************************/
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/* Sign-extend an integer of variable width */
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static int32_t SignExtend(int32_t value, int32_t bits) {
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#ifndef VB_SIGNED_PROPAGATE
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value &= ~((uint32_t) 0xFFFFFFFF << bits);
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bits = (int32_t) 1 << (bits - (int32_t) 1);
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return (value ^ bits) - bits;
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#else
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return value << (32 - bits) >> (32 - bits);
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#endif
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}
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/******************************** Sub-Modules ********************************/
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#include "bus.c"
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#include "cpu.c"
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#include "vip.c"
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2024-10-14 20:07:00 +00:00
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/***************************** Library Functions *****************************/
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/* Process a simulation for a given number of clocks */
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static int sysEmulate(VB *sim, uint32_t clocks) {
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return
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cpuEmulate(sim, clocks) |
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vipEmulate(sim, clocks)
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;
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}
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/* Determine how many clocks are guaranteed to process */
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static uint32_t sysUntil(VB *sim, uint32_t clocks) {
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clocks = cpuUntil(sim, clocks);
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clocks = vipUntil(sim, clocks);
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return clocks;
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}
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/******************************* API Commands ********************************/
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/* Process one simulation */
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VBAPI int vbEmulate(VB *sim, uint32_t *clocks) {
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int brk; /* A callback requested a break */
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uint32_t until; /* Clocks guaranteed to process */
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while (*clocks != 0) {
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until = sysUntil(sim, *clocks);
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brk = sysEmulate(sim, until);
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*clocks -= until;
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if (brk)
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return brk; /* TODO: return 1 */
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}
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return 0;
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}
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/* Process multiple simulations */
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VBAPI int vbEmulateEx(VB **sims, int count, uint32_t *clocks) {
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int brk; /* A callback requested a break */
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uint32_t until; /* Clocks guaranteed to process */
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int x; /* Iterator */
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while (*clocks != 0) {
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until = *clocks;
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for (x = count - 1; x >= 0; x--)
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until = sysUntil(sims[x], until);
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brk = 0;
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for (x = count - 1; x >= 0; x--)
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brk |= sysEmulate(sims[x], until);
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*clocks -= until;
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if (brk)
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return brk; /* TODO: return 1 */
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}
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return 0;
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}
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/* Retrieve the game pack RAM buffer */
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VBAPI void* vbGetCartRAM(VB *sim, uint32_t *size) {
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if (size != NULL)
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*size = sim->cart.ram == NULL ? 0 : sim->cart.ramMask + 1;
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return sim->cart.ram;
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}
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/* Retrieve the game pack ROM buffer */
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VBAPI void* vbGetCartROM(VB *sim, uint32_t *size) {
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if (size != NULL)
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*size = sim->cart.rom == NULL ? 0 : sim->cart.romMask + 1;
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return sim->cart.rom;
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}
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2024-10-16 21:15:39 +00:00
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/* Retrieve the exception callback handler */
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VBAPI vbOnException vbGetExceptionCallback(VB *sim) {
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return sim->onException;
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}
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2024-10-16 21:15:39 +00:00
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/* Retrieve the execute callback handler */
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VBAPI vbOnExecute vbGetExecuteCallback(VB *sim) {
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return sim->onExecute;
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}
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2024-10-16 21:15:39 +00:00
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/* Retrieve the fetch callback handler */
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VBAPI vbOnFetch vbGetFetchCallback(VB *sim) {
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return sim->onFetch;
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}
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2024-10-16 21:15:39 +00:00
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/* Retrieve the frame callback handler */
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VBAPI vbOnFrame vbGetFrameCallback(VB *sim) {
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return sim->onFrame;
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}
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2024-10-14 20:07:00 +00:00
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/* Retrieve the value of the program counter */
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VBAPI uint32_t vbGetProgramCounter(VB *sim) {
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return sim->cpu.pc;
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}
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/* Retrieve the value in a program register */
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VBAPI int32_t vbGetProgramRegister(VB *sim, int index) {
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return index < 1 || index > 31 ? 0 : sim->cpu.program[index];
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}
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/* Retrieve the read callback handler */
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VBAPI vbOnRead vbGetReadCallback(VB *sim) {
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return sim->onRead;
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}
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/* Retrieve the value in a system register */
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VBAPI uint32_t vbGetSystemRegister(VB *sim, int index) {
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return index < 0 || index > 31 ? 0 : cpuGetSystemRegister(sim, index);
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}
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/* Retrieve a simulation's userdata pointer */
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VBAPI void* vbGetUserData(VB *sim) {
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return sim->tag;
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}
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/* Retrieve the write callback handler */
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VBAPI vbOnWrite vbGetWriteCallback(VB *sim) {
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return sim->onWrite;
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}
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/* Initialize a simulation instance */
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VBAPI VB* vbInit(VB *sim) {
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sim->cart.ram = NULL;
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sim->cart.rom = NULL;
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sim->onExecute = NULL;
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sim->onFetch = NULL;
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sim->onFrame = NULL;
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sim->onRead = NULL;
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sim->onWrite = NULL;
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vbReset(sim);
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return sim;
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}
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/* Read a value from the memory bus */
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VBAPI int32_t vbRead(VB *sim, uint32_t address, int type) {
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int32_t value;
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if (type < 0 || type > 4)
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return 0;
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busRead(sim, address, type, &value);
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return value;
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}
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/* Simulate a hardware reset */
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VBAPI VB* vbReset(VB *sim) {
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int x; /* Iterator */
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/* WRAM (the hardware does not do this) */
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for (x = 0; x < 0x10000; x++)
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sim->wram[x] = 0x00;
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/* Components */
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cpuReset(sim);
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vipReset(sim);
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return sim;
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}
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/* Specify a game pak RAM buffer */
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VBAPI int vbSetCartRAM(VB *sim, void *sram, uint32_t size) {
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if (sram != NULL) {
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if (size < 16 || size > 0x1000000 || (size & (size - 1)) != 0)
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return 1;
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sim->cart.ramMask = size - 1;
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}
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sim->cart.ram = sram;
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|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Specify a game pak ROM buffer */
|
|
|
|
VBAPI int vbSetCartROM(VB *sim, void *rom, uint32_t size) {
|
|
|
|
if (rom != NULL) {
|
|
|
|
if (size < 16 || size > 0x1000000 || (size & (size - 1)) != 0)
|
|
|
|
return 1;
|
|
|
|
sim->cart.romMask = size - 1;
|
|
|
|
}
|
|
|
|
sim->cart.rom = rom;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2024-10-16 21:15:39 +00:00
|
|
|
/* Specify a new exception callback handler */
|
2024-10-14 20:07:00 +00:00
|
|
|
VBAPI vbOnException vbSetExceptionCallback(VB *sim, vbOnException callback) {
|
|
|
|
vbOnException prev = sim->onException;
|
|
|
|
sim->onException = callback;
|
|
|
|
return prev;
|
|
|
|
}
|
|
|
|
|
2024-10-16 21:15:39 +00:00
|
|
|
/* Specify a new execute callback handler */
|
2024-10-14 20:07:00 +00:00
|
|
|
VBAPI vbOnExecute vbSetExecuteCallback(VB *sim, vbOnExecute callback) {
|
|
|
|
vbOnExecute prev = sim->onExecute;
|
|
|
|
sim->onExecute = callback;
|
|
|
|
return prev;
|
|
|
|
}
|
|
|
|
|
2024-10-16 21:15:39 +00:00
|
|
|
/* Specify a new fetch callback handler */
|
2024-10-14 20:07:00 +00:00
|
|
|
VBAPI vbOnFetch vbSetFetchCallback(VB *sim, vbOnFetch callback) {
|
|
|
|
vbOnFetch prev = sim->onFetch;
|
|
|
|
sim->onFetch = callback;
|
|
|
|
return prev;
|
|
|
|
}
|
|
|
|
|
2024-10-16 21:15:39 +00:00
|
|
|
/* Specify a new frame callback handler */
|
|
|
|
VBAPI vbOnFrame vbSetFrameCallback(VB *sim, vbOnFrame callback) {
|
|
|
|
vbOnFrame prev = sim->onFrame;
|
|
|
|
sim->onFrame = callback;
|
|
|
|
return prev;
|
|
|
|
}
|
|
|
|
|
2024-10-14 20:07:00 +00:00
|
|
|
/* Specify a new value for the program counter */
|
|
|
|
VBAPI uint32_t vbSetProgramCounter(VB *sim, uint32_t value) {
|
|
|
|
sim->cpu.operation = CPU_FETCH;
|
|
|
|
sim->cpu.pc = sim->cpu.nextPC = value & 0xFFFFFFFE;
|
|
|
|
sim->cpu.step = 0;
|
|
|
|
return sim->cpu.pc;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Specify a new value for a program register */
|
|
|
|
VBAPI int32_t vbSetProgramRegister(VB *sim, int index, int32_t value) {
|
|
|
|
return index < 1 || index > 31 ? 0 : (sim->cpu.program[index] = value);
|
|
|
|
}
|
|
|
|
|
2024-10-16 21:15:39 +00:00
|
|
|
/* Specify a new read callback handler */
|
2024-10-14 20:07:00 +00:00
|
|
|
VBAPI vbOnRead vbSetReadCallback(VB *sim, vbOnRead callback) {
|
|
|
|
vbOnRead prev = sim->onRead;
|
|
|
|
sim->onRead = callback;
|
|
|
|
return prev;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Specify a new value for a system register */
|
|
|
|
VBAPI uint32_t vbSetSystemRegister(VB *sim, int index, uint32_t value) {
|
|
|
|
return index < 0 || index > 31 ? 0 :
|
|
|
|
cpuSetSystemRegister(sim, index, value, 1);
|
|
|
|
}
|
|
|
|
|
2024-10-16 21:15:39 +00:00
|
|
|
/* Specify a new write callback handler */
|
2024-10-14 20:07:00 +00:00
|
|
|
VBAPI vbOnWrite vbSetWriteCallback(VB *sim, vbOnWrite callback) {
|
|
|
|
vbOnWrite prev = sim->onWrite;
|
|
|
|
sim->onWrite = callback;
|
|
|
|
return prev;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Determine the size of a simulation instance */
|
|
|
|
VBAPI size_t vbSizeOf() {
|
|
|
|
return sizeof (VB);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Specify a simulation's userdata pointer */
|
|
|
|
VBAPI void* vbSetUserData(VB *sim, void *tag) {
|
|
|
|
void *prev = sim->tag;
|
|
|
|
sim->tag = tag;
|
|
|
|
return prev;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Write a value to the memory bus */
|
|
|
|
VBAPI int32_t vbWrite(VB *sim, uint32_t address, int type, int32_t value) {
|
|
|
|
if (type < 0 || type > 4)
|
|
|
|
return 0;
|
|
|
|
busWrite(sim, address, type, value, 1);
|
|
|
|
return vbRead(sim, address, type);
|
|
|
|
}
|