416 lines
12 KiB
C
416 lines
12 KiB
C
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/* This file is included into vb.c and cannot be compiled on its own. */
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#ifdef VBAPI
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/***************************** Module Functions ******************************/
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/* Read a palette */
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static int32_t vipReadPalette(uint8_t *entries) {
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return entries[3] << 6 | entries[2] << 4 | entries[1] << 2;
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}
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/* Write a palette */
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static void vipWritePalette(uint8_t *entries, int32_t mask, int32_t value) {
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if (mask & 0x00FF)
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return;
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entries[3] = value >> 6 & 3;
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entries[2] = value >> 4 & 3;
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entries[1] = value >> 2 & 3;
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}
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/* Read a typed value from an I/O register */
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static int32_t vipReadIO(VB *sim, uint32_t address, int type) {
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int mask; /* Byte access mask */
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int32_t value; /* Return value */
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/* Adjustments by type */
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switch (type) {
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case VB_S32: /* Word */
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return vipReadIO(sim, address, VB_U16) |
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(uint32_t) vipReadIO(sim, address + 2, VB_U16) << 16;
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case VB_S8: /* Byte */
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case VB_U8:
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mask = 0x00FF << ((address & 1) << 3);
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break;
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case VB_S16: /* Halfword */
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case VB_U16:
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mask = 0xFFFF;
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}
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/* Access by register */
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switch (address >> 1) {
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case 0x5F800>>1: /* INTPND */
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value = sim->vip.intpnd;
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break;
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case 0x5F802>>1: /* INTENB */
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value = sim->vip.intenb;
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break;
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case 0x5F820>>1: /* DPSTTS */
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value =
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(int32_t) sim->vip.dpctrl.lock << 10 |
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(int32_t) sim->vip.dpctrl.synce << 9 |
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(int32_t) sim->vip.dpctrl.re << 8 |
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(int32_t) sim->vip.dpctrl.fclk << 7 |
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(int32_t) sim->vip.dpctrl.scanrdy << 6 |
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(int32_t) sim->vip.dpctrl.r1bsy << 5 |
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(int32_t) sim->vip.dpctrl.l1bsy << 4 |
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(int32_t) sim->vip.dpctrl.r0bsy << 3 |
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(int32_t) sim->vip.dpctrl.l0bsy << 2 |
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(int32_t) sim->vip.dpctrl.disp << 1
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;
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break;
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case 0x5F824>>1: /* BRTA */
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value = sim->vip.brtRest[0];
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break;
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case 0x5F826>>1: /* BRTB */
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value = sim->vip.brtRest[1];
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break;
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case 0x5F828>>1: /* BRTC */
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value = sim->vip.brtRest[2];
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break;
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case 0x5F82A>>1: /* REST */
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value = sim->vip.brtRest[3];
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break;
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case 0x5F82E>>1: /* FRMCYC */
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value = sim->vip.frmcyc;
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break;
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case 0x5F830>>1: /* CTA */
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value = (int32_t) sim->vip.cta.cta_r << 8 | sim->vip.cta.cta_l;
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break;
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case 0x5F840>>1: /* XPSTTS */
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value =
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(int32_t) sim->vip.xpctrl.sbout << 15 |
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(int32_t) sim->vip.xpctrl.sbcount << 8 |
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(int32_t) sim->vip.xpctrl.overtime << 4 |
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(int32_t) sim->vip.xpctrl.f1bsy << 3 |
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(int32_t) sim->vip.xpctrl.f0bsy << 2 |
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(int32_t) sim->vip.xpctrl.xpen << 1
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;
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break;
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case 0x5F844>>1: /* VER */
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value = 2;
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break;
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case 0x5F848>>1: /* SPT0 */
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value = sim->vip.spt[0];
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break;
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case 0x5F84A>>1: /* SPT1 */
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value = sim->vip.spt[1];
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break;
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case 0x5F84C>>1: /* SPT2 */
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value = sim->vip.spt[2];
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break;
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case 0x5F84E>>1: /* SPT3 */
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value = sim->vip.spt[3];
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break;
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case 0x5F860>>1: /* GPLT0 */
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value = vipReadPalette(sim->vip.gplt[0]);
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break;
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case 0x5F862>>1: /* GPLT1 */
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value = vipReadPalette(sim->vip.gplt[1]);
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break;
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case 0x5F864>>1: /* GPLT2 */
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value = vipReadPalette(sim->vip.gplt[2]);
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break;
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case 0x5F866>>1: /* GPLT3 */
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value = vipReadPalette(sim->vip.gplt[3]);
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break;
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case 0x5F868>>1: /* JPLT0 */
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value = vipReadPalette(sim->vip.jplt[0]);
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break;
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case 0x5F86A>>1: /* JPLT1 */
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value = vipReadPalette(sim->vip.jplt[1]);
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break;
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case 0x5F86C>>1: /* JPLT2 */
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value = vipReadPalette(sim->vip.jplt[2]);
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break;
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case 0x5F86E>>1: /* JPLT3 */
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value = vipReadPalette(sim->vip.jplt[3]);
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break;
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case 0x5F870>>1: /* BKCOL */
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value = sim->vip.bkcol;
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break;
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/* Unmapped */
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default: value = 0;
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}
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/* Select byte bits as necessary */
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return
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mask == 0x00FF ? value & 0x00FF :
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mask == 0xFF00 ? value >> 8 :
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value;
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}
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/* Write a typed value to an I/O register */
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static void vipWriteIO(
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VB *sim, uint32_t address, int type, int32_t value, int debug) {
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int mask; /* Byte access mask */
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/* Adjustments by type */
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switch (type) {
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case VB_S32: /* Word */
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vipWriteIO(sim, address , VB_U16, value , debug);
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vipWriteIO(sim, address + 2, VB_U16, value >> 16, debug);
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return;
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case VB_S8: /* Byte */
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case VB_U8:
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/* Select which half of the register to access */
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if (debug) {
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mask = (address & 1) << 3;
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value = (value & 0x00FF) << mask;
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mask = 0xFF00 >> mask;
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break;
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}
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/* Convert to a halfword access */
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if ((address & 1) != 0)
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value = (value & 0x00FF) << 8;
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/* Fallthrough */
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default: /* Halfword */
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mask = 0x0000;
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}
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/* Access by register */
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switch (address >> 1) {
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case 0x5F802>>1: /* INTENB */
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sim->vip.intenb = (sim->vip.intenb & mask) | (value & 0xE01F);
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break;
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case 0x5F804>>1: /* INTCLR */
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sim->vip.intpnd &= ~value;
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if (sim->vip.intpnd == 0)
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sim->cpu.irq &= ~0x0010;
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break;
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case 0x5F822>>1: /* DPCTRL */
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if ((mask & 0xFF00) == 0) {
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sim->vip.dpctrl.lock = value >> 10 & 1;
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sim->vip.dpctrl.synce = value >> 9 & 1;
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sim->vip.dpctrl.re = value >> 8 & 1;
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}
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if ((mask & 0x00FF) == 0) {
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sim->vip.dpctrl.disp = value >> 1 & 1;
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/* if (value & 1) {} TODO: DPRST */
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}
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break;
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case 0x5F824>>1: /* BRTA */
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sim->vip.brtRest[0] = (sim->vip.brtRest[0] & mask) | value;
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break;
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case 0x5F826>>1: /* BRTB */
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sim->vip.brtRest[1] = (sim->vip.brtRest[1] & mask) | value;
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break;
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case 0x5F828>>1: /* BRTC */
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sim->vip.brtRest[2] = (sim->vip.brtRest[2] & mask) | value;
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break;
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case 0x5F82A>>1: /* REST */
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sim->vip.brtRest[3] = (sim->vip.brtRest[3] & mask) | value;
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break;
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case 0x5F82E>>1: /* FRMCYC */
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sim->vip.frmcyc = (sim->vip.frmcyc & mask) | (value & 15);
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break;
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case 0x5F830>>1: /* CTA */
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if ((mask & 0xFF00) == 0)
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sim->vip.cta.cta_r = value >> 8;
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if ((mask & 0x00FF) == 0)
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sim->vip.cta.cta_l = value;
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break;
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case 0x5F842>>1: /* XPCTRL */
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if ((mask & 0xFF00) == 0)
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sim->vip.xpctrl.sbcmp = value >> 8 & 31;
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if ((mask & 0x00FF) == 0) {
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sim->vip.xpctrl.xpen = value >> 1 & 1;
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/* if (value & 1) TODO: XPRST */
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}
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break;
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case 0x5F848>>1: /* SPT0 */
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sim->vip.spt[0] = (sim->vip.spt[0]&mask) | (value&0x03FF&~mask);
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break;
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case 0x5F84A>>1: /* SPT1 */
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sim->vip.spt[1] = (sim->vip.spt[1]&mask) | (value&0x03FF&~mask);
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break;
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case 0x5F84C>>1: /* SPT2 */
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sim->vip.spt[2] = (sim->vip.spt[2]&mask) | (value&0x03FF&~mask);
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break;
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case 0x5F84E>>1: /* SPT3 */
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sim->vip.spt[3] = (sim->vip.spt[3]&mask) | (value&0x03FF&~mask);
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break;
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case 0x5F860>>1: /* GPLT0 */
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vipWritePalette(sim->vip.gplt[0], mask, value);
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break;
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case 0x5F862>>1: /* GPLT1 */
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vipWritePalette(sim->vip.gplt[1], mask, value);
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break;
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case 0x5F864>>1: /* GPLT2 */
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vipWritePalette(sim->vip.gplt[2], mask, value);
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break;
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case 0x5F866>>1: /* GPLT3 */
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vipWritePalette(sim->vip.gplt[3], mask, value);
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break;
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case 0x5F868>>1: /* JPLT0 */
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vipWritePalette(sim->vip.jplt[0], mask, value);
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break;
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case 0x5F86A>>1: /* JPLT1 */
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vipWritePalette(sim->vip.jplt[1], mask, value);
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break;
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case 0x5F86C>>1: /* JPLT2 */
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vipWritePalette(sim->vip.jplt[2], mask, value);
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break;
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case 0x5F86E>>1: /* JPLT3 */
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vipWritePalette(sim->vip.jplt[3], mask, value);
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break;
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case 0x5F870>>1: /* BKCOL */
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sim->vip.bkcol = (sim->vip.bkcol & mask) | (value & 3 * ~mask);
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break;
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}
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}
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/***************************** Library Functions *****************************/
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/* Process component */
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static int vipEmulate(VB *sim, uint32_t clocks) {
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(void) sim;
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(void) clocks;
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return 0;
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}
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/* Read a typed value from the VIP bus */
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static void vipRead(VB *sim, uint32_t address, int type, int32_t *value) {
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/* Working variables */
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address &= 0x0007FFFF;
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/* VRAM */
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if (address < 0x40000) {
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*value = busReadBuffer(&sim->vip.vram[address], type);
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}
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/* Unmapped */
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else if (address < 0x5E000)
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*value = 0;
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/* I/O register */
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else if (address < 0x60000)
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*value = vipReadIO(sim, address, type);
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/* Unmapped */
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if (address < 0x78000)
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*value = 0;
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/* Mirrors of character memory */
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else {
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address = 0x06000 | (address << 2 & 0x18000) | (address & 0x01FFF);
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*value = busReadBuffer(&sim->vip.vram[address], type);
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}
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}
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/* Simulate a hardware reset */
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static void vipReset(VB *sim) {
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int x, y; /* Iterators */
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/* Normal */
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sim->vip.dpctrl.disp = 0;
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sim->vip.dpctrl.re = 0;
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sim->vip.dpctrl.synce = 0;
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sim->vip.intenb = 0x0000;
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sim->vip.xpctrl.xpen = 0;
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/* Extra (the hardware does not do this) */
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sim->vip.bkcol = 0;
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sim->vip.cta.cta_l = 0;
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sim->vip.cta.cta_r = 0;
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sim->vip.frmcyc = 0;
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sim->vip.intpnd = 0x0000;
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sim->vip.dpctrl.fclk = 0;
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sim->vip.dpctrl.l0bsy = 0;
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sim->vip.dpctrl.l1bsy = 0;
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sim->vip.dpctrl.lock = 0;
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sim->vip.dpctrl.r0bsy = 0;
|
||
|
|
sim->vip.dpctrl.r1bsy = 0;
|
||
|
|
sim->vip.dpctrl.scanrdy = 0;
|
||
|
|
sim->vip.xpctrl.f0bsy = 0;
|
||
|
|
sim->vip.xpctrl.f1bsy = 0;
|
||
|
|
sim->vip.xpctrl.overtime = 0;
|
||
|
|
sim->vip.xpctrl.sbcmp = 0;
|
||
|
|
sim->vip.xpctrl.sbcount = 0;
|
||
|
|
sim->vip.xpctrl.sbout = 0;
|
||
|
|
for (x = 0; x < 4; x++) {
|
||
|
|
sim->vip.brtRest[x] = 0;
|
||
|
|
sim->vip.spt [x] = 0;
|
||
|
|
for (y = 0; y < 4; y++) {
|
||
|
|
sim->vip.gplt[x][y] = 0;
|
||
|
|
sim->vip.jplt[x][y] = 0;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Determine how many clocks are guaranteed to process */
|
||
|
|
static uint32_t vipUntil(VB *sim, uint32_t clocks) {
|
||
|
|
(void) sim;
|
||
|
|
return clocks;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Write a typed value to the VIP bus */
|
||
|
|
static void vipWrite(VB*sim,uint32_t address,int type,int32_t value,int debug){
|
||
|
|
(void) debug;
|
||
|
|
|
||
|
|
/* Working variables */
|
||
|
|
address &= 0x0007FFFF;
|
||
|
|
|
||
|
|
/* VRAM */
|
||
|
|
if (address < 0x40000)
|
||
|
|
busWriteBuffer(&sim->vip.vram[address], type, value);
|
||
|
|
|
||
|
|
/* Unmapped */
|
||
|
|
else if (address < 0x5E000)
|
||
|
|
;
|
||
|
|
|
||
|
|
/* I/O register */
|
||
|
|
else if (address < 0x60000)
|
||
|
|
vipWriteIO(sim, address, type, value, debug);
|
||
|
|
|
||
|
|
/* Unmapped */
|
||
|
|
else if (address < 0x78000)
|
||
|
|
;
|
||
|
|
|
||
|
|
/* Mirrors of character memory */
|
||
|
|
else {
|
||
|
|
address = 0x06000 | (address << 2 & 0x18000) | (address & 0x01FFF);
|
||
|
|
busWriteBuffer(&sim->vip.vram[address], type, value);
|
||
|
|
}
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
#endif /* VBAPI */
|