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Implement additional pseudo-halt addresses

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This commit is contained in:
GuyPerfect
2024-10-23 20:35:40 -05:00
parent 226da7a5b3
commit 0c914fce1a
4 changed files with 134 additions and 36 deletions
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core/pseudo-halt.c
+96 -12
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@@ -6,8 +6,13 @@
/********************************* Constants *********************************/
/* Pseudo-halt operations */
#define PH_NEVER 0 /* Must be zero */
#define PH_XPSTTS 1
#define PH_NEVER 0
#define PH_DPSTTS 1
#define PH_GAME_PAD 2
#define PH_INTPND 3
#define PH_TCR 4
#define PH_TLHR 5
#define PH_XPSTTS 6
@@ -17,32 +22,76 @@
static void phActivate(VB *sim, uint32_t address, int type) {
int range; /* Memory address range by component */
(void) type;
/* Working variables */
address = 0x07FFFFFF;
range = address >> 24;
address &= 0x07FFFFFF;
range = address >> 24;
/* Configure CPU */
sim->cpu.operation = CPU_PHALT;
sim->ph.operation = PH_NEVER;
/* Configure pseudo-halt */
sim->ph.operation = PH_NEVER;
/* VIP */
if (range == 0) {
address &= 0x0007FFFF;
/* TODO: Frame buffer */
/* I/O register */
switch (address) {
case 0x5F800: /* INTPND */
if (
sim->vip.dp.step != 0 ||
sim->vip.dp.enabled ||
(sim->vip.dp.disp && sim->vip.dp.synce) ||
sim->vip.xp.enabled ||
sim->vip.xp.xpen
) sim->ph.operation = PH_INTPND;
break;
case 0x5F820: /* DPSTTS */
if (
sim->vip.dp.step != 0 ||
sim->vip.dp.enabled ||
(sim->vip.dp.disp && sim->vip.dp.synce)
) sim->ph.operation = PH_DPSTTS;
break;
case 0x5F840: /* XPSTTS */
if (sim->vip.dp.disp && sim->vip.xp.xpen)
if (sim->vip.xp.enabled || sim->vip.xp.xpen)
sim->ph.operation = PH_XPSTTS;
break;
}
}
/* Misc. I/O */
else if (range == 2 && (type == VB_S8 || type == VB_U8)) {
address &= 0x0000003F;
switch (address) {
/* TODO: Communication port */
/* Game pad */
case 0x10: /* SDLR */
case 0x14: /* SDHR */
case 0x28: /* SCR */
if (sim->pad.si_stat != 0)
sim->ph.operation = PH_GAME_PAD;
break;
/* Timer */
case 0x18: /* TLR */
case 0x1C: /* THR */
if (sim->tmr.t_enb)
sim->ph.operation = PH_TLHR;
break;
case 0x20: /* TCR */
if (sim->tmr.t_enb)
sim->ph.operation = PH_TCR;
break;
}
}
/* Configure CPU */
sim->cpu.clocks = phUntil(sim);
sim->cpu.clocks = phUntil(sim);
sim->cpu.operation = CPU_PHALT;
}
/* Test whether the current memory access matches the monitored access */
@@ -84,6 +133,35 @@ static int phMatches(VB *sim, uint32_t address, int type, int32_t value) {
/****************************** Clock Measurers ******************************/
/* DPSTTS */
static uint32_t phDPSTTS(VB *sim) {
switch (sim->vip.dp.step) {
case 0: /* 0ms - FCLK rising edge */
case 2: /* 3ms-8ms - Display left frame buffer */
case 3: /* 8ms - L*BSY falling edge */
case 6: /* 13ms-18ms - Display right frame buffer */
case 7: /* 18ms - R*BSY falling edge */
return sim->vip.dp.until;
}
/* case 1: 3ms - L*BSY rising edge */
/* case 4: 10ms - FCLK falling edge */
/* case 5: 13ms - R*BSY rising edge */
return sim->vip.dp.clocks;
}
/* INTPND */
static uint32_t phINTPND(VB *sim) {
if (!(
sim->vip.dp.step != 0 ||
sim->vip.dp.enabled ||
(sim->vip.dp.disp && sim->vip.dp.synce)
)) return sim->vip.xp.until;
if (!(sim->vip.xp.enabled || sim->vip.xp.xpen))
return sim->vip.dp.until;
return sim->vip.dp.until < sim->vip.xp.until ?
sim->vip.dp.until : sim->vip.xp.until;
}
/* XPSTTS */
static uint32_t phXPSTTS(VB *sim) {
uint32_t clocks; /* Return value */
@@ -125,6 +203,7 @@ static int phAssess(VB *sim, uint32_t address, int type, int32_t value) {
int x; /* Iterator */
/* Memory access does not match last time */
address &= TYPE_MASKS[type];
if (!phMatches(sim, address, type, value))
sim->ph.step = 0;
@@ -167,7 +246,12 @@ static int phAssess(VB *sim, uint32_t address, int type, int32_t value) {
/* Determine how long the CPU should wait before checking the monitor value */
static uint32_t phUntil(VB *sim) {
switch (sim->ph.operation) {
case PH_XPSTTS: return phXPSTTS(sim);
case PH_DPSTTS : return phDPSTTS(sim);
case PH_GAME_PAD: return sim->pad.si_stat;
case PH_INTPND : return phINTPND(sim);
case PH_TCR : return sim->tmr.until;
case PH_TLHR : return sim->tmr.clocks;
case PH_XPSTTS : return phXPSTTS(sim);
}
return 0; /* PH_NEVER */
}