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Implement VIP, fix interrupts

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This commit is contained in:
GuyPerfect
2024-10-19 17:01:36 -05:00
parent 3c2c9bb938
commit 37b9a94338
4 changed files with 509 additions and 52 deletions
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core/cpu.c
+5 -3
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@@ -376,7 +376,7 @@ static uint32_t cpuSetSystemRegister(VB*sim,
case VB_FEPSW: return sim->cpu.fepsw = value & 0x000FF3FF;
case VB_PIR : return 0x00005346;
case VB_PSW :
sim->cpu.psw.i = value >> 16 & 0xF;
sim->cpu.psw.i = value >> 16 & 15;
sim->cpu.psw.np = value >> 15 & 1;
sim->cpu.psw.ep = value >> 14 & 1;
sim->cpu.psw.ae = value >> 13 & 1;
@@ -414,7 +414,7 @@ static int cpuIRQ(VB *sim) {
if (sim->cpu.psw.id | sim->cpu.psw.ep | sim->cpu.psw.np)
return 0;
level = IRQ_LEVELS[sim->cpu.irq];
if (level == -1 || level > sim->cpu.psw.i)
if (level < sim->cpu.psw.i)
return 0;
cpuThrow(sim, 0xFE00 | level << 4);
return 1;
@@ -476,6 +476,9 @@ static int cpuException(VB *sim) {
/* Regular exception */
else {
/* All exceptions */
sim->cpu.eipsw = cpuGetSystemRegister(sim, VB_PSW);
/* Interrupts only */
if ((cause & 0xFF00) == 0xFE00) {
sim->cpu.psw.i = (cause >> 4 & 7) + 1;
@@ -487,7 +490,6 @@ static int cpuException(VB *sim) {
/* All exceptions */
sim->cpu.ecr.eicc = cause;
sim->cpu.eipsw = cpuGetSystemRegister(sim, VB_PSW);
sim->cpu.eipc = sim->cpu.pc;
sim->cpu.psw.ep = 1;
sim->cpu.nextPC = 0xFFFF0000 |