Implement VSU
This commit is contained in:
parent
50903c7513
commit
3afe0282c2
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@ -3,7 +3,7 @@
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/********************************* Constants *********************************/
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/******************************** Lookup Data ********************************/
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/* Memory access address masks by data type */
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static const uint32_t TYPE_MASKS[] = {
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@ -20,6 +20,7 @@ static const uint32_t TYPE_MASKS[] = {
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static void vipRead (VB *, uint32_t, int, int32_t *);
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static void vipWrite(VB *, uint32_t, int, int32_t, int);
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static void vsuWrite(VB *, uint32_t, int, int32_t, int);
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@ -197,7 +198,9 @@ static void busWrite(VB*sim,uint32_t address,int type,int32_t value,int debug){
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vipWrite(sim, address, type, value, debug);
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break;
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case 1: break; /* VSU */
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case 1: /* VSU */
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vsuWrite(sim, address, type, value, debug);
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break;
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case 2: /* Misc. I/O */
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busWriteMisc(sim, address, type, value);
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@ -857,7 +857,7 @@ static int cpuFloatCommon(VB *sim, double value, int32_t *bits) {
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}
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/* Underflow */
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if (value < 0 ? value > -FLT_MIN : value < FLT_MIN) {
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if (value != 0 && value > -FLT_MIN && value < FLT_MIN) {
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sim->cpu.psw.fud = 1;
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floatVal = 0;
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/* TODO: Can this produce negative zero? */
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@ -6,16 +6,16 @@
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/***************************** Library Functions *****************************/
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/* Process component */
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static int padEmulate(VB *sim, uint32_t clocks) {
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static void padEmulate(VB *sim, uint32_t clocks) {
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/* No hardware read in progress */
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if (sim->pad.si_stat == 0)
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return 0;
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return;
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/* Hardware read completes after time to process */
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if (sim->pad.si_stat > clocks) {
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sim->pad.si_stat -= clocks;
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return 0;
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return;
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}
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/* Complete hardware read */
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@ -30,7 +30,6 @@ static int padEmulate(VB *sim, uint32_t clocks) {
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(sim->pad.keys & 0x000E) == 0
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) sim->cpu.irq |= 0x0001;
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return 0;
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}
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/* Read a value from SCR */
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@ -21,11 +21,11 @@ static void tmrUpdate(VB *sim, uint16_t value) {
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/***************************** Library Functions *****************************/
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/* Process component */
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static int tmrEmulate(VB *sim, uint32_t clocks) {
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static void tmrEmulate(VB *sim, uint32_t clocks) {
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/* Timer is disabled */
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if (!sim->tmr.t_enb)
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return 0;
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return;
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/* Process all clocks */
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for (;;) {
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@ -34,7 +34,7 @@ static int tmrEmulate(VB *sim, uint32_t clocks) {
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if (sim->tmr.clocks > clocks) {
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sim->tmr.clocks -= clocks;
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sim->tmr.until -= clocks;
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return 0;
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return;
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}
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/* Advance forward the component's number of clocks */
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185
core/vb.c
185
core/vb.c
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@ -11,6 +11,63 @@
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/* Output image */
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typedef uint8_t Pixels[2][384*224];
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/* VSU channel */
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typedef struct {
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/* Envelope */
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struct {
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/* Register state */
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uint8_t enb; /* Modifications enabled */
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uint8_t dir; /* Modification direction */
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uint8_t interval; /* Modification interval */
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uint8_t rep; /* Repeat modifications */
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uint8_t value; /* Master output level */
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/* Other state */
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uint32_t clocks; /* Clocks until modification */
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uint8_t reload; /* Automatic reload value */
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} env;
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/* Frequency */
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struct {
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uint16_t current; /* Current value */
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uint16_t written; /* Last value written */
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} freq;
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/* Stereo levels */
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struct {
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uint8_t left; /* Left output level */
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uint8_t right; /* Right output level */
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} lrv;
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/* Control */
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struct {
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/* Register state */
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uint8_t auto_; /* Shutoff enabled */
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uint8_t enb; /* Sound generation enabled */
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uint8_t interval; /* Shutoff interval */
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/* Other state */
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uint32_t clocks; /* Clocks until shutoff */
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} int_;
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/* Waveform */
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struct {
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/* Register state */
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uint8_t wave; /* Waveform index */
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/* Other state */
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int sample; /* Current sample index */
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} wave;
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/* Other state */
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uint32_t clocks; /* Clocks until next sample */
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uint16_t output[2]; /* Current output sample */
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} Channel;
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/* Simulation state */
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struct VB {
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@ -93,7 +150,7 @@ struct VB {
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/* Game pad */
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struct {
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/* Hardware state */
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/* Register state */
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uint8_t k_int_inh; /* Interrupt acknowledge/disable */
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uint8_t para_si; /* Read reset signal */
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uint8_t s_abt_dis; /* Abort hardware read */
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@ -102,7 +159,7 @@ struct VB {
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uint32_t si_stat; /* Hardware read in progress */
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uint8_t soft_ck; /* Controller communication signal */
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/* Simulation state */
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/* Other state */
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uint16_t keys; /* Next input bits */
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int step; /* Software read processing phase */
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} pad;
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@ -110,13 +167,13 @@ struct VB {
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/* Timer */
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struct {
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/* Hardware state */
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/* Register state */
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uint8_t t_clk_sel; /* Counter tick duration */
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uint8_t t_enb; /* Enable timer */
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uint8_t tim_z_int; /* Enable interrupt */
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uint8_t z_stat; /* Zero status */
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/* Simulation state */
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/* Other state */
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uint32_t clocks; /* Master clocks to wait */
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uint16_t counter; /* Current counter value */
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uint16_t reload; /* Reload counter value */
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@ -135,7 +192,7 @@ struct VB {
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/* Display processor */
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struct {
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/* Hardware state */
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/* Register state */
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uint8_t disp; /* Display enabled */
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uint8_t fclk; /* Frame clock signal high */
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uint8_t l0bsy; /* Displaying left frame buffer 0 */
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@ -147,7 +204,7 @@ struct VB {
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uint8_t scanrdy; /* Mirrors are stable */
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uint8_t synce; /* Servo enabled */
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/* Simulation state */
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/* Other state */
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uint8_t brt[4]; /* Precomputed brightness */
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int buffer; /* Index of frame buffer to display */
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uint32_t clocks; /* Master clocks to wait */
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@ -163,7 +220,7 @@ struct VB {
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/* Pixel processor */
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struct {
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/* Hardware state */
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/* Register state */
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uint8_t f0bsy; /* Drawing into frame buffer 0 */
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uint8_t f1bsy; /* Drawing into frame buffer 1 */
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uint8_t overtime; /* Drawing extends into display interval */
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@ -172,7 +229,7 @@ struct VB {
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uint32_t sbout; /* Drawing specified vertical output position */
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uint8_t xpen; /* Drawing enabled */
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/* Simulation state */
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/* Other state */
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uint32_t clocks; /* Master clocks to wait */
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int column; /* Current horizontal output position */
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int frame; /* FRMCYC counter */
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@ -200,6 +257,58 @@ struct VB {
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uint8_t ram[0x40000]; /* Video memory */
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} vip;
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/* VSU */
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struct {
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/* Audio sources */
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Channel channels[6];
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/* Channel 5 frequency modification */
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struct {
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/* Register state */
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uint8_t clk; /* Base modification clock */
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uint8_t dir; /* Sweep direction */
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uint8_t enb; /* Modifications enabled */
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uint8_t func; /* Modification function */
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uint8_t interval; /* Modification interval */
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uint8_t rep; /* Repeat modulation */
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uint8_t shift; /* Sweep shift amount */
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/* Other state */
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uint32_t clocks; /* Clocks until modification */
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uint16_t next; /* Next frequency value */
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int sample; /* Current sample index */
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} freqmod;
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/* Channel 6 noise generator */
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struct {
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/* Register state */
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uint8_t tap; /* LSFR feedback bit position */
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/* Other state */
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uint16_t register_; /* Pseudorandom bits */
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} noise;
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/* Sample output */
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struct {
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float i1[2]; /* Previous analog input sample */
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float o1[2]; /* Previous analog output sample */
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uint32_t capacity; /* Number of audio frames in samples */
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uint32_t offset; /* Position in output buffer */
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int16_t *samples; /* Output memory */
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} out;
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/* Memory */
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int8_t modulation[32]; /* Modulation amounts */
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uint8_t waves[5][32]; /* Wafeform samples */
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/* Other state */
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uint32_t clocks; /* Clocks until next output sample */
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int sample; /* Output sample index, period 417 */
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} vsu;
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/* Other state */
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uint8_t wcr; /* Wait controller state */
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uint8_t wram[0x10000]; /* System RAM */
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@ -210,6 +319,7 @@ struct VB {
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vbOnFetch onFetch; /* CPU instruction fetch */
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vbOnFrame onFrame; /* VIP frame ready */
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vbOnRead onRead; /* CPU instruction read */
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vbOnSamples onSamples; /* VSU samples full */
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vbOnWrite onWrite; /* CPU instruction write */
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void *tag; /* User data */
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};
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@ -238,6 +348,7 @@ static int32_t SignExtend(int32_t value, int32_t bits) {
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#include "bus.c"
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#include "cpu.c"
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#include "vip.c"
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#include "vsu.c"
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@ -245,20 +356,21 @@ static int32_t SignExtend(int32_t value, int32_t bits) {
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/* Process a simulation for a given number of clocks */
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static int sysEmulate(VB *sim, uint32_t clocks) {
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return
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cpuEmulate(sim, clocks) |
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vipEmulate(sim, clocks) |
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padEmulate(sim, clocks) |
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tmrEmulate(sim, clocks)
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;
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int ret;
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ret = cpuEmulate(sim, clocks);
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padEmulate(sim, clocks);
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tmrEmulate(sim, clocks);
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vsuEmulate(sim, clocks);
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ret |= vipEmulate(sim, clocks);
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return ret;
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}
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/* Determine how many clocks are guaranteed to process */
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static uint32_t sysUntil(VB *sim, uint32_t clocks) {
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clocks = cpuUntil(sim, clocks);
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clocks = vipUntil(sim, clocks);
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clocks = padUntil(sim, clocks);
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clocks = tmrUntil(sim, clocks);
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clocks = vipUntil(sim, clocks);
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return clocks;
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}
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@ -395,6 +507,27 @@ VBAPI vbOnRead vbGetReadCallback(VB *sim) {
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return sim->onRead;
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}
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/* Retrieve the audio samples buffer */
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VBAPI void* vbGetSamples(VB *sim, uint32_t *capacity, uint32_t *position) {
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if (capacity == NULL) {
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if (capacity != NULL)
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*capacity = 0;
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if (position != NULL)
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*position = 0;
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} else {
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if (capacity != NULL)
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*capacity = sim->vsu.out.capacity;
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if (position != NULL)
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*position = sim->vsu.out.offset >> 1;
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}
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return sim->vsu.out.samples;
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}
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/* Retrieve the samples callback handler */
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VBAPI vbOnSamples vbGetSamplesCallback(VB *sim) {
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return sim->onSamples;
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}
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/* Retrieve the value in a system register */
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VBAPI uint32_t vbGetSystemRegister(VB *sim, int index) {
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return index < 0 || index > 31 ? 0 : cpuGetSystemRegister(sim, index);
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@ -414,10 +547,12 @@ VBAPI vbOnWrite vbGetWriteCallback(VB *sim) {
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VBAPI VB* vbInit(VB *sim) {
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sim->cart.ram = NULL;
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sim->cart.rom = NULL;
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sim->vsu.out.samples = NULL;
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sim->onExecute = NULL;
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sim->onFetch = NULL;
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sim->onFrame = NULL;
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sim->onRead = NULL;
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sim->onSamples = NULL;
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sim->onWrite = NULL;
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vbReset(sim);
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return sim;
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@ -445,9 +580,10 @@ VBAPI VB* vbReset(VB *sim) {
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/* Components */
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cpuReset(sim);
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vipReset(sim);
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padReset(sim);
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tmrReset(sim);
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vipReset(sim);
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vsuReset(sim);
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return sim;
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}
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@ -526,6 +662,23 @@ VBAPI vbOnRead vbSetReadCallback(VB *sim, vbOnRead callback) {
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return prev;
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}
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/* Specify a new audio samples buffer */
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VBAPI int vbSetSamples(VB *sim, void *samples, uint32_t capacity) {
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if (capacity == 0 || capacity > 0x40000000)
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return 1;
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sim->vsu.out.capacity = capacity;
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sim->vsu.out.offset = 0;
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sim->vsu.out.samples = samples;
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return 0;
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}
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/* Specify a new samples callback handler */
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VBAPI vbOnSamples vbSetSamplesCallback(VB *sim, vbOnSamples callback) {
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vbOnSamples prev = sim->onSamples;
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sim->onSamples = callback;
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return prev;
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}
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/* Specify a new value for a system register */
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VBAPI uint32_t vbSetSystemRegister(VB *sim, int index, uint32_t value) {
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return index < 0 || index > 31 ? 0 :
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@ -23,6 +23,7 @@ extern "C" {
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VB_DIRECT_FETCH
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VB_DIRECT_FRAME
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VB_DIRECT_READ
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VB_DIRECT_SAMPLES
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VB_DIRECT_WRITE
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Implements callbacks as direct function calls with names given by the above
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@ -91,6 +92,7 @@ typedef int (*vbOnExecute )(VB *sim, uint32_t address, const uint16_t *code, in
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typedef int (*vbOnFetch )(VB *sim, int fetch, uint32_t address, int32_t *value, uint32_t *cycles);
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typedef int (*vbOnFrame )(VB *sim);
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typedef int (*vbOnRead )(VB *sim, uint32_t address, int type, int32_t *value, uint32_t *cycles);
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typedef void (*vbOnSamples )(VB *sim, int16_t *buffer, uint32_t capacity);
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typedef int (*vbOnWrite )(VB *sim, uint32_t address, int type, int32_t *value, uint32_t *cycles, int *cancel);
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@ -112,6 +114,8 @@ VBAPI void vbGetPixels (VB *sim, void *left, int leftStrideX,
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VBAPI uint32_t vbGetProgramCounter (VB *sim);
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VBAPI int32_t vbGetProgramRegister (VB *sim, int index);
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VBAPI vbOnRead vbGetReadCallback (VB *sim);
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VBAPI void* vbGetSamples (VB *sim, uint32_t *capacity, uint32_t *position);
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VBAPI vbOnSamples vbGetSamplesCallback (VB *sim);
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VBAPI uint32_t vbGetSystemRegister (VB *sim, int index);
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VBAPI void* vbGetUserData (VB *sim);
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VBAPI vbOnWrite vbGetWriteCallback (VB *sim);
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@ -128,6 +132,8 @@ VBAPI uint16_t vbSetKeys (VB *sim, uint16_t keys);
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VBAPI uint32_t vbSetProgramCounter (VB *sim, uint32_t value);
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VBAPI int32_t vbSetProgramRegister (VB *sim, int index, int32_t value);
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VBAPI vbOnRead vbSetReadCallback (VB *sim, vbOnRead callback);
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VBAPI int vbSetSamples (VB *sim, void *samples, uint32_t capacity);
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VBAPI vbOnSamples vbSetSamplesCallback (VB *sim, vbOnSamples callback);
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VBAPI uint32_t vbSetSystemRegister (VB *sim, int index, uint32_t value);
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VBAPI void* vbSetUserData (VB *sim, void *tag);
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VBAPI vbOnWrite vbSetWriteCallback (VB *sim, vbOnWrite callback);
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@ -0,0 +1,530 @@
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/* This file is included into vb.c and cannot be compiled on its own. */
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#ifdef VBAPI
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/********************************* Constants *********************************/
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/* Analog output low-pass filter coefficient = 0.022 / (0.022 + 1 / 41700) */
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#define RC_A (float) (1 - 1 / 918.4)
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/******************************** Lookup Data ********************************/
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/* Noise feedback bit positions by tap field */
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static uint8_t NOISE_TAPS[] = { 14, 10, 13, 4, 8, 6, 9, 11 };
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/* Clock flags per output sample -- 479 clocks plus bit value */
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/* Ensures exactly 200,000 clocks every 417 samples = 41,700 Hz */
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static uint32_t SAMPLE_CLOCKS[] = {
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0xD6B6B5B5, 0x5ADAD6D6, 0x6D6B6B5B, 0xB5B5ADAD,
|
||||
0xD6D6B6B5, 0x6B5B5ADA, 0xAD6D6D6B, 0xB6B5B5AD,
|
||||
0x5ADAD6D6, 0x6B6B5B5B, 0xB5ADAD6D, 0xD6D6B6B5,
|
||||
0x5B5ADAD6, 1
|
||||
};
|
||||
|
||||
|
||||
|
||||
/***************************** Callback Handlers *****************************/
|
||||
|
||||
/* Samples buffer is full */
|
||||
#ifndef VB_DIRECT_SAMPLES
|
||||
#define VB_ON_SAMPLES sim->onSamples
|
||||
#else
|
||||
extern void VB_DIRECT_SAMPLES(VB *, void *, uint32_t);
|
||||
#define VB_ON_SAMPLES VB_DIRECT_SAMPLES
|
||||
#endif
|
||||
static void vsuOnSamples(VB *sim) {
|
||||
if (sim->onSamples != NULL)
|
||||
VB_ON_SAMPLES(sim, sim->vsu.out.samples, sim->vsu.out.capacity);
|
||||
}
|
||||
#undef VB_ON_EXCEPTION
|
||||
|
||||
|
||||
|
||||
/***************************** Module Functions ******************************/
|
||||
|
||||
/* Stage the next frequency modification value */
|
||||
static void vsuNextFreqMod(VB *sim, Channel *chan) {
|
||||
uint16_t next;
|
||||
|
||||
/* Sweep */
|
||||
if (sim->vsu.freqmod.func == 0) {
|
||||
next = chan->freq.current >> sim->vsu.freqmod.shift;
|
||||
if (sim->vsu.freqmod.dir == 0)
|
||||
next = chan->freq.current - next;
|
||||
else next = chan->freq.current + next;
|
||||
if (next > 2047)
|
||||
chan->int_.enb = 0;
|
||||
}
|
||||
|
||||
/* Modulation */
|
||||
else {
|
||||
next = (chan->freq.written +
|
||||
sim->vsu.modulation[sim->vsu.freqmod.sample]) & 2047;
|
||||
if (sim->vsu.freqmod.sample != 31)
|
||||
sim->vsu.freqmod.sample++;
|
||||
else if (sim->vsu.freqmod.rep)
|
||||
sim->vsu.freqmod.sample = 0;
|
||||
}
|
||||
|
||||
/* Configure state */
|
||||
sim->vsu.freqmod.next = next;
|
||||
}
|
||||
|
||||
/* Process one channel */
|
||||
static void vsuEmulateChannel(VB *sim, int index, uint32_t clocks) {
|
||||
uint32_t bit; /* Pseudorandom bit */
|
||||
Channel *chan; /* Channel handle */
|
||||
uint32_t level; /* Stereo output level */
|
||||
uint32_t sample; /* Input sample */
|
||||
uint32_t until; /* Clocks to process sub-channel components */
|
||||
int e; /* Iterator */
|
||||
|
||||
/* Select channel */
|
||||
chan = &sim->vsu.channels[index];
|
||||
|
||||
/* Select input sample */
|
||||
sample =
|
||||
!chan->int_.enb ? 0 : /* Disabled */
|
||||
index == 5 ? (sim->vsu.noise.register_ & 1) ? 63 : 0 : /* Noise */
|
||||
chan->wave.wave > 4 ? 0 : /* Wave range */
|
||||
sim->vsu.waves[chan->wave.wave][chan->wave.sample] /* Wave */
|
||||
;
|
||||
|
||||
/* Compute output samples */
|
||||
for (e = 0; e < 2; e++) {
|
||||
level = e == 0 ? chan->lrv.left : chan->lrv.right;
|
||||
level = (level * chan->env.value >> 3) + (level && chan->env.value);
|
||||
chan->output[e] = level * sample;
|
||||
}
|
||||
|
||||
/* Channel is disabled */
|
||||
if (!chan->int_.enb)
|
||||
return;
|
||||
|
||||
/* Process all clocks */
|
||||
do {
|
||||
|
||||
/* Clocks until next state change */
|
||||
until = clocks;
|
||||
if (chan->clocks < until) /* Next sample */
|
||||
until = chan->clocks;
|
||||
if (
|
||||
chan->env.enb && /* Modifications enabled */
|
||||
chan->env.clocks < until /* Next modification */
|
||||
) until = chan->env.clocks;
|
||||
if (
|
||||
chan->int_.auto_ && /* Shutoff enabled */
|
||||
chan->int_.clocks < until /* Shutoff */
|
||||
) until = chan->int_.clocks;
|
||||
if (
|
||||
index == 4 && /* Channel 5 */
|
||||
sim->vsu.freqmod.enb && /* Modifications enabled */
|
||||
sim->vsu.freqmod.interval != 0 && /* Modifications valid */
|
||||
sim->vsu.freqmod.clocks < until /* Next modification */
|
||||
) until = sim->vsu.freqmod.clocks;
|
||||
|
||||
/* Manage clocks */
|
||||
clocks -= until;
|
||||
|
||||
/* Automatic shutoff */
|
||||
if (
|
||||
chan->int_.auto_ && /* Shutoff enabled */
|
||||
chan->int_.clocks == until
|
||||
) {
|
||||
chan->int_.enb = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
/* Next sample */
|
||||
if (chan->clocks == until) {
|
||||
|
||||
/* Wave */
|
||||
if (index != 5) {
|
||||
chan->clocks = 4 * (2048 - (uint32_t) chan->freq.current);
|
||||
chan->wave.sample = (chan->wave.sample + 1) & 31;
|
||||
}
|
||||
|
||||
/* Noise */
|
||||
else {
|
||||
chan->clocks = 40 * (2048 - (uint32_t) chan->freq.current);
|
||||
bit = ((
|
||||
sim->vsu.noise.register_ >> NOISE_TAPS[sim->vsu.noise.tap]^
|
||||
sim->vsu.noise.register_ >> 7
|
||||
) & 1) ^ 1;
|
||||
sim->vsu.noise.register_ = bit |
|
||||
(sim->vsu.noise.register_ << 1 & 0x7FFE);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* Envelope modification */
|
||||
if (
|
||||
chan->env.enb && /* Modifications enabled */
|
||||
chan->env.clocks == until
|
||||
) {
|
||||
if (chan->env.dir == 0 && chan->env.value != 0)
|
||||
chan->env.value--;
|
||||
else if (chan->env.dir == 1 && chan->env.value != 15)
|
||||
chan->env.value++;
|
||||
else if (chan->env.rep)
|
||||
chan->env.value = chan->env.reload;
|
||||
else chan->env.enb = 0;
|
||||
chan->env.clocks = (uint32_t) chan->env.interval * 307220;
|
||||
}
|
||||
|
||||
/* Frequency modification */
|
||||
if (
|
||||
index == 4 && /* Channel 5 */
|
||||
sim->vsu.freqmod.enb && /* Modifications enabled */
|
||||
sim->vsu.freqmod.interval != 0 && /* Modifications valid */
|
||||
sim->vsu.freqmod.clocks == until
|
||||
) {
|
||||
chan->freq.current = sim->vsu.freqmod.next;
|
||||
vsuNextFreqMod(sim, chan);
|
||||
if (!chan->int_.enb)
|
||||
return;
|
||||
sim->vsu.freqmod.clocks = (uint32_t) sim->vsu.freqmod.interval *
|
||||
(sim->vsu.freqmod.clk == 0 ? 19201 : 153610);
|
||||
}
|
||||
|
||||
} while (clocks != 0);
|
||||
|
||||
}
|
||||
|
||||
/* Write a value to S*EV0 */
|
||||
static void vsuWriteEV0(VB *sim, int index, uint8_t value) {
|
||||
Channel *chan = &sim->vsu.channels[index];
|
||||
|
||||
/* Parse fields */
|
||||
chan->env.dir = value >> 3 & 1;
|
||||
chan->env.interval = value & 7;
|
||||
chan->env.value = value >> 4 & 15;
|
||||
chan->env.reload = chan->env.value;
|
||||
|
||||
/* Configure state */
|
||||
chan->env.clocks = (uint32_t) chan->env.interval * 307220;
|
||||
}
|
||||
|
||||
/* Write a value to S*EV1 */
|
||||
static void vsuWriteEV1(VB *sim, int index, uint8_t value) {
|
||||
Channel *chan = &sim->vsu.channels[index];
|
||||
|
||||
/* Parse fields */
|
||||
chan->env.enb = value & 1;
|
||||
chan->env.rep = value >> 1 & 1;
|
||||
|
||||
/* Processing by channel */
|
||||
switch (index) {
|
||||
|
||||
case 4: /* Channel 5 */
|
||||
sim->vsu.freqmod.enb = value >> 6 & 1;
|
||||
sim->vsu.freqmod.func = value >> 4 & 1;
|
||||
sim->vsu.freqmod.rep = value >> 4 & 1;
|
||||
vsuNextFreqMod(sim, chan);
|
||||
break;
|
||||
|
||||
case 5: /* Channel 6 */
|
||||
sim->vsu.noise.tap = value >> 4 & 7;
|
||||
sim->vsu.noise.register_ = 0x0000;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* Write a value to S*FQH */
|
||||
static void vsuWriteFQH(VB *sim, int index, uint16_t value) {
|
||||
Channel *chan = &sim->vsu.channels[index];
|
||||
value = value << 8 & 0x0700;
|
||||
chan->freq.current = (chan->freq.current & 0x00FF) | value;
|
||||
chan->freq.written = (chan->freq.written & 0x00FF) | value;
|
||||
}
|
||||
|
||||
/* Write a value to S*FQL */
|
||||
static void vsuWriteFQL(VB *sim, int index, uint8_t value) {
|
||||
Channel *chan = &sim->vsu.channels[index];
|
||||
chan->freq.current = (chan->freq.current & 0x0700) | value;
|
||||
chan->freq.written = (chan->freq.written & 0x0700) | value;
|
||||
}
|
||||
|
||||
/* Write a value to S*INT */
|
||||
static void vsuWriteINT(VB *sim, int index, uint8_t value) {
|
||||
Channel *chan = &sim->vsu.channels[index];
|
||||
|
||||
/* Parse fields */
|
||||
chan->int_.auto_ = value >> 5 & 1;
|
||||
chan->int_.enb = value >> 7 & 1;
|
||||
chan->int_.interval = value & 31;
|
||||
|
||||
/* Update state */
|
||||
chan->int_.clocks = 76805 * (uint32_t) chan->int_.interval;
|
||||
chan->clocks = (index == 5 ? 40 : 4) *
|
||||
((uint32_t) 2048 - chan->freq.current);
|
||||
if (index != 5)
|
||||
chan->wave.sample = 0;
|
||||
else sim->vsu.noise.register_ = 0x0000;
|
||||
if (index == 4) {
|
||||
sim->vsu.freqmod.clocks = (uint32_t) sim->vsu.freqmod.interval *
|
||||
(sim->vsu.freqmod.clk ? 153610 : 19201);
|
||||
sim->vsu.freqmod.sample = 0;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* Write a value to S*LRV */
|
||||
static void vsuWriteLRV(VB *sim, int index, uint8_t value) {
|
||||
Channel *chan = &sim->vsu.channels[index];
|
||||
chan->lrv.left = value >> 4 & 15;
|
||||
chan->lrv.right = value & 15;
|
||||
}
|
||||
|
||||
/* Write a value to S*RAM */
|
||||
static void vsuWriteRAM(VB *sim, int index, uint8_t value) {
|
||||
sim->vsu.channels[index].wave.wave = value & 7;
|
||||
}
|
||||
|
||||
/* Write a value to S5SWP */
|
||||
static void vsuWriteSWP(VB *sim, uint8_t value) {
|
||||
uint32_t clocks;
|
||||
|
||||
/* Parse fields */
|
||||
sim->vsu.freqmod.clk = value >> 7 & 1;
|
||||
sim->vsu.freqmod.dir = value >> 3 & 1;
|
||||
sim->vsu.freqmod.interval = value >> 4 & 15;
|
||||
sim->vsu.freqmod.shift = value & 7;
|
||||
|
||||
/* Configure state */
|
||||
clocks = (uint32_t) sim->vsu.freqmod.interval *
|
||||
(sim->vsu.freqmod.clk ? 153610 : 19201);
|
||||
if (clocks < sim->vsu.freqmod.clocks)
|
||||
sim->vsu.freqmod.clocks = clocks;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/***************************** Module Functions ******************************/
|
||||
|
||||
/* Process component */
|
||||
static void vsuEmulate(VB *sim, uint32_t clocks) {
|
||||
Channel *chan; /* Channel handle */
|
||||
uint32_t digital[2]; /* Digital output samples */
|
||||
float i0; /* Current analog input sample */
|
||||
float o0; /* Current analog output sample */
|
||||
uint32_t until; /* Clocks to process channels */
|
||||
int e, x; /* Iterators */
|
||||
|
||||
/* Process all clocks */
|
||||
do {
|
||||
|
||||
/* Clocks until next sample */
|
||||
until = clocks;
|
||||
if (sim->vsu.clocks < until)
|
||||
until = sim->vsu.clocks;
|
||||
|
||||
/* Working variables */
|
||||
clocks -= until;
|
||||
digital[0] = digital[1] = 0;
|
||||
|
||||
/* Process all channels */
|
||||
for (x = 0; x < 6; x++) {
|
||||
chan = &sim->vsu.channels[x];
|
||||
vsuEmulateChannel(sim, x, until);
|
||||
digital[0] += chan->output[0];
|
||||
digital[1] += chan->output[1];
|
||||
}
|
||||
|
||||
/* Output sample */
|
||||
for (e = 0; e < 2; e++) {
|
||||
|
||||
/* Compute the output sample for this stereo channel */
|
||||
i0 = (digital[e] >> 4) / 685.0f;
|
||||
o0 = RC_A * (sim->vsu.out.o1[e] + i0 - sim->vsu.out.i1[e]);
|
||||
if (o0 < -1.0f) o0 = -1.0f;
|
||||
if (o0 > +1.0f) o0 = +1.0f;
|
||||
sim->vsu.out.i1[e] = i0;
|
||||
sim->vsu.out.o1[e] = o0;
|
||||
|
||||
/* Output the sample to caller memory */
|
||||
if (
|
||||
sim->vsu.out.samples != NULL &&
|
||||
sim->vsu.out.offset >> 1 < sim->vsu.out.capacity
|
||||
) {
|
||||
sim->vsu.out.samples[sim->vsu.out.offset++] =
|
||||
(int16_t) (o0 * 32767.0f + (o0 < 0.0f ? -0.5f : +0.5f));
|
||||
if (
|
||||
e == 1 &&
|
||||
sim->vsu.out.offset >> 1 == sim->vsu.out.capacity
|
||||
) vsuOnSamples(sim);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* Advance to the next sample */
|
||||
sim->vsu.sample += sim->vsu.sample == 416 ? -416 : 1;
|
||||
sim->vsu.clocks = 479 + (1 &
|
||||
SAMPLE_CLOCKS[sim->vsu.sample >> 5] >> (sim->vsu.sample & 31));
|
||||
|
||||
} while (clocks != 0);
|
||||
|
||||
}
|
||||
|
||||
/* Simulate a hardware reset */
|
||||
static void vsuReset(VB *sim) {
|
||||
Channel *chan; /* Channel handle */
|
||||
int x, y; /* Iterators */
|
||||
|
||||
/* Memory */
|
||||
for (x = 0; x < 32; x++) {
|
||||
sim->vsu.modulation[x] = 0;
|
||||
for (y = 0; y < 5; y++)
|
||||
sim->vsu.waves[y][x] = 0;
|
||||
}
|
||||
|
||||
/* Channel state */
|
||||
for (x = 0; x < 6; x++) {
|
||||
chan = &sim->vsu.channels[x];
|
||||
chan->clocks = 0;
|
||||
chan->env.clocks = 0;
|
||||
chan->env.enb = 0;
|
||||
chan->env.dir = 0;
|
||||
chan->env.interval = 0;
|
||||
chan->env.reload = 0;
|
||||
chan->env.rep = 0;
|
||||
chan->env.value = 0;
|
||||
chan->freq.current = 0x000;
|
||||
chan->freq.written = 0x000;
|
||||
chan->lrv.left = 0;
|
||||
chan->lrv.right = 0;
|
||||
chan->int_.auto_ = 0;
|
||||
chan->int_.clocks = 0;
|
||||
chan->int_.enb = 0;
|
||||
chan->int_.interval = 0;
|
||||
chan->wave.sample = 0;
|
||||
chan->wave.wave = 0;
|
||||
}
|
||||
|
||||
/* Other channel state */
|
||||
sim->vsu.freqmod.clk = 0;
|
||||
sim->vsu.freqmod.clocks = 0;
|
||||
sim->vsu.freqmod.dir = 0;
|
||||
sim->vsu.freqmod.enb = 0;
|
||||
sim->vsu.freqmod.func = 0;
|
||||
sim->vsu.freqmod.interval = 0;
|
||||
sim->vsu.freqmod.next = 0;
|
||||
sim->vsu.freqmod.rep = 0;
|
||||
sim->vsu.freqmod.sample = 0;
|
||||
sim->vsu.freqmod.shift = 0;
|
||||
sim->vsu.noise.register_ = 0;
|
||||
sim->vsu.noise.tap = 0;
|
||||
|
||||
/* Other */
|
||||
sim->vsu.clocks = 479 + (SAMPLE_CLOCKS[0] & 1);
|
||||
sim->vsu.sample = 0;
|
||||
for (x = 0; x < 2; x++)
|
||||
sim->vsu.out.i1[x] = sim->vsu.out.o1[x] = 0;
|
||||
}
|
||||
|
||||
/* Write a typed value to the VSU bus */
|
||||
static void vsuWrite(VB*sim,uint32_t address,int type,int32_t value,int debug){
|
||||
|
||||
/* Only byte writes are allowed */
|
||||
switch (type) {
|
||||
case VB_S16:
|
||||
case VB_U16:
|
||||
case VB_S32:
|
||||
return;
|
||||
}
|
||||
|
||||
/* Unmapped */
|
||||
if (address & 3)
|
||||
return;
|
||||
|
||||
/* Working variables */
|
||||
address &= 0x7FF;
|
||||
|
||||
/* Wave memory */
|
||||
if (address < 0x280) {
|
||||
if (debug || !(
|
||||
sim->vsu.channels[0].int_.enb |
|
||||
sim->vsu.channels[1].int_.enb |
|
||||
sim->vsu.channels[2].int_.enb |
|
||||
sim->vsu.channels[3].int_.enb |
|
||||
sim->vsu.channels[4].int_.enb |
|
||||
sim->vsu.channels[5].int_.enb
|
||||
)) sim->vsu.waves[address >> 7][address >> 2 & 31] = value & 63;
|
||||
}
|
||||
|
||||
/* Modulation memory */
|
||||
else if (address < 0x300) {
|
||||
if (debug || !sim->vsu.channels[4].int_.enb)
|
||||
sim->vsu.modulation[address >> 2 & 31] = value;
|
||||
}
|
||||
|
||||
/* I/O register */
|
||||
else switch (address >> 2) {
|
||||
|
||||
case 0x400>>2: vsuWriteINT(sim, 0, value); break; /* S1INT */
|
||||
case 0x404>>2: vsuWriteLRV(sim, 0, value); break; /* S1LRV */
|
||||
case 0x408>>2: vsuWriteFQL(sim, 0, value); break; /* S1FQL */
|
||||
case 0x40C>>2: vsuWriteFQH(sim, 0, value); break; /* S1FQH */
|
||||
case 0x410>>2: vsuWriteEV0(sim, 0, value); break; /* S1EV0 */
|
||||
case 0x414>>2: vsuWriteEV1(sim, 0, value); break; /* S1EV1 */
|
||||
case 0x418>>2: vsuWriteRAM(sim, 0, value); break; /* S1RAM */
|
||||
|
||||
case 0x440>>2: vsuWriteINT(sim, 1, value); break; /* S2INT */
|
||||
case 0x444>>2: vsuWriteLRV(sim, 1, value); break; /* S2LRV */
|
||||
case 0x448>>2: vsuWriteFQL(sim, 1, value); break; /* S2FQL */
|
||||
case 0x44C>>2: vsuWriteFQH(sim, 1, value); break; /* S2FQH */
|
||||
case 0x450>>2: vsuWriteEV0(sim, 1, value); break; /* S2EV0 */
|
||||
case 0x454>>2: vsuWriteEV1(sim, 1, value); break; /* S2EV1 */
|
||||
case 0x458>>2: vsuWriteRAM(sim, 1, value); break; /* S2RAM */
|
||||
|
||||
case 0x480>>2: vsuWriteINT(sim, 2, value); break; /* S3INT */
|
||||
case 0x484>>2: vsuWriteLRV(sim, 2, value); break; /* S3LRV */
|
||||
case 0x488>>2: vsuWriteFQL(sim, 2, value); break; /* S3FQL */
|
||||
case 0x48C>>2: vsuWriteFQH(sim, 2, value); break; /* S3FQH */
|
||||
case 0x490>>2: vsuWriteEV0(sim, 2, value); break; /* S3EV0 */
|
||||
case 0x494>>2: vsuWriteEV1(sim, 2, value); break; /* S3EV1 */
|
||||
case 0x498>>2: vsuWriteRAM(sim, 2, value); break; /* S3RAM */
|
||||
|
||||
case 0x4C0>>2: vsuWriteINT(sim, 3, value); break; /* S4INT */
|
||||
case 0x4C4>>2: vsuWriteLRV(sim, 3, value); break; /* S4LRV */
|
||||
case 0x4C8>>2: vsuWriteFQL(sim, 3, value); break; /* S4FQL */
|
||||
case 0x4CC>>2: vsuWriteFQH(sim, 3, value); break; /* S4FQH */
|
||||
case 0x4D0>>2: vsuWriteEV0(sim, 3, value); break; /* S4EV0 */
|
||||
case 0x4D4>>2: vsuWriteEV1(sim, 3, value); break; /* S4EV1 */
|
||||
case 0x4D8>>2: vsuWriteRAM(sim, 3, value); break; /* S4RAM */
|
||||
|
||||
case 0x500>>2: vsuWriteINT(sim, 4, value); break; /* S5INT */
|
||||
case 0x504>>2: vsuWriteLRV(sim, 4, value); break; /* S5LRV */
|
||||
case 0x508>>2: vsuWriteFQL(sim, 4, value); break; /* S5FQL */
|
||||
case 0x50C>>2: vsuWriteFQH(sim, 4, value); break; /* S5FQH */
|
||||
case 0x510>>2: vsuWriteEV0(sim, 4, value); break; /* S5EV0 */
|
||||
case 0x514>>2: vsuWriteEV1(sim, 4, value); break; /* S5EV1 */
|
||||
case 0x518>>2: vsuWriteRAM(sim, 4, value); break; /* S5RAM */
|
||||
case 0x51C>>2: vsuWriteSWP(sim, value); break; /* S5SWP */
|
||||
|
||||
case 0x540>>2: vsuWriteINT(sim, 5, value); break; /* S5INT */
|
||||
case 0x544>>2: vsuWriteLRV(sim, 5, value); break; /* S5LRV */
|
||||
case 0x548>>2: vsuWriteFQL(sim, 5, value); break; /* S5FQL */
|
||||
case 0x54C>>2: vsuWriteFQH(sim, 5, value); break; /* S5FQH */
|
||||
case 0x550>>2: vsuWriteEV0(sim, 5, value); break; /* S5EV0 */
|
||||
case 0x554>>2: vsuWriteEV1(sim, 5, value); break; /* S5EV1 */
|
||||
|
||||
case 0x580>>2: /* SSTOP */
|
||||
if ((value & 1) == 0)
|
||||
break;
|
||||
sim->vsu.channels[0].int_.enb =
|
||||
sim->vsu.channels[1].int_.enb =
|
||||
sim->vsu.channels[2].int_.enb =
|
||||
sim->vsu.channels[3].int_.enb =
|
||||
sim->vsu.channels[4].int_.enb =
|
||||
sim->vsu.channels[5].int_.enb = 0;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
#endif /* VBAPI */
|
||||
Loading…
Reference in New Issue