Establish display processing
This commit is contained in:
parent
c91eb0785f
commit
448658430c
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@ -1692,10 +1692,8 @@ static int cpuEmulate(VB *sim, uint32_t clocks) {
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}
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/* Advance forward the CPU's number of clocks */
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if (sim->cpu.clocks != 0) {
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clocks -= sim->cpu.clocks;
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sim->cpu.clocks = 0;
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}
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/* Processing by operation ID */
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switch (sim->cpu.operation) {
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60
core/vb.c
60
core/vb.c
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@ -96,8 +96,10 @@ struct VB {
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uint8_t cta_r; /* Right column table index */
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} cta;
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/* Display control */
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/* Display processor */
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struct {
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/* Hardware state */
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uint8_t disp; /* Display enabled */
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uint8_t fclk; /* Frame clock signal high */
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uint8_t l0bsy; /* Displaying left frame buffer 0 */
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@ -108,9 +110,20 @@ struct VB {
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uint8_t re; /* Memory refresh enabled */
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uint8_t scanrdy; /* Mirrors are stable */
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uint8_t synce; /* Servo enabled */
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} dpctrl;
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/* Drawing control */
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/* Simulation state */
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uint8_t brt[4]; /* Precomputed brightness */
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int buffer; /* Index of frame buffer to display */
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uint32_t clocks; /* Master clocks to wait */
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int column; /* Index of column to display */
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uint32_t cta; /* Column table pointer in memory */
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uint32_t fbDest; /* Output frame pixel address */
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uint32_t fbSrc; /* Source frame buffer address */
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int32_t repeat; /* Current column table repeat value */
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int step; /* Processing phase */
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} dp;
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/* Pixel processor */
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struct {
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uint8_t f0bsy; /* Drawing into frame buffer 0 */
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uint8_t f1bsy; /* Drawing into frame buffer 1 */
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@ -119,7 +132,7 @@ struct VB {
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uint8_t sbcount; /* Current vertical output position */
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uint8_t sbout; /* Drawing specified vertical output position */
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uint8_t xpen; /* Drawing enabled */
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} xpctrl;
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} xp;
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/* Control state */
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uint8_t bkcol; /* Backdrop color */
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@ -131,8 +144,11 @@ struct VB {
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uint8_t jplt[4][4]; /* Object palettes */
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uint16_t spt[4]; /* Object control */
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/* Output frame buffers [buffer index][0=left, 1=right][pixel index] */
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uint8_t frames[2][2][384 * 224];
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/* Other state */
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uint8_t vram[0x40000]; /* Video memory */
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uint8_t ram[0x40000]; /* Video memory */
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} vip;
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/* Other state */
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@ -142,6 +158,7 @@ struct VB {
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vbOnException onException; /* CPU exception */
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vbOnExecute onExecute; /* CPU instruction execute */
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vbOnFetch onFetch; /* CPU instruction fetch */
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vbOnFrame onFrame; /* VIP frame ready */
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vbOnRead onRead; /* CPU instruction read */
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vbOnWrite onWrite; /* CPU instruction write */
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void *tag; /* User data */
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@ -242,21 +259,26 @@ VBAPI void* vbGetCartROM(VB *sim, uint32_t *size) {
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return sim->cart.rom;
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}
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/* Retrieve the exception callback handle */
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/* Retrieve the exception callback handler */
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VBAPI vbOnException vbGetExceptionCallback(VB *sim) {
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return sim->onException;
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}
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/* Retrieve the execute callback handle */
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/* Retrieve the execute callback handler */
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VBAPI vbOnExecute vbGetExecuteCallback(VB *sim) {
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return sim->onExecute;
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}
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/* Retrieve the fetch callback handle */
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/* Retrieve the fetch callback handler */
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VBAPI vbOnFetch vbGetFetchCallback(VB *sim) {
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return sim->onFetch;
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}
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/* Retrieve the frame callback handler */
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VBAPI vbOnFrame vbGetFrameCallback(VB *sim) {
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return sim->onFrame;
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}
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/* Retrieve the value of the program counter */
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VBAPI uint32_t vbGetProgramCounter(VB *sim) {
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return sim->cpu.pc;
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@ -267,7 +289,7 @@ VBAPI int32_t vbGetProgramRegister(VB *sim, int index) {
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return index < 1 || index > 31 ? 0 : sim->cpu.program[index];
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}
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/* Retrieve the read callback handle */
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/* Retrieve the read callback handler */
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VBAPI vbOnRead vbGetReadCallback(VB *sim) {
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return sim->onRead;
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}
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@ -282,7 +304,7 @@ VBAPI void* vbGetUserData(VB *sim) {
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return sim->tag;
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}
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/* Retrieve the write callback handle */
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/* Retrieve the write callback handler */
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VBAPI vbOnWrite vbGetWriteCallback(VB *sim) {
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return sim->onWrite;
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}
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@ -293,6 +315,7 @@ VBAPI VB* vbInit(VB *sim) {
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sim->cart.rom = NULL;
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sim->onExecute = NULL;
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sim->onFetch = NULL;
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sim->onFrame = NULL;
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sim->onRead = NULL;
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sim->onWrite = NULL;
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vbReset(sim);
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@ -344,27 +367,34 @@ VBAPI int vbSetCartROM(VB *sim, void *rom, uint32_t size) {
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return 0;
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}
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/* Specify a new exception callback handle */
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/* Specify a new exception callback handler */
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VBAPI vbOnException vbSetExceptionCallback(VB *sim, vbOnException callback) {
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vbOnException prev = sim->onException;
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sim->onException = callback;
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return prev;
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}
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/* Specify a new execute callback handle */
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/* Specify a new execute callback handler */
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VBAPI vbOnExecute vbSetExecuteCallback(VB *sim, vbOnExecute callback) {
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vbOnExecute prev = sim->onExecute;
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sim->onExecute = callback;
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return prev;
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}
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/* Specify a new fetch callback handle */
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/* Specify a new fetch callback handler */
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VBAPI vbOnFetch vbSetFetchCallback(VB *sim, vbOnFetch callback) {
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vbOnFetch prev = sim->onFetch;
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sim->onFetch = callback;
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return prev;
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}
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/* Specify a new frame callback handler */
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VBAPI vbOnFrame vbSetFrameCallback(VB *sim, vbOnFrame callback) {
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vbOnFrame prev = sim->onFrame;
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sim->onFrame = callback;
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return prev;
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}
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/* Specify a new value for the program counter */
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VBAPI uint32_t vbSetProgramCounter(VB *sim, uint32_t value) {
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sim->cpu.operation = CPU_FETCH;
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@ -378,7 +408,7 @@ VBAPI int32_t vbSetProgramRegister(VB *sim, int index, int32_t value) {
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return index < 1 || index > 31 ? 0 : (sim->cpu.program[index] = value);
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}
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/* Specify a new read callback handle */
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/* Specify a new read callback handler */
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VBAPI vbOnRead vbSetReadCallback(VB *sim, vbOnRead callback) {
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vbOnRead prev = sim->onRead;
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sim->onRead = callback;
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@ -391,7 +421,7 @@ VBAPI uint32_t vbSetSystemRegister(VB *sim, int index, uint32_t value) {
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cpuSetSystemRegister(sim, index, value, 1);
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}
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/* Specify a new write callback handle */
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/* Specify a new write callback handler */
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VBAPI vbOnWrite vbSetWriteCallback(VB *sim, vbOnWrite callback) {
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vbOnWrite prev = sim->onWrite;
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sim->onWrite = callback;
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12
core/vb.h
12
core/vb.h
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@ -21,6 +21,7 @@ extern "C" {
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VB_DIRECT_EXCEPTION
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VB_DIRECT_EXECUTE
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VB_DIRECT_FETCH
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VB_DIRECT_FRAME
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VB_DIRECT_READ
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VB_DIRECT_WRITE
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@ -58,14 +59,6 @@ extern "C" {
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/********************************* Constants *********************************/
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/* Callback IDs */
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#define VB_EXCEPTION 0
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#define VB_EXECUTE 1
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#define VB_FETCH 2
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#define VB_FRAME 3
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#define VB_READ 4
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#define VB_WRITE 5
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/* System registers */
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#define VB_ADTRE 25
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#define VB_CHCW 24
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@ -96,6 +89,7 @@ typedef struct VB VB;
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typedef int (*vbOnException)(VB *sim, uint16_t *cause);
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typedef int (*vbOnExecute )(VB *sim, uint32_t address, const uint16_t *code, int length);
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typedef int (*vbOnFetch )(VB *sim, int fetch, uint32_t address, int32_t *value, uint32_t *cycles);
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typedef int (*vbOnFrame )(VB *sim);
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typedef int (*vbOnRead )(VB *sim, uint32_t address, int type, int32_t *value, uint32_t *cycles);
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typedef int (*vbOnWrite )(VB *sim, uint32_t address, int type, int32_t *value, uint32_t *cycles, int *cancel);
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@ -112,6 +106,7 @@ VBAPI void* vbGetCartROM (VB *sim, uint32_t *size);
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VBAPI vbOnException vbGetExceptionCallback(VB *sim);
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VBAPI vbOnExecute vbGetExecuteCallback (VB *sim);
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VBAPI vbOnFetch vbGetFetchCallback (VB *sim);
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VBAPI vbOnFrame vbGetFrameCallback (VB *sim);
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VBAPI uint32_t vbGetProgramCounter (VB *sim);
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VBAPI int32_t vbGetProgramRegister (VB *sim, int index);
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VBAPI vbOnRead vbGetReadCallback (VB *sim);
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@ -126,6 +121,7 @@ VBAPI int vbSetCartROM (VB *sim, void *rom, uint32_t size);
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VBAPI vbOnException vbSetExceptionCallback(VB *sim, vbOnException callback);
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VBAPI vbOnExecute vbSetExecuteCallback (VB *sim, vbOnExecute callback);
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VBAPI vbOnFetch vbSetFetchCallback (VB *sim, vbOnFetch callback);
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VBAPI vbOnFrame vbSetFrameCallback (VB *sim, vbOnFrame callback);
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VBAPI uint32_t vbSetProgramCounter (VB *sim, uint32_t value);
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VBAPI int32_t vbSetProgramRegister (VB *sim, int index, int32_t value);
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VBAPI vbOnRead vbSetReadCallback (VB *sim, vbOnRead callback);
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295
core/vip.c
295
core/vip.c
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@ -3,13 +3,68 @@
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/********************************** Macros ***********************************/
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/* Compute how many clocks are in some number of milliseconds */
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#define vipClocksMs(x) x * 20000
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/***************************** Module Functions ******************************/
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/* Precompute brightness values for image output */
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static void vipComputeBrightness(VB *sim) {
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int32_t brt[4]; /* Working output */
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int32_t repeat; /* Multiplier from column table */
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int x; /* Iterator */
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/* Compute brightness from hardware state */
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repeat = (int32_t) sim->vip.ram[sim->vip.dp.cta + 1] + 1;
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brt[1] = repeat * sim->vip.brtRest[0];
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brt[2] = repeat * sim->vip.brtRest[1];
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brt[3] = repeat * sim->vip.brtRest[2] + brt[2] + brt[1];
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/* Scale brightness values to 0..255 */
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for (x = 1; x < 4; x++)
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sim->vip.dp.brt[x] = ((brt[x] > 127 ? 127 : brt[x]) * 510 + 127) / 254;
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}
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/* Read a palette */
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static int32_t vipReadPalette(uint8_t *entries) {
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return entries[3] << 6 | entries[2] << 4 | entries[1] << 2;
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}
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/* Raise an interrupt request */
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static void vipThrow(VB *sim, uint16_t cause) {
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if (!(sim->vip.intenb & cause))
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return;
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sim->vip.intpnd |= cause;
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sim->cpu.irq |= 0x0010;
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}
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/* Transfer one column of frame buffer pixels to output */
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static void vipTransferColumn(VB *sim, int32_t eye) {
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int32_t bits; /* Pixel bits from frame buffer */
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int y, z; /* Iterators */
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/* Select source and destination addresses in host memory */
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uint8_t *dest = &sim->vip.frames
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[sim->vip.dp.buffer][eye][sim->vip.dp.column];
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uint8_t *src = &sim->vip.ram[
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eye << 16 |
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sim->vip.dp.buffer << 15 |
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sim->vip.dp.column << 6
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];
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/* Transfer all rows as words */
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for (y = 0; y < 224; y += 4) {
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bits = busReadBuffer(src, VB_S32);
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for (z = 0; z < 1536; z += 384, bits >>= 2)
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dest[z] = sim->vip.dp.brt[bits & 3];
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}
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}
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/* Write a palette */
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static void vipWritePalette(uint8_t *entries, int32_t mask, int32_t value) {
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if (mask & 0x00FF)
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@ -21,7 +76,7 @@ static void vipWritePalette(uint8_t *entries, int32_t mask, int32_t value) {
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/* Read a typed value from an I/O register */
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static int32_t vipReadIO(VB *sim, uint32_t address, int type) {
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int mask; /* Byte access mask */
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int32_t mask; /* Byte access mask */
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int32_t value; /* Return value */
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/* Adjustments by type */
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@ -53,16 +108,16 @@ static int32_t vipReadIO(VB *sim, uint32_t address, int type) {
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case 0x5F820>>1: /* DPSTTS */
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value =
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(int32_t) sim->vip.dpctrl.lock << 10 |
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(int32_t) sim->vip.dpctrl.synce << 9 |
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(int32_t) sim->vip.dpctrl.re << 8 |
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(int32_t) sim->vip.dpctrl.fclk << 7 |
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(int32_t) sim->vip.dpctrl.scanrdy << 6 |
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(int32_t) sim->vip.dpctrl.r1bsy << 5 |
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(int32_t) sim->vip.dpctrl.l1bsy << 4 |
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(int32_t) sim->vip.dpctrl.r0bsy << 3 |
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(int32_t) sim->vip.dpctrl.l0bsy << 2 |
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(int32_t) sim->vip.dpctrl.disp << 1
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(int32_t) sim->vip.dp.lock << 10 |
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(int32_t) sim->vip.dp.synce << 9 |
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(int32_t) sim->vip.dp.re << 8 |
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(int32_t) sim->vip.dp.fclk << 7 |
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(int32_t) sim->vip.dp.scanrdy << 6 |
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(int32_t) sim->vip.dp.r1bsy << 5 |
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(int32_t) sim->vip.dp.l1bsy << 4 |
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(int32_t) sim->vip.dp.r0bsy << 3 |
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(int32_t) sim->vip.dp.l0bsy << 2 |
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(int32_t) sim->vip.dp.disp << 1
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;
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break;
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@ -89,12 +144,12 @@ static int32_t vipReadIO(VB *sim, uint32_t address, int type) {
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case 0x5F840>>1: /* XPSTTS */
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value =
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(int32_t) sim->vip.xpctrl.sbout << 15 |
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(int32_t) sim->vip.xpctrl.sbcount << 8 |
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(int32_t) sim->vip.xpctrl.overtime << 4 |
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(int32_t) sim->vip.xpctrl.f1bsy << 3 |
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(int32_t) sim->vip.xpctrl.f0bsy << 2 |
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(int32_t) sim->vip.xpctrl.xpen << 1
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(int32_t) sim->vip.xp.sbout << 15 |
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(int32_t) sim->vip.xp.sbcount << 8 |
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(int32_t) sim->vip.xp.overtime << 4 |
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(int32_t) sim->vip.xp.f1bsy << 3 |
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(int32_t) sim->vip.xp.f0bsy << 2 |
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(int32_t) sim->vip.xp.xpen << 1
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;
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break;
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@ -158,7 +213,7 @@ static int32_t vipReadIO(VB *sim, uint32_t address, int type) {
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/* Write a typed value to an I/O register */
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static void vipWriteIO(
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VB *sim, uint32_t address, int type, int32_t value, int debug) {
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int mask; /* Byte access mask */
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int32_t mask; /* Byte access mask */
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/* Adjustments by type */
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switch (type) {
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@ -202,12 +257,12 @@ static void vipWriteIO(
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case 0x5F822>>1: /* DPCTRL */
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if ((mask & 0xFF00) == 0) {
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sim->vip.dpctrl.lock = value >> 10 & 1;
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sim->vip.dpctrl.synce = value >> 9 & 1;
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sim->vip.dpctrl.re = value >> 8 & 1;
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sim->vip.dp.lock = value >> 10 & 1;
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sim->vip.dp.synce = value >> 9 & 1;
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sim->vip.dp.re = value >> 8 & 1;
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}
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if ((mask & 0x00FF) == 0) {
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sim->vip.dpctrl.disp = value >> 1 & 1;
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sim->vip.dp.disp = value >> 1 & 1;
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/* if (value & 1) {} TODO: DPRST */
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}
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break;
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@ -238,9 +293,9 @@ static void vipWriteIO(
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case 0x5F842>>1: /* XPCTRL */
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if ((mask & 0xFF00) == 0)
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sim->vip.xpctrl.sbcmp = value >> 8 & 31;
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sim->vip.xp.sbcmp = value >> 8 & 31;
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if ((mask & 0x00FF) == 0) {
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sim->vip.xpctrl.xpen = value >> 1 & 1;
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sim->vip.xp.xpen = value >> 1 & 1;
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/* if (value & 1) TODO: XPRST */
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}
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break;
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@ -292,13 +347,138 @@ static void vipWriteIO(
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/***************************** Callback Handlers *****************************/
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/* Prepare to handle an exception */
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#ifndef VB_DIRECT_FRAME
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#define VB_ON_FRAME sim->onFrame
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#else
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extern int VB_DIRECT_FRAME(VB *);
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#define VB_ON_FRAME VB_DIRECT_FRAME
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#endif
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static int vipOnFrame(VB *sim) {
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return sim->onFrame != NULL && VB_ON_FRAME(sim);
|
||||
}
|
||||
#undef VB_ON_FRAME
|
||||
|
||||
|
||||
|
||||
/***************************** Library Functions *****************************/
|
||||
|
||||
/* Display processor */
|
||||
static int vipEmulateDisplay(VB *sim, uint32_t clocks) {
|
||||
|
||||
/* Process all clocks */
|
||||
while (clocks != 0) {
|
||||
|
||||
/* The next event is after the time remaining */
|
||||
if (sim->vip.dp.clocks > clocks) {
|
||||
sim->vip.dp.clocks -= clocks;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Advance forward the component's number of clocks */
|
||||
clocks -= sim->vip.dp.clocks;
|
||||
sim->vip.dp.clocks = 0;
|
||||
|
||||
/* Processing by operation phase */
|
||||
switch (sim->vip.dp.step) {
|
||||
|
||||
case 0: /* 0ms - FCLK rising edge */
|
||||
sim->vip.dp.clocks = vipClocksMs(3);
|
||||
sim->vip.dp.fclk = 1;
|
||||
sim->vip.dp.step = 1;
|
||||
vipThrow(sim, 0x0010); /* FRAMESTART */
|
||||
/* TODO: Initiate drawing, throw GAMESTART */
|
||||
/* ELSE: Set OVERTIME, throw TIMEERR */
|
||||
break;
|
||||
|
||||
/* 0ms-3ms - Idle */
|
||||
|
||||
case 1: /* 3ms - L*BSY rising edge */
|
||||
if (sim->vip.dp.buffer == 0)
|
||||
sim->vip.dp.l0bsy = 1;
|
||||
else sim->vip.dp.l1bsy = 1;
|
||||
sim->vip.dp.column = 0;
|
||||
sim->vip.dp.cta = 0x3DC00 | (uint32_t)sim->vip.cta.cta_l<<1;
|
||||
sim->vip.dp.step = 2;
|
||||
vipComputeBrightness(sim);
|
||||
|
||||
/* Fallthrough */
|
||||
case 2: /* 3ms-8ms - Display left frame buffer */
|
||||
if ((sim->vip.dp.column & 3) == 0)
|
||||
vipComputeBrightness(sim);
|
||||
vipTransferColumn(sim, 0);
|
||||
sim->vip.dp.clocks =
|
||||
260 + (0xA94 >> sim->vip.dp.column % 12 & 1);
|
||||
sim->vip.dp.column++;
|
||||
if ((sim->vip.dp.column & 3) == 0)
|
||||
sim->vip.dp.cta -= 2;
|
||||
if (sim->vip.dp.column == 384)
|
||||
sim->vip.dp.step = 3;
|
||||
break;
|
||||
|
||||
case 3: /* 8ms - L*BSY falling edge */
|
||||
if (sim->vip.dp.buffer == 0)
|
||||
sim->vip.dp.l0bsy = 0;
|
||||
else sim->vip.dp.l1bsy = 0;
|
||||
sim->vip.dp.clocks = vipClocksMs(2);
|
||||
sim->vip.dp.step = 4;
|
||||
vipThrow(sim, 0x0002); /* LFBEND */
|
||||
break;
|
||||
|
||||
/* 8ms-10ms - Idle */
|
||||
|
||||
case 4: /* 10ms - FCLK falling edge */
|
||||
sim->vip.dp.clocks = vipClocksMs(3);
|
||||
sim->vip.dp.fclk = 0;
|
||||
sim->vip.dp.step = 5;
|
||||
break;
|
||||
|
||||
/* 10ms-13ms - Idle */
|
||||
|
||||
case 5: /* 13ms - R*BSY rising edge */
|
||||
if (sim->vip.dp.buffer == 0)
|
||||
sim->vip.dp.r0bsy = 1;
|
||||
else sim->vip.dp.r1bsy = 1;
|
||||
sim->vip.dp.column = 0;
|
||||
sim->vip.dp.cta = 0x3DE00 | (uint32_t)sim->vip.cta.cta_r<<1;
|
||||
sim->vip.dp.step = 6;
|
||||
|
||||
/* Fallthrough */
|
||||
case 6: /* 13ms-18ms - Display right frame buffer */
|
||||
vipTransferColumn(sim, 1);
|
||||
sim->vip.dp.clocks =
|
||||
260 + (0xA94 >> sim->vip.dp.column % 12 & 1);
|
||||
sim->vip.dp.column++;
|
||||
if (sim->vip.dp.column == 384)
|
||||
sim->vip.dp.step = 7;
|
||||
break;
|
||||
|
||||
case 7: /* 18ms - R*BSY falling edge */
|
||||
if (sim->vip.dp.buffer == 0)
|
||||
sim->vip.dp.r0bsy = 0;
|
||||
else sim->vip.dp.r1bsy = 0;
|
||||
sim->vip.dp.clocks = vipClocksMs(2);
|
||||
sim->vip.dp.step = 0;
|
||||
vipThrow(sim, 0x0004); /* RFBEND */
|
||||
if (vipOnFrame(sim))
|
||||
return 1;
|
||||
break;
|
||||
|
||||
/* 18ms-20ms - Idle */
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Process component */
|
||||
static int vipEmulate(VB *sim, uint32_t clocks) {
|
||||
(void) sim;
|
||||
(void) clocks;
|
||||
return 0;
|
||||
int brk = vipEmulateDisplay(sim, clocks);
|
||||
/*vipEmulateDrawing(sim, clocks);*/
|
||||
return brk;
|
||||
}
|
||||
|
||||
/* Read a typed value from the VIP bus */
|
||||
|
|
@ -307,10 +487,9 @@ static void vipRead(VB *sim, uint32_t address, int type, int32_t *value) {
|
|||
/* Working variables */
|
||||
address &= 0x0007FFFF;
|
||||
|
||||
/* VRAM */
|
||||
if (address < 0x40000) {
|
||||
*value = busReadBuffer(&sim->vip.vram[address], type);
|
||||
}
|
||||
/* RAM */
|
||||
if (address < 0x40000)
|
||||
*value = busReadBuffer(&sim->vip.ram[address], type);
|
||||
|
||||
/* Unmapped */
|
||||
else if (address < 0x5E000)
|
||||
|
|
@ -327,7 +506,7 @@ static void vipRead(VB *sim, uint32_t address, int type, int32_t *value) {
|
|||
/* Mirrors of character memory */
|
||||
else {
|
||||
address = 0x06000 | (address << 2 & 0x18000) | (address & 0x01FFF);
|
||||
*value = busReadBuffer(&sim->vip.vram[address], type);
|
||||
*value = busReadBuffer(&sim->vip.ram[address], type);
|
||||
}
|
||||
|
||||
}
|
||||
|
|
@ -337,31 +516,33 @@ static void vipReset(VB *sim) {
|
|||
int x, y; /* Iterators */
|
||||
|
||||
/* Normal */
|
||||
sim->vip.dpctrl.disp = 0;
|
||||
sim->vip.dpctrl.re = 0;
|
||||
sim->vip.dpctrl.synce = 0;
|
||||
sim->vip.dp.disp = 0;
|
||||
sim->vip.dp.re = 0;
|
||||
sim->vip.dp.synce = 0;
|
||||
sim->vip.intenb = 0x0000;
|
||||
sim->vip.xpctrl.xpen = 0;
|
||||
sim->vip.xp.xpen = 0;
|
||||
|
||||
/* Extra (the hardware does not do this) */
|
||||
for (x = 0; x < 0x80000; x++)
|
||||
sim->vip.ram[x] = 0;
|
||||
sim->vip.bkcol = 0;
|
||||
sim->vip.cta.cta_l = 0;
|
||||
sim->vip.cta.cta_r = 0;
|
||||
sim->vip.cta.cta_l = 0xFA;
|
||||
sim->vip.cta.cta_r = 0xFA;
|
||||
sim->vip.frmcyc = 0;
|
||||
sim->vip.intpnd = 0x0000;
|
||||
sim->vip.dpctrl.fclk = 0;
|
||||
sim->vip.dpctrl.l0bsy = 0;
|
||||
sim->vip.dpctrl.l1bsy = 0;
|
||||
sim->vip.dpctrl.lock = 0;
|
||||
sim->vip.dpctrl.r0bsy = 0;
|
||||
sim->vip.dpctrl.r1bsy = 0;
|
||||
sim->vip.dpctrl.scanrdy = 0;
|
||||
sim->vip.xpctrl.f0bsy = 0;
|
||||
sim->vip.xpctrl.f1bsy = 0;
|
||||
sim->vip.xpctrl.overtime = 0;
|
||||
sim->vip.xpctrl.sbcmp = 0;
|
||||
sim->vip.xpctrl.sbcount = 0;
|
||||
sim->vip.xpctrl.sbout = 0;
|
||||
sim->vip.dp.fclk = 0;
|
||||
sim->vip.dp.l0bsy = 0;
|
||||
sim->vip.dp.l1bsy = 0;
|
||||
sim->vip.dp.lock = 0;
|
||||
sim->vip.dp.r0bsy = 0;
|
||||
sim->vip.dp.r1bsy = 0;
|
||||
sim->vip.dp.scanrdy = 0;
|
||||
sim->vip.xp.f0bsy = 0;
|
||||
sim->vip.xp.f1bsy = 0;
|
||||
sim->vip.xp.overtime = 0;
|
||||
sim->vip.xp.sbcmp = 0;
|
||||
sim->vip.xp.sbcount = 0;
|
||||
sim->vip.xp.sbout = 0;
|
||||
for (x = 0; x < 4; x++) {
|
||||
sim->vip.brtRest[x] = 0;
|
||||
sim->vip.spt [x] = 0;
|
||||
|
|
@ -371,24 +552,28 @@ static void vipReset(VB *sim) {
|
|||
}
|
||||
}
|
||||
|
||||
/* Other */
|
||||
sim->vip.dp.brt[0] = 0;
|
||||
sim->vip.dp.clocks = 0;
|
||||
sim->vip.dp.step = 0;
|
||||
}
|
||||
|
||||
/* Determine how many clocks are guaranteed to process */
|
||||
static uint32_t vipUntil(VB *sim, uint32_t clocks) {
|
||||
(void) sim;
|
||||
/* Don't allow clocks to exceed interrupt conditions, even if disabled */
|
||||
return clocks;
|
||||
}
|
||||
|
||||
/* Write a typed value to the VIP bus */
|
||||
static void vipWrite(VB*sim,uint32_t address,int type,int32_t value,int debug){
|
||||
(void) debug;
|
||||
|
||||
/* Working variables */
|
||||
address &= 0x0007FFFF;
|
||||
|
||||
/* VRAM */
|
||||
/* RAM */
|
||||
if (address < 0x40000)
|
||||
busWriteBuffer(&sim->vip.vram[address], type, value);
|
||||
busWriteBuffer(&sim->vip.ram[address], type, value);
|
||||
|
||||
/* Unmapped */
|
||||
else if (address < 0x5E000)
|
||||
|
|
@ -405,7 +590,7 @@ static void vipWrite(VB*sim,uint32_t address,int type,int32_t value,int debug){
|
|||
/* Mirrors of character memory */
|
||||
else {
|
||||
address = 0x06000 | (address << 2 & 0x18000) | (address & 0x01FFF);
|
||||
busWriteBuffer(&sim->vip.vram[address], type, value);
|
||||
busWriteBuffer(&sim->vip.ram[address], type, value);
|
||||
}
|
||||
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue