diff --git a/core/cpu.c b/core/cpu.c
index 4bcbc49..56dd715 100644
--- a/core/cpu.c
+++ b/core/cpu.c
@@ -234,7 +234,7 @@ static int cpuOnExecute(VB *sim) {
     #define VB_ON_READ VB_DIRECT_READ
 #endif
 static int cpuRead(VB *sim, uint32_t address, int type, int32_t *value) {
-    uint32_t cycles = 4; /* TODO: Research this */
+    uint32_t cycles = 0; /* TODO: Research this */
 
     /* Retrieve the value from the simulation state directly */
     busRead(sim, address, type, value);
@@ -289,7 +289,7 @@ static int cpuReadFetch(VB *sim, int fetch, uint32_t address, int32_t *value) {
 #endif
 static int cpuWrite(VB *sim, uint32_t address, int type, int32_t value) {
     int      cancel = 0;
-    uint32_t cycles = 3; /* TODO: Research this */
+    uint32_t cycles = 0; /* TODO: Research this */
 
     /* Reset pseudo-halt */
     if (sim->ph.enabled)
diff --git a/core/vsu.c b/core/vsu.c
index 8701761..905bbb3 100644
--- a/core/vsu.c
+++ b/core/vsu.c
@@ -548,6 +548,7 @@ static void vsuReset(VB *sim) {
 
 /* Write a typed value to the VSU bus */
 static void vsuWrite(VB*sim,uint32_t address,int type,int32_t value,int debug){
+    (void) type;
 
     /* Unmapped */
     if (address & 1)