Overplane and sweep fixes
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parent
c06da32321
commit
8f9950f39e
33
core/vip.c
33
core/vip.c
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@ -42,14 +42,14 @@ static const uint8_t BG_TEMPLATES[][64] = {
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/* 8-bit color magnitude by brightness level */
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static const uint8_t BRIGHT8[] = {
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0, 10, 16, 21, 25, 30, 33, 37, 40, 44, 47, 50, 53, 56, 59, 61,
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64, 67, 69, 72, 74, 77, 79, 82, 84, 86, 89, 91, 93, 95, 97,100,
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102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,131,
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133,135,137,139,141,142,144,146,148,149,151,153,155,156,158,160,
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161,163,165,166,168,170,171,173,175,176,178,179,181,183,184,186,
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187,189,190,192,194,195,197,198,200,201,203,204,206,207,209,210,
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212,213,215,216,217,219,220,222,223,225,226,227,229,230,232,233,
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235,236,237,239,240,241,243,244,246,247,248,250,251,252,254,255
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0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30,
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32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62,
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64, 66, 68, 70, 72, 74, 76, 78, 80, 82, 84, 86, 88, 90, 92, 94,
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96, 98,100,102,104,106,108,110,112,114,116,118,120,122,124,126,
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129,131,133,135,137,139,141,143,145,147,149,151,153,155,157,159,
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161,163,165,167,169,171,173,175,177,179,181,183,185,187,189,191,
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193,195,197,199,201,203,205,207,209,211,213,215,217,219,221,223,
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225,227,229,231,233,235,237,239,241,243,245,247,249,251,253,255
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};
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@ -68,10 +68,9 @@ static int32_t vipReadPalette(uint8_t *entries) {
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/* Raise an interrupt request */
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static void vipThrow(VB *sim, uint16_t cause) {
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if (!(sim->vip.intenb & cause))
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return;
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sim->vip.intpnd |= cause;
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sim->cpu.irq |= 0x0010;
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if (sim->vip.intenb & cause)
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sim->cpu.irq |= 0x0010;
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}
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/* Write a palette */
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@ -422,10 +421,9 @@ static void vipTransferColumn(VB *sim, int32_t eye) {
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/* Output is disabled */
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if ((sim->vip.dp.disp & sim->vip.dp.synce) == 0) {
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for (z = 0; z < 0x15000; z += 4) {
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busWriteBuffer(dest, VB_S32, 0);
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dest += 4;
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}
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for (y = 0; y < 224; y += 16)
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for (z = 0; z < 16; z++, dest += 384)
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*dest = 0;
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return;
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}
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@ -838,7 +836,10 @@ static void vipDrawWorld(VB *sim, uint8_t *world, uint16_t attr) {
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bx &= bgw;
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by &= bgh;
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}
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else cell = over;
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else {
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cell = over;
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continue; /* TODO: Research overplane */
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}
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}
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/* Locate the cell in the BG map */
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20
core/vsu.c
20
core/vsu.c
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@ -164,7 +164,7 @@ static void vsuEmulateChannel(VB *sim, int index, uint32_t clocks) {
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if (!chan->int_.enb)
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return;
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sim->vsu.freqmod.clocks = (uint32_t) sim->vsu.freqmod.interval *
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(sim->vsu.freqmod.clk == 0 ? 19201 : 153610);
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(sim->vsu.freqmod.clk == 0 ? 19200 : 153600);
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}
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} while (clocks != 0);
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@ -207,6 +207,8 @@ static void vsuWriteEV0(VB *sim, int index, uint8_t value) {
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chan->env.interval = value & 7;
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chan->env.value = value >> 4 & 15;
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chan->env.reload = chan->env.value;
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if (index == 4)
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vsuNextFreqMod(sim, chan);
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/* Configure state */
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chan->env.clocks = 307220 * ((uint32_t) chan->env.interval + 1);
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@ -243,6 +245,8 @@ static void vsuWriteFQH(VB *sim, int index, uint16_t value) {
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value = value << 8 & 0x0700;
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chan->freq.current = (chan->freq.current & 0x00FF) | value;
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chan->freq.written = (chan->freq.written & 0x00FF) | value;
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if (index == 4)
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vsuNextFreqMod(sim, chan);
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}
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/* Write a value to S*FQL */
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@ -250,6 +254,8 @@ static void vsuWriteFQL(VB *sim, int index, uint8_t value) {
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Channel *chan = &sim->vsu.channels[index];
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chan->freq.current = (chan->freq.current & 0x0700) | value;
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chan->freq.written = (chan->freq.written & 0x0700) | value;
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if (index == 4)
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vsuNextFreqMod(sim, chan);
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}
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/* Write a value to S*INT */
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@ -274,7 +280,7 @@ static void vsuWriteINT(VB *sim, int index, uint8_t value) {
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}
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if (index == 4) {
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sim->vsu.freqmod.clocks = (uint32_t) sim->vsu.freqmod.interval *
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(sim->vsu.freqmod.clk ? 153610 : 19201);
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(sim->vsu.freqmod.clk == 0 ? 19200 : 153600);
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sim->vsu.freqmod.sample = 0;
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}
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@ -297,14 +303,14 @@ static void vsuWriteSWP(VB *sim, uint8_t value) {
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uint32_t clocks;
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/* Parse fields */
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sim->vsu.freqmod.clk = value >> 7 & 1;
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sim->vsu.freqmod.dir = value >> 3 & 1;
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sim->vsu.freqmod.interval = value >> 4 & 15;
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sim->vsu.freqmod.shift = value & 7;
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sim->vsu.freqmod.clk = value >> 7 & 1;
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sim->vsu.freqmod.dir = value >> 3 & 1;
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sim->vsu.freqmod.interval = value >> 4 & 7;
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sim->vsu.freqmod.shift = value & 7;
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/* Configure state */
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clocks = (uint32_t) sim->vsu.freqmod.interval *
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(sim->vsu.freqmod.clk ? 153610 : 19201);
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(sim->vsu.freqmod.clk == 0 ? 19200 : 153600);
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if (clocks < sim->vsu.freqmod.clocks)
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sim->vsu.freqmod.clocks = clocks;
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}
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