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Overplane and sweep fixes

This commit is contained in:
Guy Perfect 2024-10-22 19:53:27 -05:00
parent c06da32321
commit 8f9950f39e
2 changed files with 30 additions and 23 deletions
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31
core/vip.c
View File

@ -42,14 +42,14 @@ static const uint8_t BG_TEMPLATES[][64] = {
/* 8-bit color magnitude by brightness level */
static const uint8_t BRIGHT8[] = {
0, 10, 16, 21, 25, 30, 33, 37, 40, 44, 47, 50, 53, 56, 59, 61,
64, 67, 69, 72, 74, 77, 79, 82, 84, 86, 89, 91, 93, 95, 97,100,
102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,131,
133,135,137,139,141,142,144,146,148,149,151,153,155,156,158,160,
161,163,165,166,168,170,171,173,175,176,178,179,181,183,184,186,
187,189,190,192,194,195,197,198,200,201,203,204,206,207,209,210,
212,213,215,216,217,219,220,222,223,225,226,227,229,230,232,233,
235,236,237,239,240,241,243,244,246,247,248,250,251,252,254,255
0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30,
32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62,
64, 66, 68, 70, 72, 74, 76, 78, 80, 82, 84, 86, 88, 90, 92, 94,
96, 98,100,102,104,106,108,110,112,114,116,118,120,122,124,126,
129,131,133,135,137,139,141,143,145,147,149,151,153,155,157,159,
161,163,165,167,169,171,173,175,177,179,181,183,185,187,189,191,
193,195,197,199,201,203,205,207,209,211,213,215,217,219,221,223,
225,227,229,231,233,235,237,239,241,243,245,247,249,251,253,255
};
@ -68,9 +68,8 @@ static int32_t vipReadPalette(uint8_t *entries) {
/* Raise an interrupt request */
static void vipThrow(VB *sim, uint16_t cause) {
if (!(sim->vip.intenb & cause))
return;
sim->vip.intpnd |= cause;
if (sim->vip.intenb & cause)
sim->cpu.irq |= 0x0010;
}
@ -422,10 +421,9 @@ static void vipTransferColumn(VB *sim, int32_t eye) {
/* Output is disabled */
if ((sim->vip.dp.disp & sim->vip.dp.synce) == 0) {
for (z = 0; z < 0x15000; z += 4) {
busWriteBuffer(dest, VB_S32, 0);
dest += 4;
}
for (y = 0; y < 224; y += 16)
for (z = 0; z < 16; z++, dest += 384)
*dest = 0;
return;
}
@ -838,7 +836,10 @@ static void vipDrawWorld(VB *sim, uint8_t *world, uint16_t attr) {
bx &= bgw;
by &= bgh;
}
else cell = over;
else {
cell = over;
continue; /* TODO: Research overplane */
}
}
/* Locate the cell in the BG map */

14
core/vsu.c
View File

@ -164,7 +164,7 @@ static void vsuEmulateChannel(VB *sim, int index, uint32_t clocks) {
if (!chan->int_.enb)
return;
sim->vsu.freqmod.clocks = (uint32_t) sim->vsu.freqmod.interval *
(sim->vsu.freqmod.clk == 0 ? 19201 : 153610);
(sim->vsu.freqmod.clk == 0 ? 19200 : 153600);
}
} while (clocks != 0);
@ -207,6 +207,8 @@ static void vsuWriteEV0(VB *sim, int index, uint8_t value) {
chan->env.interval = value & 7;
chan->env.value = value >> 4 & 15;
chan->env.reload = chan->env.value;
if (index == 4)
vsuNextFreqMod(sim, chan);
/* Configure state */
chan->env.clocks = 307220 * ((uint32_t) chan->env.interval + 1);
@ -243,6 +245,8 @@ static void vsuWriteFQH(VB *sim, int index, uint16_t value) {
value = value << 8 & 0x0700;
chan->freq.current = (chan->freq.current & 0x00FF) | value;
chan->freq.written = (chan->freq.written & 0x00FF) | value;
if (index == 4)
vsuNextFreqMod(sim, chan);
}
/* Write a value to S*FQL */
@ -250,6 +254,8 @@ static void vsuWriteFQL(VB *sim, int index, uint8_t value) {
Channel *chan = &sim->vsu.channels[index];
chan->freq.current = (chan->freq.current & 0x0700) | value;
chan->freq.written = (chan->freq.written & 0x0700) | value;
if (index == 4)
vsuNextFreqMod(sim, chan);
}
/* Write a value to S*INT */
@ -274,7 +280,7 @@ static void vsuWriteINT(VB *sim, int index, uint8_t value) {
}
if (index == 4) {
sim->vsu.freqmod.clocks = (uint32_t) sim->vsu.freqmod.interval *
(sim->vsu.freqmod.clk ? 153610 : 19201);
(sim->vsu.freqmod.clk == 0 ? 19200 : 153600);
sim->vsu.freqmod.sample = 0;
}
@ -299,12 +305,12 @@ static void vsuWriteSWP(VB *sim, uint8_t value) {
/* Parse fields */
sim->vsu.freqmod.clk = value >> 7 & 1;
sim->vsu.freqmod.dir = value >> 3 & 1;
sim->vsu.freqmod.interval = value >> 4 & 15;
sim->vsu.freqmod.interval = value >> 4 & 7;
sim->vsu.freqmod.shift = value & 7;
/* Configure state */
clocks = (uint32_t) sim->vsu.freqmod.interval *
(sim->vsu.freqmod.clk ? 153610 : 19201);
(sim->vsu.freqmod.clk == 0 ? 19200 : 153600);
if (clocks < sim->vsu.freqmod.clocks)
sim->vsu.freqmod.clocks = clocks;
}