Tweaks in preparation for web module

2024-10-31 19:14:18 -05:00
parent b134903878
commit ae22c95dbe
6 changed files with 75 additions and 40 deletions
@@ -142,6 +142,7 @@ static uint32_t phDPSTTS(VB *sim) {
        case 3: /* 8ms - L*BSY falling edge */
        case 6: /* 13ms-18ms - Display right frame buffer */
        case 7: /* 18ms - R*BSY falling edge */
+        case 8: /* 20ms - Display interval complete */
            return sim->vip.dp.until;
    }
    /* case 1: 3ms - L*BSY rising edge */