Tweaks in preparation for web module

2024-10-31 19:14:18 -05:00
parent b134903878
commit ae22c95dbe
6 changed files with 75 additions and 40 deletions
@@ -368,8 +368,21 @@ static void vsuEmulate(VB *sim, uint32_t clocks) {
                sim->vsu.out.samples != NULL &&
                sim->vsu.out.offset >> 1 < sim->vsu.out.capacity
            ) {
-                sim->vsu.out.samples[sim->vsu.out.offset++] =
-                    (int16_t) (o0 * 32767.0f + (o0 < 0.0f ? -0.5f : +0.5f));
+
+                /* Processing by data type*/
+                switch (sim->vsu.out.type) {
+                    case VB_S16:
+                        ((int16_t *) sim->vsu.out.samples)
+                        [sim->vsu.out.offset++] = (int16_t)
+                        (o0 * 32767.0f + (o0 < 0.0f ? -0.5f : +0.5f));
+                        break;
+                    case VB_F32:
+                        ((float *) sim->vsu.out.samples)
+                        [sim->vsu.out.offset++] = o0;
+                        break;
+                }
+
+                /* Invoke the samples callback */
                if (
                    e == 1 &&
                    sim->vsu.out.offset >> 1 == sim->vsu.out.capacity