From bcd80d291b1be0e334bd5da481ca69211b16e6b0 Mon Sep 17 00:00:00 2001
From: Guy Perfect <guytpk@gmail.com>
Date: Wed, 23 Oct 2024 21:16:35 -0500
Subject: [PATCH] Pseudo-halt timing fix

---
 core/cpu.c         |  2 +-
 core/pseudo-halt.c |  4 +++-
 core/vb.c          | 22 ++++++++++++++++------
 3 files changed, 20 insertions(+), 8 deletions(-)

diff --git a/core/cpu.c b/core/cpu.c
index 2eda606..39e978e 100644
--- a/core/cpu.c
+++ b/core/cpu.c
@@ -1860,7 +1860,7 @@ static uint32_t cpuUntil(VB *sim, uint32_t clocks) {
 
     /* Pseudo-halting */
     if (sim->cpu.operation == CPU_PHALT) {
-        if (sim->cpu.clocks == 0) /* Requires an interrupt */
+        if (sim->cpu.clocks == 0)
             return clocks;
     }
 
diff --git a/core/pseudo-halt.c b/core/pseudo-halt.c
index c65d26c..fcdacfc 100644
--- a/core/pseudo-halt.c
+++ b/core/pseudo-halt.c
@@ -121,11 +121,12 @@ static int phMatches(VB *sim, uint32_t address, int type, int32_t value) {
     return
         sim->ph.adtre == sim->cpu.adtre                     &&
         sim->ph.chcw  == cpuGetSystemRegister(sim, VB_CHCW) &&
+        sim->ph.ecr   == cpuGetSystemRegister(sim, VB_ECR)  &&
         sim->ph.eipc  == sim->cpu.eipc                      &&
         sim->ph.eipsw == sim->cpu.eipsw                     &&
         sim->ph.fepc  == sim->cpu.fepc                      &&
         sim->ph.fepsw == sim->cpu.fepsw                     &&
-        sim->ph.psw   == cpuGetSystemRegister(sim, VB_PSW)
+        sim->ph.psw   == cpuGetSystemRegister(sim, VB_PSW )
     ;
 }
 
@@ -229,6 +230,7 @@ static int phAssess(VB *sim, uint32_t address, int type, int32_t value) {
             sim->ph.program[x - 1] = sim->cpu.program[x];
         sim->ph.adtre = sim->cpu.adtre;
         sim->ph.chcw  = cpuGetSystemRegister(sim, VB_CHCW);
+        sim->ph.ecr   = cpuGetSystemRegister(sim, VB_ECR);
         sim->ph.eipc  = sim->cpu.eipc;
         sim->ph.eipsw = sim->cpu.eipsw;
         sim->ph.fepc  = sim->cpu.fepc;
diff --git a/core/vb.c b/core/vb.c
index 61f7e89..587e419 100644
--- a/core/vb.c
+++ b/core/vb.c
@@ -322,6 +322,7 @@ struct VB {
         /* CPU snapshot */
         uint32_t adtre;
         uint32_t chcw;
+        uint32_t ecr;
         uint32_t eipc;
         uint32_t eipsw;
         uint32_t fepc;
@@ -381,12 +382,21 @@ static int32_t SignExtend(int32_t value, int32_t bits) {
 
 /* Process a simulation for a given number of clocks */
 static int sysEmulate(VB *sim, uint32_t clocks) {
-    int ret;
-    ret  = cpuEmulate(sim, clocks);
-           padEmulate(sim, clocks);
-           tmrEmulate(sim, clocks);
-           vsuEmulate(sim, clocks);
-    ret |= vipEmulate(sim, clocks);
+    int ret = 0;
+
+    /* CPU is in a pseudo-halt state that requires an interrupt to exit */
+    int never =
+        sim->cpu.operation == CPU_PHALT &&
+        sim->ph.operation  == PH_NEVER
+    ;
+
+    /* Process all components */
+    if (!never) ret  = cpuEmulate(sim, clocks);
+                       padEmulate(sim, clocks);
+                       tmrEmulate(sim, clocks);
+                       vsuEmulate(sim, clocks);
+                ret |= vipEmulate(sim, clocks);
+    if ( never) ret |= cpuEmulate(sim, clocks);
     return ret;
 }