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Even more VSU edge cases

This commit is contained in:
Guy Perfect 2025-03-01 15:42:16 -06:00
parent 459a16076a
commit dd1045553b
2 changed files with 24 additions and 15 deletions
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1
core/vb.c
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@ -362,6 +362,7 @@ struct VB {
/* Other state */ /* Other state */
uint32_t clocks; /* Clocks until modification */ uint32_t clocks; /* Clocks until modification */
uint8_t modmask; /* Modifications masked */ uint8_t modmask; /* Modifications masked */
uint8_t freqmask; /* Frequency mask */
uint16_t next; /* Next frequency value */ uint16_t next; /* Next frequency value */
int sample; /* Current sample index */ int sample; /* Current sample index */
} freqmod; } freqmod;

26
core/vsu.c
View File

@ -83,11 +83,11 @@ static void vsuNextFreqMod(VB *sim, Channel *chan) {
/* Modulation */ /* Modulation */
else { else {
next = (int32_t) chan->freq.written + next = (int32_t) chan->freq.written +
sim->vsu.modulation[sim->vsu.freqmod.sample]; sim->vsu.modulation[sim->vsu.freqmod.sample] & 0x7FF;
if (next < 0) if (sim->vsu.freqmod.freqmask == 1)
next = 0; next = (next & 0x700) | (chan->freq.written & 0x0FF);
if (next > 2047) else if (sim->vsu.freqmod.freqmask == 2) {
next = 2047; next = (next & 0x0FF) | (chan->freq.written & 0x700);
} }
/* Configure state */ /* Configure state */
@ -257,7 +257,9 @@ static void vsuWriteFQH(VB *sim, int index, uint16_t value) {
value = value << 8 & 0x0700; value = value << 8 & 0x0700;
chan->freq.current = (chan->freq.current & 0x00FF) | value; chan->freq.current = (chan->freq.current & 0x00FF) | value;
chan->freq.written = (chan->freq.written & 0x00FF) | value; chan->freq.written = (chan->freq.written & 0x00FF) | value;
if (index == 4) if (index != 4)
return;
sim->vsu.freqmod.freqmask = 2;
vsuNextFreqMod(sim, chan); vsuNextFreqMod(sim, chan);
} }
@ -266,7 +268,9 @@ static void vsuWriteFQL(VB *sim, int index, uint8_t value) {
Channel *chan = &sim->vsu.channels[index]; Channel *chan = &sim->vsu.channels[index];
chan->freq.current = (chan->freq.current & 0x0700) | value; chan->freq.current = (chan->freq.current & 0x0700) | value;
chan->freq.written = (chan->freq.written & 0x0700) | value; chan->freq.written = (chan->freq.written & 0x0700) | value;
if (index == 4) if (index != 4)
return;
sim->vsu.freqmod.freqmask = 1;
vsuNextFreqMod(sim, chan); vsuNextFreqMod(sim, chan);
} }
@ -510,6 +514,7 @@ static void vsuReset(VB *sim) {
sim->vsu.freqmod.func = 0; sim->vsu.freqmod.func = 0;
sim->vsu.freqmod.interval = 0; sim->vsu.freqmod.interval = 0;
sim->vsu.freqmod.modmask = 0; sim->vsu.freqmod.modmask = 0;
sim->vsu.freqmod.freqmask = 0;
sim->vsu.freqmod.next = 0; sim->vsu.freqmod.next = 0;
sim->vsu.freqmod.rep = 0; sim->vsu.freqmod.rep = 0;
sim->vsu.freqmod.sample = 0; sim->vsu.freqmod.sample = 0;
@ -536,11 +541,14 @@ static void vsuWrite(VB*sim,uint32_t address,int type,int32_t value,int debug){
} }
/* Unmapped */ /* Unmapped */
if (address & 3) if (address & 1)
return; return;
/* Working variables */ /* Working variables */
address &= 0x7FF; address &= 0x7FC;
/* Clear frequency mask */
sim->vsu.freqmod.freqmask = 0;
/* Wave memory */ /* Wave memory */
if (address < 0x280) { if (address < 0x280) {