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Implement communication port

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This commit is contained in:
GuyPerfect
2024-10-28 19:11:33 -05:00
parent da001e02cd
commit e828d99da1
5 changed files with 261 additions and 29 deletions
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core/bus.c
+17 -16
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@@ -95,17 +95,17 @@ static int32_t busReadMisc(VB *sim, uint8_t address, int type) {
/* Access by register */
switch (address >> 2 & 15) {
case 0x00>>2: break; /* CCR */
case 0x04>>2: break; /* CCSR */
case 0x08>>2: break; /* CDTR */
case 0x0C>>2: break; /* CDRR */
case 0x10>>2: return sim->pad.sdlr; /* SDLR */
case 0x14>>2: return sim->pad.sdhr; /* SDHR */
case 0x18>>2: return sim->tmr.counter & 0xFF; /* TLR */
case 0x1C>>2: return sim->tmr.counter >> 8 & 0xFF; /* THR */
case 0x20>>2: return tmrReadControl(sim); /* TCR */
case 0x24>>2: return sim->wcr; /* WCR */
case 0x28>>2: return padReadControl(sim); /* SCR */
case 0x00>>2: return extReadCCR(sim); /* CCR */
case 0x04>>2: return extReadCCSR(sim); /* CCSR */
case 0x08>>2: return sim->ext.cdtr; /* CDTR */
case 0x0C>>2: return sim->ext.cdrr; /* CDRR */
case 0x10>>2: return sim->pad.sdlr; /* SDLR */
case 0x14>>2: return sim->pad.sdhr; /* SDHR */
case 0x18>>2: return sim->tmr.counter & 0xFF; /* TLR */
case 0x1C>>2: return sim->tmr.counter >> 8 & 0xFF; /* THR */
case 0x20>>2: return tmrReadControl(sim); /* TCR */
case 0x28>>2: return padReadControl(sim); /* SCR */
case 0x24>>2: return sim->wcr.exp1w << 1 | sim->wcr.rom1w; /* WCR */
}
/* Unmapped */
@@ -123,15 +123,16 @@ static void busWriteMisc(VB *sim, uint8_t address, int type, int32_t value) {
/* Access by register */
switch (address >> 2 & 15) {
case 0x00>>2: break; /* CCR */
case 0x04>>2: break; /* CCSR */
case 0x08>>2: break; /* CDTR */
case 0x0C>>2: break; /* CDRR */
case 0x00>>2: extWriteCCR (sim, value); break; /* CCR */
case 0x04>>2: extWriteCCSR(sim, value); break; /* CCSR */
case 0x08>>2: sim->ext.cdtr = value; break; /* CDTR */
case 0x18>>2: tmrWriteLow (sim, value); break; /* TLR */
case 0x1C>>2: tmrWriteHigh (sim, value); break; /* THR */
case 0x20>>2: tmrWriteControl(sim, value); break; /* TCR */
case 0x24>>2: sim->wcr = value & 3; break; /* WCR */
case 0x28>>2: padWriteControl(sim, value); break; /* SCR */
case 0x24>>2: /* WCR */
sim->wcr.exp1w = value >> 1 & 1;
sim->wcr.rom1w = value & 1;
}
}