Implement communication port
This commit is contained in:
parent
da001e02cd
commit
e828d99da1
33
core/bus.c
33
core/bus.c
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@ -95,17 +95,17 @@ static int32_t busReadMisc(VB *sim, uint8_t address, int type) {
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/* Access by register */
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switch (address >> 2 & 15) {
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case 0x00>>2: break; /* CCR */
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case 0x04>>2: break; /* CCSR */
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case 0x08>>2: break; /* CDTR */
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case 0x0C>>2: break; /* CDRR */
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case 0x10>>2: return sim->pad.sdlr; /* SDLR */
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case 0x14>>2: return sim->pad.sdhr; /* SDHR */
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case 0x18>>2: return sim->tmr.counter & 0xFF; /* TLR */
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case 0x1C>>2: return sim->tmr.counter >> 8 & 0xFF; /* THR */
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case 0x20>>2: return tmrReadControl(sim); /* TCR */
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case 0x24>>2: return sim->wcr; /* WCR */
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case 0x28>>2: return padReadControl(sim); /* SCR */
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case 0x00>>2: return extReadCCR(sim); /* CCR */
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case 0x04>>2: return extReadCCSR(sim); /* CCSR */
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case 0x08>>2: return sim->ext.cdtr; /* CDTR */
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case 0x0C>>2: return sim->ext.cdrr; /* CDRR */
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case 0x10>>2: return sim->pad.sdlr; /* SDLR */
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case 0x14>>2: return sim->pad.sdhr; /* SDHR */
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case 0x18>>2: return sim->tmr.counter & 0xFF; /* TLR */
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case 0x1C>>2: return sim->tmr.counter >> 8 & 0xFF; /* THR */
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case 0x20>>2: return tmrReadControl(sim); /* TCR */
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case 0x28>>2: return padReadControl(sim); /* SCR */
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case 0x24>>2: return sim->wcr.exp1w << 1 | sim->wcr.rom1w; /* WCR */
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}
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/* Unmapped */
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@ -123,15 +123,16 @@ static void busWriteMisc(VB *sim, uint8_t address, int type, int32_t value) {
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/* Access by register */
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switch (address >> 2 & 15) {
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case 0x00>>2: break; /* CCR */
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case 0x04>>2: break; /* CCSR */
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case 0x08>>2: break; /* CDTR */
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case 0x0C>>2: break; /* CDRR */
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case 0x00>>2: extWriteCCR (sim, value); break; /* CCR */
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case 0x04>>2: extWriteCCSR(sim, value); break; /* CCSR */
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case 0x08>>2: sim->ext.cdtr = value; break; /* CDTR */
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case 0x18>>2: tmrWriteLow (sim, value); break; /* TLR */
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case 0x1C>>2: tmrWriteHigh (sim, value); break; /* THR */
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case 0x20>>2: tmrWriteControl(sim, value); break; /* TCR */
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case 0x24>>2: sim->wcr = value & 3; break; /* WCR */
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case 0x28>>2: padWriteControl(sim, value); break; /* SCR */
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case 0x24>>2: /* WCR */
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sim->wcr.exp1w = value >> 1 & 1;
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sim->wcr.rom1w = value & 1;
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}
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}
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@ -0,0 +1,162 @@
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/* This file is included into vb.c and cannot be compiled on its own. */
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#ifdef VBAPI
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/***************************** Callback Handlers *****************************/
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/* Prepare to handle an exception */
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#ifndef VB_DIRECT_LINK
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#define VB_ON_LINK sim1->onLink
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#else
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extern int VB_DIRECT_LINK(VB *, VB *, uint8_t *, uint8_t *);
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#define VB_ON_LINK VB_DIRECT_LINK
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#endif
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static int extOnLink(VB *sim1, VB *sim2, uint8_t *value1, uint8_t *value2) {
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return sim1->onLink != NULL && VB_ON_LINK(sim1, sim2, value1, value2);
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}
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#undef VB_ON_LINK
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/***************************** Library Functions *****************************/
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/* Process component */
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static int extEmulate(VB *sim, uint32_t clocks) {
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VB *peer; /* Communication peer */
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VB *sims[2]; /* Communication peers */
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uint8_t values[2]; /* Transmission values */
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int x; /* Iterator */
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/* Communication will not occur */
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if (!sim->ext.c_stat || sim->ext.c_clk_sel)
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return 0;
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/* Communication completes after time to process */
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if (sim->ext.clocks > clocks) {
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sim->ext.clocks -= clocks;
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return 0;
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}
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/* Exchange transmission data */
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sims [0] = sim;
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sims [1] = sim->peer;
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values[0] = sim->ext.cdtr;
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values[1] = sim->peer == NULL ? 0 : sim->peer->ext.cdtr;
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if (extOnLink(sim, sim->peer, &values[0], &values[1]))
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return 1;
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/* Update state */
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for (x = 0; x < 2; x++) {
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sim = sims[x];
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peer = sims[x ^ 1];
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if (sim == NULL)
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break;
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if (peer == NULL)
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peer = sim;
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/* Registers */
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sim->ext.cdrr = values[x ^ 1];
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sim->ext.c_irq |= !sim->ext.c_int_inh;
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sim->ext.c_stat = 0;
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sim->ext.cc_rd = sim->ext.cc_wr & peer->ext.cc_wr;
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sim->ext.cc_smp = sim->ext.cc_sig & peer->ext.cc_sig & sim->ext.cc_rd;
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sim->ext.cc_irq |= !sim->ext.cc_int_inh &&
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sim->ext.cc_smp == sim->ext.cc_int_lev;
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/* Interrupt */
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if (sim->ext.c_irq | sim->ext.cc_irq)
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sim->cpu.irq |= 0x0008;
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}
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return 0;
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}
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/* Read a value from CCR */
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static int32_t extReadCCR(VB *sim) {
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return 0x6D |
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sim->ext.c_int_inh << 7 |
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sim->ext.c_clk_sel << 4 |
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sim->ext.c_stat << 1
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;
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}
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/* Read a value from CCSR */
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static int32_t extReadCCSR(VB *sim) {
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return 0x60 |
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sim->ext.cc_int_inh << 7 |
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sim->ext.cc_int_lev << 4 |
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sim->ext.cc_sig << 3 |
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sim->ext.cc_smp << 2 |
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sim->ext.cc_wr << 1 |
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sim->ext.cc_rd
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;
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}
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/* Simulate a hardware reset */
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static void extReset(VB *sim) {
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/* Normal */
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sim->ext.c_clk_sel = 0;
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sim->ext.c_int_inh = 0;
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sim->ext.c_stat = 0;
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sim->ext.cc_int_inh = 1;
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sim->ext.cc_int_lev = 1;
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sim->ext.cc_sig = 1;
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sim->ext.cc_wr = 1;
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sim->ext.cdrr = 0x00;
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sim->ext.cdtr = 0x00;
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/* Other */
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sim->ext.c_irq = 0;
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sim->ext.cc_irq = 0;
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}
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/* Determine how many clocks are guaranteed to process */
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static uint32_t extUntil(VB *sim, uint32_t clocks) {
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return !sim->ext.c_stat || sim->ext.c_clk_sel || clocks < sim->ext.clocks ?
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clocks : sim->ext.clocks;
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}
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/* Write a value to CCR */
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static void extWriteCCR(VB *sim, uint8_t value) {
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/* Configure state */
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sim->ext.c_int_inh = value >> 7 & 1;
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sim->ext.c_clk_sel = value >> 4 & 1;
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/* Acknowledge interrupt */
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if (sim->ext.c_int_inh) {
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sim->ext.c_irq = 0;
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if (!sim->ext.cc_irq)
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sim->cpu.irq &= ~0x0008;
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}
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/* Do not initiate a communication */
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if (sim->ext.c_stat || (value & 0x04) == 0) /* C-Start */
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return;
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/* Initiate a communication */
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sim->ext.c_stat = 1;
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sim->ext.clocks = 3200; /* 160us */
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}
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/* Write a value to CCSR */
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static void extWriteCCSR(VB *sim, uint8_t value) {
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/* Configure state */
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sim->ext.cc_int_inh = value >> 7 & 1;
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sim->ext.cc_int_lev = value >> 4 & 1;
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sim->ext.cc_sig = value >> 3 & 1;
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sim->ext.cc_wr = value >> 1 & 1;
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/* Acknowledge interrupt */
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if (!sim->ext.cc_int_inh)
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return;
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sim->ext.cc_irq = 0;
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if (!sim->ext.c_irq)
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sim->cpu.irq &= ~0x0008;
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}
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#endif /* VBAPI */
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@ -9,12 +9,12 @@
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static void padEmulate(VB *sim, uint32_t clocks) {
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/* No hardware read in progress */
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if (sim->pad.si_stat == 0)
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if (!sim->pad.si_stat)
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return;
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/* Hardware read completes after time to process */
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if (sim->pad.si_stat > clocks) {
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sim->pad.si_stat -= clocks;
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if (sim->pad.clocks > clocks) {
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sim->pad.clocks -= clocks;
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return;
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}
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@ -38,7 +38,7 @@ static int32_t padReadControl(VB *sim) {
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sim->pad.k_int_inh << 7 |
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sim->pad.para_si << 5 |
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sim->pad.soft_ck << 4 |
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!!sim->pad.si_stat << 1 |
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sim->pad.si_stat << 1 |
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sim->pad.s_abt_dis
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;
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}
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@ -78,7 +78,8 @@ static void padWriteControl(VB *sim, uint8_t value) {
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sim->pad.si_stat == 0 && /* No hardware read underway */
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!sim->pad.s_abt_dis /* Hardware reads enabled */
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) {
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sim->pad.si_stat = 10240; /* 512us */
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sim->pad.clocks = 10240; /* 512us */
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sim->pad.si_stat = 1;
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sim->pad.step = 0; /* Abort software read */
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}
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@ -86,7 +87,7 @@ static void padWriteControl(VB *sim, uint8_t value) {
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sim->pad.para_si = value >> 5 & 1;
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if (
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sim->pad.para_si &&
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sim->pad.si_stat == 0 /* No hardware read underway */
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!sim->pad.si_stat /* No hardware read underway */
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) sim->pad.step = 32;
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/* Signal a bit for a software read */
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@ -107,8 +108,8 @@ static void padWriteControl(VB *sim, uint8_t value) {
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/* Determine how many clocks are guaranteed to process */
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static uint32_t padUntil(VB *sim, uint32_t clocks) {
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return sim->pad.si_stat != 0 && sim->pad.si_stat < clocks ?
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sim->pad.si_stat : clocks;
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return sim->pad.si_stat && sim->pad.clocks < clocks ?
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sim->pad.clocks : clocks;
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}
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73
core/vb.c
73
core/vb.c
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@ -146,6 +146,28 @@ struct VB {
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int step; /* Operation sub-task ID */
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} cpu;
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/* Communication port */
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struct {
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/* Register state */
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uint8_t c_clk_sel; /* Transmission clock source */
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uint8_t c_int_inh; /* Interrupt acknowledge/disable */
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uint8_t c_stat; /* Communication is underway */
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uint8_t cc_int_inh; /* Interrupt acknowledge/disable */
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uint8_t cc_int_lev; /* Interrupt condition */
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uint8_t cc_rd; /* Manual read */
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uint8_t cc_sig; /* Automatic write */
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uint8_t cc_smp; /* Automatic read */
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uint8_t cc_wr; /* Manual write */
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uint8_t cdrr; /* Data received */
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uint8_t cdtr; /* Data to transmit */
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/* Other state */
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int8_t c_irq; /* COM interrupt request */
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int8_t cc_irq; /* COMCNT interrupt request */
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uint32_t clocks; /* Master clocks to wait */
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} ext;
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/* Game pad */
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struct {
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@ -159,8 +181,9 @@ struct VB {
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uint8_t soft_ck; /* Controller communication signal */
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/* Other state */
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uint16_t keys; /* Next input bits */
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int step; /* Software read processing phase */
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uint32_t clocks; /* Master clocks to wait */
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uint16_t keys; /* Next input bits */
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int step; /* Software read processing phase */
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} pad;
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/* Timer */
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@ -310,6 +333,12 @@ struct VB {
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int sample; /* Output sample index, period 417 */
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} vsu;
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/* Wait controller */
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struct {
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uint8_t exp1w; /* Cartridge expansion 1-wait */
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uint8_t rom1w; /* Cartridge ROM 1-wait */
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} wcr;
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/* Pseudo-halt */
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struct {
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uint32_t address; /* Monitor address */
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@ -335,7 +364,6 @@ struct VB {
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} ph;
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/* Other state */
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uint8_t wcr; /* Wait controller state */
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uint8_t wram[0x10000]; /* System RAM */
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/* Application data */
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@ -343,9 +371,11 @@ struct VB {
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vbOnExecute onExecute; /* CPU instruction execute */
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vbOnFetch onFetch; /* CPU instruction fetch */
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vbOnFrame onFrame; /* VIP frame ready */
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vbOnLink onLink; /* Communication transfer */
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vbOnRead onRead; /* CPU instruction read */
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vbOnSamples onSamples; /* VSU samples full */
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vbOnWrite onWrite; /* CPU instruction write */
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VB *peer; /* Communication peer */
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void *tag; /* User data */
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};
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@ -368,6 +398,7 @@ static int32_t SignExtend(int32_t value, int32_t bits) {
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/******************************** Sub-Modules ********************************/
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#include "ext.c"
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#include "game-pad.c"
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#include "timer.c"
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#include "bus.c"
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@ -391,7 +422,8 @@ static int sysEmulate(VB *sim, uint32_t clocks) {
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;
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/* Process all components */
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if (!never) ret = cpuEmulate(sim, clocks);
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if (!never){ret = cpuEmulate(sim, clocks);}
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ret |= extEmulate(sim, clocks);
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padEmulate(sim, clocks);
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tmrEmulate(sim, clocks);
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vsuEmulate(sim, clocks);
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/* Determine how many clocks are guaranteed to process */
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static uint32_t sysUntil(VB *sim, uint32_t clocks) {
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clocks = cpuUntil(sim, clocks);
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clocks = extUntil(sim, clocks);
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clocks = padUntil(sim, clocks);
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clocks = tmrUntil(sim, clocks);
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clocks = vipUntil(sim, clocks);
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@ -487,6 +520,11 @@ VBAPI uint16_t vbGetKeys(VB *sim) {
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return sim->pad.keys;
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}
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/* Retrieve the current link callback handler */
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VBAPI vbOnLink vbGetLinkCallback(VB *sim) {
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return sim->onLink;
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}
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/* Retrieve a core option value */
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VBAPI int vbGetOption(VB *sim, int key) {
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switch (key) {
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@ -495,6 +533,11 @@ VBAPI int vbGetOption(VB *sim, int key) {
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return 0;
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}
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/* Retrieve the communication peer */
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VBAPI VB* vbGetPeer(VB *sim) {
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return sim->peer;
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}
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/* Retrieve the most recent frame image pixels */
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VBAPI void vbGetPixels(VB *sim, void *left, int leftStrideX, int leftStrideY,
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void *right, int rightStrideX, int rightStrideY) {
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@ -594,9 +637,11 @@ VBAPI VB* vbInit(VB *sim) {
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sim->onExecute = NULL;
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sim->onFetch = NULL;
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sim->onFrame = NULL;
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sim->onLink = NULL;
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sim->onRead = NULL;
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sim->onSamples = NULL;
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sim->onWrite = NULL;
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sim->peer = NULL;
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sim->ph.enabled = 0;
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vbReset(sim);
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return sim;
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@ -616,7 +661,8 @@ VBAPI VB* vbReset(VB *sim) {
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int x; /* Iterator */
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/* Wait controller */
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sim->wcr = 0x00;
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sim->wcr.exp1w = 0;
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sim->wcr.rom1w = 0;
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/* WRAM (the hardware does not do this) */
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for (x = 0; x < 0x10000; x++)
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@ -624,6 +670,7 @@ VBAPI VB* vbReset(VB *sim) {
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/* Components */
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cpuReset(sim);
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extReset(sim);
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padReset(sim);
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tmrReset(sim);
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vipReset(sim);
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@ -689,6 +736,13 @@ VBAPI uint16_t vbSetKeys(VB *sim, uint16_t keys) {
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return sim->pad.keys = keys;
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}
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/* Specify a new link callback handler */
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VBAPI vbOnLink vbSetLinkCallback(VB *sim, vbOnLink callback) {
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vbOnLink prev = sim->onLink;
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sim->onLink = callback;
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return prev;
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}
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/* Specify a new core option value */
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VBAPI int vbSetOption(VB *sim, int key, int value) {
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switch (key) {
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@ -706,6 +760,15 @@ VBAPI int vbSetOption(VB *sim, int key, int value) {
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return value;
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}
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/* Specify a new communication peer */
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VBAPI VB* vbSetPeer(VB *sim, VB *peer) {
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VB *prev = sim->peer;
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sim->peer = peer;
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if (peer != prev && prev != NULL)
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prev->peer = NULL;
|
||||
return prev;
|
||||
}
|
||||
|
||||
/* Specify a new value for the program counter */
|
||||
VBAPI uint32_t vbSetProgramCounter(VB *sim, uint32_t value) {
|
||||
sim->cpu.operation = CPU_FETCH;
|
||||
|
|
|
@ -22,6 +22,7 @@ extern "C" {
|
|||
VB_DIRECT_EXECUTE
|
||||
VB_DIRECT_FETCH
|
||||
VB_DIRECT_FRAME
|
||||
VB_DIRECT_LINK
|
||||
VB_DIRECT_READ
|
||||
VB_DIRECT_SAMPLES
|
||||
VB_DIRECT_WRITE
|
||||
|
@ -94,6 +95,7 @@ typedef int (*vbOnException)(VB *sim, uint16_t *cause);
|
|||
typedef int (*vbOnExecute )(VB *sim, uint32_t address, const uint16_t *code, int length);
|
||||
typedef int (*vbOnFetch )(VB *sim, int fetch, uint32_t address, int32_t *value, uint32_t *cycles);
|
||||
typedef int (*vbOnFrame )(VB *sim);
|
||||
typedef int (*vbOnLink )(VB *sim1, VB *sim2, uint8_t *value1, uint8_t *value2);
|
||||
typedef int (*vbOnRead )(VB *sim, uint32_t address, int type, int32_t *value, uint32_t *cycles);
|
||||
typedef void (*vbOnSamples )(VB *sim, int16_t *buffer, uint32_t capacity);
|
||||
typedef int (*vbOnWrite )(VB *sim, uint32_t address, int type, int32_t *value, uint32_t *cycles, int *cancel);
|
||||
|
@ -113,7 +115,9 @@ VBAPI vbOnExecute vbGetExecuteCallback (VB *sim);
|
|||
VBAPI vbOnFetch vbGetFetchCallback (VB *sim);
|
||||
VBAPI vbOnFrame vbGetFrameCallback (VB *sim);
|
||||
VBAPI uint16_t vbGetKeys (VB *sim);
|
||||
VBAPI vbOnLink vbGetLinkCallback (VB *sim);
|
||||
VBAPI int vbGetOption (VB *sim, int key);
|
||||
VBAPI VB* vbGetPeer (VB *sim);
|
||||
VBAPI void vbGetPixels (VB *sim, void *left, int leftStrideX, int leftStrideY, void *right, int rightStrideX, int rightStrideY);
|
||||
VBAPI uint32_t vbGetProgramCounter (VB *sim);
|
||||
VBAPI int32_t vbGetProgramRegister (VB *sim, int index);
|
||||
|
@ -132,6 +136,7 @@ VBAPI vbOnException vbSetExceptionCallback(VB *sim, vbOnException callback);
|
|||
VBAPI vbOnExecute vbSetExecuteCallback (VB *sim, vbOnExecute callback);
|
||||
VBAPI vbOnFetch vbSetFetchCallback (VB *sim, vbOnFetch callback);
|
||||
VBAPI vbOnFrame vbSetFrameCallback (VB *sim, vbOnFrame callback);
|
||||
VBAPI vbOnLink vbSetLinkCallback (VB *sim, vbOnLink callback);
|
||||
VBAPI uint16_t vbSetKeys (VB *sim, uint16_t keys);
|
||||
VBAPI int vbSetOption (VB *sim, int key, int value);
|
||||
VBAPI uint32_t vbSetProgramCounter (VB *sim, uint32_t value);
|
||||
|
|
Loading…
Reference in New Issue