Compare commits

..
4 Commits
Author SHA1 Message Date
GuyPerfect ecbd103917 Manage IRQ on writes to INTENB 2025-03-04 10:19:12 -06:00
GuyPerfect b2412d9487 Fix shameful syntax error 2025-03-01 15:51:49 -06:00
GuyPerfect dd1045553b Even more VSU edge cases 2025-03-01 15:42:16 -06:00
GuyPerfect 459a16076a Expand BRTx to 0..132, fix affine parallax 2025-02-25 09:02:22 -06:00
3 changed files with 40 additions and 27 deletions
+1
View File
@@ -361,6 +361,7 @@ struct VB {
/* Other state */ /* Other state */
uint32_t clocks; /* Clocks until modification */ uint32_t clocks; /* Clocks until modification */
uint8_t freqmask; /* Frequency mask */
uint8_t modmask; /* Modifications masked */ uint8_t modmask; /* Modifications masked */
uint16_t next; /* Next frequency value */ uint16_t next; /* Next frequency value */
int sample; /* Current sample index */ int sample; /* Current sample index */
+15 -11
View File
@@ -42,14 +42,15 @@ static const uint8_t BG_TEMPLATES[][64] = {
/* 8-bit color magnitude by brightness level */ /* 8-bit color magnitude by brightness level */
static const uint8_t BRIGHT8[] = { static const uint8_t BRIGHT8[] = {
0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 0, 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 28,
32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 30, 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 57, 59,
64, 66, 68, 70, 72, 74, 76, 78, 80, 82, 84, 86, 88, 90, 92, 94, 61, 63, 65, 67, 69, 71, 73, 75, 77, 79, 81, 83, 85, 86, 88, 90,
96, 98,100,102,104,106,108,110,112,114,116,118,120,122,124,126, 92, 94, 96, 98,100,102,104,106,108,110,112,113,115,117,119,121,
129,131,133,135,137,139,141,143,145,147,149,151,153,155,157,159, 123,125,127,129,131,133,135,137,139,141,142,144,146,148,150,152,
161,163,165,167,169,171,173,175,177,179,181,183,185,187,189,191, 154,156,158,160,162,164,166,168,170,171,173,175,177,179,181,183,
193,195,197,199,201,203,205,207,209,211,213,215,217,219,221,223, 185,187,189,191,193,195,197,198,200,202,204,206,208,210,212,214,
225,227,229,231,233,235,237,239,241,243,245,247,249,251,253,255 216,218,220,222,224,226,227,229,231,233,235,237,239,241,243,245,
247,249,251,253,255
}; };
@@ -435,6 +436,9 @@ static void vipWriteIO(
case 0x5F802>>1: /* INTENB */ case 0x5F802>>1: /* INTENB */
sim->vip.intenb = (sim->vip.intenb & mask) | (value & 0xE01F); sim->vip.intenb = (sim->vip.intenb & mask) | (value & 0xE01F);
if (sim->vip.intenb & sim->vip.intpnd)
sim->cpu.irq |= 0x0010;
else sim->cpu.irq &= ~0x0010;
break; break;
case 0x5F804>>1: /* INTCLR */ case 0x5F804>>1: /* INTCLR */
sim->vip.intpnd &= ~value; sim->vip.intpnd &= ~value;
@@ -586,7 +590,7 @@ static void vipComputeBrightness(VB *sim) {
/* Transform brightness values to 0..255 */ /* Transform brightness values to 0..255 */
for (x = 1; x < 4; x++) for (x = 1; x < 4; x++)
sim->vip.dp.brt[x] = brt[x] > 127 ? 255 : BRIGHT8[brt[x]]; sim->vip.dp.brt[x] = brt[x] > 132 ? 255 : BRIGHT8[brt[x]];
} }
/* Transfer one column of frame buffer pixels to output */ /* Transfer one column of frame buffer pixels to output */
@@ -1060,8 +1064,8 @@ static void vipDrawAffine(VB *sim, World *world) {
/* Adjust left-edge parameters */ /* Adjust left-edge parameters */
if ((mp < 0) ^ i) { if ((mp < 0) ^ i) {
mx += dx * (wx - mp); mx += dx * (wx + mp);
my += dy * (wx - mp); my += dy * (wx + mp);
} else { } else {
mx += dx * wx; mx += dx * wx;
my += dy * wx; my += dy * wx;
+18 -10
View File
@@ -82,12 +82,12 @@ static void vsuNextFreqMod(VB *sim, Channel *chan) {
/* Modulation */ /* Modulation */
else { else {
next = (int32_t) chan->freq.written + next = ((int32_t) chan->freq.written +
sim->vsu.modulation[sim->vsu.freqmod.sample]; sim->vsu.modulation[sim->vsu.freqmod.sample]) & 0x7FF;
if (next < 0) if (sim->vsu.freqmod.freqmask == 1)
next = 0; next = (next & 0x700) | (chan->freq.written & 0x0FF);
if (next > 2047) else if (sim->vsu.freqmod.freqmask == 2)
next = 2047; next = (next & 0x0FF) | (chan->freq.written & 0x700);
} }
/* Configure state */ /* Configure state */
@@ -257,7 +257,9 @@ static void vsuWriteFQH(VB *sim, int index, uint16_t value) {
value = value << 8 & 0x0700; value = value << 8 & 0x0700;
chan->freq.current = (chan->freq.current & 0x00FF) | value; chan->freq.current = (chan->freq.current & 0x00FF) | value;
chan->freq.written = (chan->freq.written & 0x00FF) | value; chan->freq.written = (chan->freq.written & 0x00FF) | value;
if (index == 4) if (index != 4)
return;
sim->vsu.freqmod.freqmask = 2;
vsuNextFreqMod(sim, chan); vsuNextFreqMod(sim, chan);
} }
@@ -266,7 +268,9 @@ static void vsuWriteFQL(VB *sim, int index, uint8_t value) {
Channel *chan = &sim->vsu.channels[index]; Channel *chan = &sim->vsu.channels[index];
chan->freq.current = (chan->freq.current & 0x0700) | value; chan->freq.current = (chan->freq.current & 0x0700) | value;
chan->freq.written = (chan->freq.written & 0x0700) | value; chan->freq.written = (chan->freq.written & 0x0700) | value;
if (index == 4) if (index != 4)
return;
sim->vsu.freqmod.freqmask = 1;
vsuNextFreqMod(sim, chan); vsuNextFreqMod(sim, chan);
} }
@@ -507,6 +511,7 @@ static void vsuReset(VB *sim) {
sim->vsu.freqmod.clocks = 0; sim->vsu.freqmod.clocks = 0;
sim->vsu.freqmod.dir = 0; sim->vsu.freqmod.dir = 0;
sim->vsu.freqmod.enb = 0; sim->vsu.freqmod.enb = 0;
sim->vsu.freqmod.freqmask = 0;
sim->vsu.freqmod.func = 0; sim->vsu.freqmod.func = 0;
sim->vsu.freqmod.interval = 0; sim->vsu.freqmod.interval = 0;
sim->vsu.freqmod.modmask = 0; sim->vsu.freqmod.modmask = 0;
@@ -536,11 +541,14 @@ static void vsuWrite(VB*sim,uint32_t address,int type,int32_t value,int debug){
} }
/* Unmapped */ /* Unmapped */
if (address & 3) if (address & 1)
return; return;
/* Working variables */ /* Working variables */
address &= 0x7FF; address &= 0x7FC;
/* Clear frequency mask */
sim->vsu.freqmod.freqmask = 0;
/* Wave memory */ /* Wave memory */
if (address < 0x280) { if (address < 0x280) {