841 lines
25 KiB
C
841 lines
25 KiB
C
#ifndef VBAPI
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#define VBAPI
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#endif
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#include <float.h>
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#include <vb.h>
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/*********************************** Types ***********************************/
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/* Output image */
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typedef uint8_t Pixels[2][384*224];
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/* VSU channel */
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typedef struct {
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/* Envelope */
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struct {
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/* Register state */
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uint8_t enb; /* Modifications enabled */
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uint8_t dir; /* Modification direction */
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uint8_t interval; /* Modification interval */
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uint8_t rep; /* Repeat modifications */
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uint8_t value; /* Master output level */
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/* Other state */
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uint32_t clocks; /* Clocks until modification */
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uint8_t reload; /* Automatic reload value */
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} env;
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/* Frequency */
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struct {
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uint16_t current; /* Current value */
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uint16_t written; /* Last value written */
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} freq;
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/* Stereo levels */
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struct {
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uint8_t left; /* Left output level */
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uint8_t right; /* Right output level */
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} lrv;
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/* Control */
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struct {
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/* Register state */
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uint8_t auto_; /* Shutoff enabled */
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uint8_t enb; /* Sound generation enabled */
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uint8_t interval; /* Shutoff interval */
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/* Other state */
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uint32_t clocks; /* Clocks until shutoff */
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} int_;
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/* Waveform */
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struct {
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/* Register state */
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uint8_t wave; /* Waveform index */
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/* Other state */
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int sample; /* Current sample index */
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} wave;
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/* Other state */
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uint32_t clocks; /* Clocks until next sample */
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} Channel;
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/* Simulation state */
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struct VB {
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/* Game Pak */
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struct {
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uint8_t *ram; /* Save RAM */
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uint8_t *rom; /* Program ROM */
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uint32_t ramMask; /* Size of SRAM - 1 */
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uint32_t romMask; /* Size of ROM - 1 */
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} cart;
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/* CPU */
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struct {
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/* Cache Control Word */
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struct {
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uint8_t ice; /* Instruction Cache Enable */
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} chcw;
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/* Exception Cause Register */
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struct {
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uint16_t eicc; /* Exception/Interrupt Cause Code */
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uint16_t fecc; /* Fatal Error Cause Code */
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} ecr;
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/* Program Status Word */
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struct {
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uint8_t ae; /* Address Trap Enable */
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uint8_t cy; /* Carry */
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uint8_t ep; /* Exception Pending */
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uint8_t fiv; /* Floating Invalid */
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uint8_t fov; /* Floating Overflow */
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uint8_t fpr; /* Floading Precision */
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uint8_t fro; /* Floating Reserved Operand */
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uint8_t fud; /* Floading Underflow */
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uint8_t fzd; /* Floating Zero Divide */
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uint8_t i; /* Interrupt Level */
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uint8_t id; /* Interrupt Disable */
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uint8_t np; /* NMI Pending */
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uint8_t ov; /* Overflow */
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uint8_t s; /* Sign */
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uint8_t z; /* Zero */
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} psw;
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/* Other registers */
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uint32_t adtre; /* Address Trap Register for Execution */
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uint32_t eipc; /* Exception/Interrupt PC */
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uint32_t eipsw; /* Exception/Interrupt PSW */
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uint32_t fepc; /* Fatal Error PC */
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uint32_t fepsw; /* Fatal Error PSW */
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uint32_t pc; /* Program Counter */
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int32_t program[32]; /* Program registers */
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uint32_t sr29; /* System register 29 */
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uint32_t sr31; /* System register 31 */
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/* Working data */
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union {
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struct {
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uint32_t dest;
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uint64_t src;
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} bs; /* Arithmetic bit strings */
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struct {
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uint32_t address;
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int32_t value;
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} data; /* Data accesses */
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} aux;
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/* Other state */
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uint32_t clocks; /* Master clocks to wait */
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uint16_t code[2]; /* Instruction code units */
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uint16_t exception; /* Exception cause code */
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int halt; /* CPU is halting */
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uint16_t irq; /* Interrupt request lines */
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int length; /* Instruction code length */
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uint32_t nextPC; /* Address of next instruction */
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int operation; /* Current operation ID */
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int step; /* Operation sub-task ID */
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} cpu;
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/* Communication port */
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struct {
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/* Register state */
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uint8_t c_clk_sel; /* Transmission clock source */
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uint8_t c_int_inh; /* Interrupt acknowledge/disable */
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uint8_t c_stat; /* Communication is underway */
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uint8_t cc_int_inh; /* Interrupt acknowledge/disable */
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uint8_t cc_int_lev; /* Interrupt condition */
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uint8_t cc_rd; /* Manual read */
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uint8_t cc_sig; /* Automatic write */
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uint8_t cc_smp; /* Automatic read */
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uint8_t cc_wr; /* Manual write */
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uint8_t cdrr; /* Data received */
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uint8_t cdtr; /* Data to transmit */
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/* Other state */
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int8_t c_irq; /* COM interrupt request */
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int8_t cc_irq; /* COMCNT interrupt request */
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uint32_t clocks; /* Master clocks to wait */
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} ext;
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/* Game pad */
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struct {
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/* Register state */
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uint8_t k_int_inh; /* Interrupt acknowledge/disable */
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uint8_t para_si; /* Read reset signal */
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uint8_t s_abt_dis; /* Abort hardware read */
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uint8_t sdhr; /* High key bits */
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uint8_t sdlr; /* Low key bits */
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uint32_t si_stat; /* Hardware read in progress */
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uint8_t soft_ck; /* Controller communication signal */
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/* Other state */
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uint32_t clocks; /* Master clocks to wait */
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uint16_t keys; /* Next input bits */
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int step; /* Software read processing phase */
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} pad;
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/* Timer */
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struct {
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/* Register state */
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uint8_t t_clk_sel; /* Counter tick duration */
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uint8_t t_enb; /* Enable timer */
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uint8_t tim_z_int; /* Enable interrupt */
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uint8_t z_stat; /* Zero status */
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/* Other state */
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uint32_t clocks; /* Master clocks to wait */
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uint16_t counter; /* Current counter value */
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uint16_t reload; /* Reload counter value */
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uint32_t until; /* Clocks until interrupt condition */
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} tmr;
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/* VIP */
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struct {
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/* CTA */
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struct {
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uint8_t cta_l; /* Left column table index */
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uint8_t cta_r; /* Right column table index */
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} cta;
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/* Display processor */
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struct {
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/* Register state */
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uint8_t disp; /* Display enabled */
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uint8_t fclk; /* Frame clock signal high */
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uint8_t l0bsy; /* Displaying left frame buffer 0 */
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uint8_t l1bsy; /* Displaying left frame buffer 1 */
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uint8_t lock; /* Lock CTA */
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uint8_t r0bsy; /* Displaying right frame buffer 0 */
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uint8_t r1bsy; /* Displaying right frame buffer 1*/
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uint8_t re; /* Memory refresh enabled */
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uint8_t scanrdy; /* Mirrors are stable */
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uint8_t synce; /* Servo enabled */
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/* Other state */
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uint8_t brt[4]; /* Precomputed brightness */
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int buffer; /* Index of frame buffer to display */
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uint32_t clocks; /* Master clocks to wait */
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int column; /* Index of column to display */
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uint32_t cta; /* Column table pointer in memory */
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uint8_t enabled; /* Was enabled at FCLK */
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uint32_t fbDest; /* Output frame pixel address */
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uint32_t fbSrc; /* Source frame buffer address */
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int32_t repeat; /* Current column table repeat value */
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int step; /* Processing phase */
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uint32_t until; /* Clocks until interrupt condition */
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} dp;
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/* Pixel processor */
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struct {
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/* Register state */
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uint8_t f0bsy; /* Drawing into frame buffer 0 */
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uint8_t f1bsy; /* Drawing into frame buffer 1 */
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uint8_t overtime; /* Drawing extends into display interval */
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uint8_t sbcmp; /* Vertical output position compare */
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uint8_t sbcount; /* Current vertical output position */
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uint32_t sbout; /* Drawing specified vertical output position */
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uint8_t xpen; /* Drawing enabled */
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/* Other state */
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uint32_t clocks; /* Master clocks to wait */
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int column; /* Current horizontal output position */
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uint8_t enabled; /* Was enabled at FCLK */
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int frame; /* FRMCYC counter */
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int32_t halfword; /* Current output halfword offset */
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int step; /* Processing phase */
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uint32_t until; /* Clocks until interrupt condition */
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} xp;
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/* Control state */
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uint8_t bkcol; /* Backdrop color */
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uint8_t brtRest[4]; /* Brightness and REST */
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uint8_t frmcyc; /* Game frame control */
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uint8_t gplt[4][4]; /* Background palettes */
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uint16_t intenb; /* Interrupts enabled */
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uint16_t intpnd; /* Interrupts pending */
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uint8_t jplt[4][4]; /* Object palettes */
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uint16_t spt[4]; /* Object control */
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/* Rendering shadow memory */
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uint16_t halfwords[384*28]; /* Output timing by 1x8 halfword */
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Pixels output[2]; /* Output images, row-major */
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Pixels shadow; /* Drawing shadow image, column-major */
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/* Other state */
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uint8_t ram[0x40000]; /* Video memory */
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} vip;
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/* VSU */
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struct {
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/* Audio sources */
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Channel channels[6];
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/* Channel 5 frequency modification */
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struct {
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/* Register state */
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uint8_t clk; /* Base modification clock */
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uint8_t dir; /* Sweep direction */
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uint8_t enb; /* Modifications enabled */
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uint8_t func; /* Modification function */
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uint8_t interval; /* Modification interval */
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uint8_t rep; /* Repeat modulation */
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uint8_t shift; /* Sweep shift amount */
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/* Other state */
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uint32_t clocks; /* Clocks until modification */
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uint16_t next; /* Next frequency value */
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int sample; /* Current sample index */
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} freqmod;
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/* Channel 6 noise generator */
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struct {
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/* Register state */
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uint8_t tap; /* LSFR feedback bit position */
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/* Other state */
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uint16_t register_; /* Pseudorandom bits */
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} noise;
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/* Sample output */
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struct {
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float i1[2]; /* Previous analog input sample */
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float o1[2]; /* Previous analog output sample */
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uint32_t capacity; /* Number of audio frames in samples */
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uint32_t offset; /* Position in output buffer */
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int16_t *samples; /* Output memory */
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} out;
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/* Memory */
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int8_t modulation[32]; /* Modulation amounts */
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uint8_t waves[5][32]; /* Wafeform samples */
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/* Other state */
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uint32_t clocks; /* Clocks until next output sample */
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int sample; /* Output sample index, period 417 */
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} vsu;
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/* Wait controller */
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struct {
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uint8_t exp1w; /* Cartridge expansion 1-wait */
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uint8_t rom1w; /* Cartridge ROM 1-wait */
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} wcr;
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/* Pseudo-halt */
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struct {
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uint32_t address; /* Monitor address */
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uint8_t enabled; /* Pseudo-halt function is enabled */
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uint8_t operation; /* Monitoring operation */
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uint8_t step; /* Number of consecutive matching reads */
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int type; /* Memory access type */
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int32_t value; /* Value read from monitor address */
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/* CPU snapshot */
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uint32_t adtre;
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uint32_t chcw;
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uint32_t ecr;
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uint32_t eipc;
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uint32_t eipsw;
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uint32_t fepc;
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uint32_t fepsw;
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uint32_t pc;
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int32_t program[31];
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uint32_t psw;
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uint32_t sr29;
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uint32_t sr31;
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} ph;
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/* Other state */
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uint8_t wram[0x10000]; /* System RAM */
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/* Application data */
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vbOnException onException; /* CPU exception */
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vbOnExecute onExecute; /* CPU instruction execute */
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vbOnFetch onFetch; /* CPU instruction fetch */
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vbOnFrame onFrame; /* VIP frame ready */
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vbOnLink onLink; /* Communication transfer */
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vbOnRead onRead; /* CPU instruction read */
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vbOnSamples onSamples; /* VSU samples full */
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vbOnWrite onWrite; /* CPU instruction write */
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VB *peer; /* Communication peer */
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void *tag; /* User data */
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};
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/***************************** Library Functions *****************************/
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/* Sign-extend an integer of variable width */
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static int32_t SignExtend(int32_t value, int32_t bits) {
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#ifndef VB_SIGNED_PROPAGATE
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value &= ~((uint32_t) 0xFFFFFFFF << bits);
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bits = (int32_t) 1 << (bits - (int32_t) 1);
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return (value ^ bits) - bits;
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#else
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return value << (32 - bits) >> (32 - bits);
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#endif
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}
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/******************************** Sub-Modules ********************************/
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#include "ext.c"
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#include "game-pad.c"
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#include "timer.c"
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#include "bus.c"
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#include "cpu.c"
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#include "vip.c"
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#include "vsu.c"
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#include "pseudo-halt.c"
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/***************************** Library Functions *****************************/
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/* Process a simulation for a given number of clocks */
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static int sysEmulate(VB *sim, uint32_t clocks) {
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int ret = 0;
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/* CPU is in a pseudo-halt state that requires an interrupt to exit */
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int never =
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sim->cpu.operation == CPU_PHALT &&
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sim->ph.operation == PH_NEVER
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;
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/* Process all components */
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if (!never){ret = cpuEmulate(sim, clocks);}
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ret |= extEmulate(sim, clocks);
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padEmulate(sim, clocks);
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tmrEmulate(sim, clocks);
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vsuEmulate(sim, clocks);
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ret |= vipEmulate(sim, clocks);
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if ( never) ret |= cpuEmulate(sim, clocks);
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return ret;
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}
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/* Determine how many clocks are guaranteed to process */
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static uint32_t sysUntil(VB *sim, uint32_t clocks) {
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clocks = cpuUntil(sim, clocks);
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clocks = extUntil(sim, clocks);
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clocks = padUntil(sim, clocks);
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clocks = tmrUntil(sim, clocks);
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clocks = vipUntil(sim, clocks);
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return clocks;
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}
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/******************************* API Commands ********************************/
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/* Process one simulation */
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VBAPI int vbEmulate(VB *sim, uint32_t *clocks) {
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int brk; /* A callback requested a break */
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uint32_t until; /* Clocks guaranteed to process */
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while (*clocks != 0) {
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until = sysUntil(sim, *clocks);
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brk = sysEmulate(sim, until);
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*clocks -= until;
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if (brk)
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return brk; /* TODO: return 1 */
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}
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return 0;
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}
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/* Process multiple simulations */
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VBAPI int vbEmulateEx(VB **sims, int count, uint32_t *clocks) {
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int brk; /* A callback requested a break */
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uint32_t until; /* Clocks guaranteed to process */
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int x; /* Iterator */
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while (*clocks != 0) {
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until = *clocks;
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for (x = count - 1; x >= 0; x--)
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until = sysUntil(sims[x], until);
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brk = 0;
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for (x = count - 1; x >= 0; x--)
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brk |= sysEmulate(sims[x], until);
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*clocks -= until;
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if (brk)
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return brk; /* TODO: return 1 */
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}
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return 0;
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}
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/* Retrieve the game pack RAM buffer */
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VBAPI void* vbGetCartRAM(VB *sim, uint32_t *size) {
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if (size != NULL)
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*size = sim->cart.ram == NULL ? 0 : sim->cart.ramMask + 1;
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return sim->cart.ram;
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}
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/* Retrieve the game pack ROM buffer */
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VBAPI void* vbGetCartROM(VB *sim, uint32_t *size) {
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if (size != NULL)
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*size = sim->cart.rom == NULL ? 0 : sim->cart.romMask + 1;
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return sim->cart.rom;
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}
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/* Retrieve the exception callback handler */
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VBAPI vbOnException vbGetExceptionCallback(VB *sim) {
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return sim->onException;
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}
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/* Retrieve the execute callback handler */
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VBAPI vbOnExecute vbGetExecuteCallback(VB *sim) {
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return sim->onExecute;
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}
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/* Retrieve the fetch callback handler */
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VBAPI vbOnFetch vbGetFetchCallback(VB *sim) {
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return sim->onFetch;
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}
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/* Retrieve the frame callback handler */
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VBAPI vbOnFrame vbGetFrameCallback(VB *sim) {
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return sim->onFrame;
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}
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/* Retrieve the current game pad key state */
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VBAPI uint16_t vbGetKeys(VB *sim) {
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return sim->pad.keys;
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}
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/* Retrieve the current link callback handler */
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VBAPI vbOnLink vbGetLinkCallback(VB *sim) {
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return sim->onLink;
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}
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/* Retrieve a core option value */
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VBAPI int vbGetOption(VB *sim, int key) {
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switch (key) {
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case VB_PSEUDO_HALT: return sim->ph.enabled;
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}
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return 0;
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}
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/* Retrieve the communication peer */
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VBAPI VB* vbGetPeer(VB *sim) {
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return sim->peer;
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}
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/* Retrieve the most recent frame image pixels */
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VBAPI void vbGetPixels(VB *sim, void *left, int leftStrideX, int leftStrideY,
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void *right, int rightStrideX, int rightStrideY) {
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uint8_t *dest; /* Output data */
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int offset; /* Horizontal offset of output pixel */
|
|
uint8_t *src; /* Source data */
|
|
int xStride; /* Bytes between output pixels */
|
|
int yStride; /* Bytes between output lines */
|
|
int i, x, y; /* Iterators */
|
|
|
|
/* Process both eyes */
|
|
for (i = 0; i < 2; i++) {
|
|
|
|
/* Working variables for left image */
|
|
if (i == 0) {
|
|
dest = left;
|
|
xStride = leftStrideX;
|
|
yStride = leftStrideY;
|
|
}
|
|
|
|
/* Working variables for right image */
|
|
else {
|
|
dest = right;
|
|
xStride = rightStrideX;
|
|
yStride = rightStrideY;
|
|
}
|
|
|
|
/* Nothing to do */
|
|
if (dest == NULL)
|
|
continue;
|
|
|
|
/* Transfer pixels to the destination */
|
|
src = sim->vip.output[sim->vip.dp.buffer ^ 1][i];
|
|
for (y = 0; y < 224; y++, dest += yStride)
|
|
for (x = offset = 0; x < 384; x++, offset += xStride)
|
|
dest[offset] = *src++;
|
|
}
|
|
|
|
}
|
|
|
|
/* Retrieve the value of the program counter */
|
|
VBAPI uint32_t vbGetProgramCounter(VB *sim) {
|
|
return sim->cpu.pc;
|
|
}
|
|
|
|
/* Retrieve the value in a program register */
|
|
VBAPI int32_t vbGetProgramRegister(VB *sim, int index) {
|
|
return index < 1 || index > 31 ? 0 : sim->cpu.program[index];
|
|
}
|
|
|
|
/* Retrieve the read callback handler */
|
|
VBAPI vbOnRead vbGetReadCallback(VB *sim) {
|
|
return sim->onRead;
|
|
}
|
|
|
|
/* Retrieve the audio samples buffer */
|
|
VBAPI void* vbGetSamples(VB *sim, uint32_t *capacity, uint32_t *position) {
|
|
if (sim->vsu.out.samples == NULL) {
|
|
if (capacity != NULL)
|
|
*capacity = 0;
|
|
if (position != NULL)
|
|
*position = 0;
|
|
} else {
|
|
if (capacity != NULL)
|
|
*capacity = sim->vsu.out.capacity;
|
|
if (position != NULL)
|
|
*position = sim->vsu.out.offset >> 1;
|
|
}
|
|
return sim->vsu.out.samples;
|
|
}
|
|
|
|
/* Retrieve the samples callback handler */
|
|
VBAPI vbOnSamples vbGetSamplesCallback(VB *sim) {
|
|
return sim->onSamples;
|
|
}
|
|
|
|
/* Retrieve the value in a system register */
|
|
VBAPI uint32_t vbGetSystemRegister(VB *sim, int index) {
|
|
return index < 0 || index > 31 ? 0 : cpuGetSystemRegister(sim, index);
|
|
}
|
|
|
|
/* Retrieve a simulation's userdata pointer */
|
|
VBAPI void* vbGetUserData(VB *sim) {
|
|
return sim->tag;
|
|
}
|
|
|
|
/* Retrieve the write callback handler */
|
|
VBAPI vbOnWrite vbGetWriteCallback(VB *sim) {
|
|
return sim->onWrite;
|
|
}
|
|
|
|
/* Initialize a simulation instance */
|
|
VBAPI VB* vbInit(VB *sim) {
|
|
sim->cart.ram = NULL;
|
|
sim->cart.rom = NULL;
|
|
sim->vsu.out.samples = NULL;
|
|
sim->onExecute = NULL;
|
|
sim->onFetch = NULL;
|
|
sim->onFrame = NULL;
|
|
sim->onLink = NULL;
|
|
sim->onRead = NULL;
|
|
sim->onSamples = NULL;
|
|
sim->onWrite = NULL;
|
|
sim->peer = NULL;
|
|
sim->ph.enabled = 0;
|
|
vbReset(sim);
|
|
return sim;
|
|
}
|
|
|
|
/* Read a value from the memory bus */
|
|
VBAPI int32_t vbRead(VB *sim, uint32_t address, int type) {
|
|
int32_t value;
|
|
if (type < 0 || type > 4)
|
|
return 0;
|
|
busRead(sim, address, type, &value);
|
|
return value;
|
|
}
|
|
|
|
/* Simulate a hardware reset */
|
|
VBAPI VB* vbReset(VB *sim) {
|
|
int x; /* Iterator */
|
|
|
|
/* Wait controller */
|
|
sim->wcr.exp1w = 0;
|
|
sim->wcr.rom1w = 0;
|
|
|
|
/* WRAM (the hardware does not do this) */
|
|
for (x = 0; x < 0x10000; x++)
|
|
sim->wram[x] = 0x00;
|
|
|
|
/* Components */
|
|
cpuReset(sim);
|
|
extReset(sim);
|
|
padReset(sim);
|
|
tmrReset(sim);
|
|
vipReset(sim);
|
|
vsuReset(sim);
|
|
|
|
/* Pseudo-halt */
|
|
sim->ph.step = 0;
|
|
return sim;
|
|
}
|
|
|
|
/* Specify a game pak RAM buffer */
|
|
VBAPI int vbSetCartRAM(VB *sim, void *sram, uint32_t size) {
|
|
if (sram != NULL) {
|
|
if (size < 16 || size > 0x1000000 || (size & (size - 1)) != 0)
|
|
return 1;
|
|
sim->cart.ramMask = size - 1;
|
|
}
|
|
sim->cart.ram = sram;
|
|
return 0;
|
|
}
|
|
|
|
/* Specify a game pak ROM buffer */
|
|
VBAPI int vbSetCartROM(VB *sim, void *rom, uint32_t size) {
|
|
if (rom != NULL) {
|
|
if (size < 16 || size > 0x1000000 || (size & (size - 1)) != 0)
|
|
return 1;
|
|
sim->cart.romMask = size - 1;
|
|
}
|
|
sim->cart.rom = rom;
|
|
return 0;
|
|
}
|
|
|
|
/* Specify a new exception callback handler */
|
|
VBAPI vbOnException vbSetExceptionCallback(VB *sim, vbOnException callback) {
|
|
vbOnException prev = sim->onException;
|
|
sim->onException = callback;
|
|
return prev;
|
|
}
|
|
|
|
/* Specify a new execute callback handler */
|
|
VBAPI vbOnExecute vbSetExecuteCallback(VB *sim, vbOnExecute callback) {
|
|
vbOnExecute prev = sim->onExecute;
|
|
sim->onExecute = callback;
|
|
return prev;
|
|
}
|
|
|
|
/* Specify a new fetch callback handler */
|
|
VBAPI vbOnFetch vbSetFetchCallback(VB *sim, vbOnFetch callback) {
|
|
vbOnFetch prev = sim->onFetch;
|
|
sim->onFetch = callback;
|
|
return prev;
|
|
}
|
|
|
|
/* Specify a new frame callback handler */
|
|
VBAPI vbOnFrame vbSetFrameCallback(VB *sim, vbOnFrame callback) {
|
|
vbOnFrame prev = sim->onFrame;
|
|
sim->onFrame = callback;
|
|
return prev;
|
|
}
|
|
|
|
/* Specify new game pad keys */
|
|
VBAPI uint16_t vbSetKeys(VB *sim, uint16_t keys) {
|
|
return sim->pad.keys = keys;
|
|
}
|
|
|
|
/* Specify a new link callback handler */
|
|
VBAPI vbOnLink vbSetLinkCallback(VB *sim, vbOnLink callback) {
|
|
vbOnLink prev = sim->onLink;
|
|
sim->onLink = callback;
|
|
return prev;
|
|
}
|
|
|
|
/* Specify a new core option value */
|
|
VBAPI int vbSetOption(VB *sim, int key, int value) {
|
|
switch (key) {
|
|
case VB_PSEUDO_HALT:
|
|
sim->ph.enabled = value = !!value;
|
|
if (!value) {
|
|
sim->ph.step = 0;
|
|
if (sim->cpu.operation == CPU_PHALT) {
|
|
sim->cpu.operation = CPU_FETCH;
|
|
sim->cpu.step = 0;
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
return value;
|
|
}
|
|
|
|
/* Specify a new communication peer */
|
|
VBAPI VB* vbSetPeer(VB *sim, VB *peer) {
|
|
VB *prev = sim->peer;
|
|
sim->peer = peer;
|
|
if (peer != prev && prev != NULL)
|
|
prev->peer = NULL;
|
|
return prev;
|
|
}
|
|
|
|
/* Specify a new value for the program counter */
|
|
VBAPI uint32_t vbSetProgramCounter(VB *sim, uint32_t value) {
|
|
sim->cpu.operation = CPU_FETCH;
|
|
sim->cpu.pc = sim->cpu.nextPC = value & 0xFFFFFFFE;
|
|
sim->cpu.step = 0;
|
|
return sim->cpu.pc;
|
|
}
|
|
|
|
/* Specify a new value for a program register */
|
|
VBAPI int32_t vbSetProgramRegister(VB *sim, int index, int32_t value) {
|
|
return index < 1 || index > 31 ? 0 : (sim->cpu.program[index] = value);
|
|
}
|
|
|
|
/* Specify a new read callback handler */
|
|
VBAPI vbOnRead vbSetReadCallback(VB *sim, vbOnRead callback) {
|
|
vbOnRead prev = sim->onRead;
|
|
sim->onRead = callback;
|
|
return prev;
|
|
}
|
|
|
|
/* Specify a new audio samples buffer */
|
|
VBAPI int vbSetSamples(VB *sim, void *samples, uint32_t capacity) {
|
|
if (samples != NULL && (capacity == 0 || capacity > 0x40000000))
|
|
return 1;
|
|
sim->vsu.out.capacity = samples == NULL ? 0 : capacity;
|
|
sim->vsu.out.offset = 0;
|
|
sim->vsu.out.samples = samples;
|
|
return 0;
|
|
}
|
|
|
|
/* Specify a new samples callback handler */
|
|
VBAPI vbOnSamples vbSetSamplesCallback(VB *sim, vbOnSamples callback) {
|
|
vbOnSamples prev = sim->onSamples;
|
|
sim->onSamples = callback;
|
|
return prev;
|
|
}
|
|
|
|
/* Specify a new value for a system register */
|
|
VBAPI uint32_t vbSetSystemRegister(VB *sim, int index, uint32_t value) {
|
|
return index < 0 || index > 31 ? 0 :
|
|
cpuSetSystemRegister(sim, index, value, 1);
|
|
}
|
|
|
|
/* Specify a new write callback handler */
|
|
VBAPI vbOnWrite vbSetWriteCallback(VB *sim, vbOnWrite callback) {
|
|
vbOnWrite prev = sim->onWrite;
|
|
sim->onWrite = callback;
|
|
return prev;
|
|
}
|
|
|
|
/* Determine the size of a simulation instance */
|
|
VBAPI size_t vbSizeOf() {
|
|
return sizeof (VB);
|
|
}
|
|
|
|
/* Specify a simulation's userdata pointer */
|
|
VBAPI void* vbSetUserData(VB *sim, void *tag) {
|
|
void *prev = sim->tag;
|
|
sim->tag = tag;
|
|
return prev;
|
|
}
|
|
|
|
/* Write a value to the memory bus */
|
|
VBAPI int32_t vbWrite(VB *sim, uint32_t address, int type, int32_t value) {
|
|
if (type < 0 || type > 4)
|
|
return 0;
|
|
busWrite(sim, address, type, value, 1);
|
|
return vbRead(sim, address, type);
|
|
}
|