265 lines
7.9 KiB
C
265 lines
7.9 KiB
C
/* This file is included into vb.c and cannot be compiled on its own. */
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#ifdef VBAPI
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/********************************* Constants *********************************/
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/* Pseudo-halt operations */
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#define PH_NEVER 0
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#define PH_DPSTTS 1
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#define PH_GAME_PAD 2
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#define PH_INTPND 3
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#define PH_TCR 4
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#define PH_TLHR 5
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#define PH_XPSTTS 6
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/***************************** Module Functions ******************************/
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/* Activate pseudo-halt */
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static void phActivate(VB *sim, uint32_t address, int type) {
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int range; /* Memory address range by component */
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/* Working variables */
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address &= 0x07FFFFFF;
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range = address >> 24;
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/* Configure pseudo-halt */
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sim->ph.operation = PH_NEVER;
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/* VIP */
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if (range == 0) {
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address &= 0x0007FFFF;
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/* TODO: Frame buffer */
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/* I/O register */
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switch (address) {
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case 0x5F800: /* INTPND */
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if (
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sim->vip.dp.step != 0 ||
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sim->vip.dp.enabled ||
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(sim->vip.dp.disp && sim->vip.dp.synce) ||
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sim->vip.xp.enabled ||
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sim->vip.xp.xpen
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) sim->ph.operation = PH_INTPND;
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break;
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case 0x5F820: /* DPSTTS */
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if (
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sim->vip.dp.step != 0 ||
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sim->vip.dp.enabled ||
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(sim->vip.dp.disp && sim->vip.dp.synce)
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) sim->ph.operation = PH_DPSTTS;
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break;
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case 0x5F840: /* XPSTTS */
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if (sim->vip.xp.enabled || sim->vip.xp.xpen)
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sim->ph.operation = PH_XPSTTS;
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break;
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}
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}
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/* Misc. I/O */
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else if (range == 2 && (type == VB_S8 || type == VB_U8)) {
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address &= 0x0000003F;
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switch (address) {
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/* TODO: Communication port */
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/* Game pad */
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case 0x10: /* SDLR */
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case 0x14: /* SDHR */
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case 0x28: /* SCR */
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if (sim->pad.si_stat != 0)
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sim->ph.operation = PH_GAME_PAD;
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break;
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/* Timer */
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case 0x18: /* TLR */
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case 0x1C: /* THR */
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if (sim->tmr.t_enb)
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sim->ph.operation = PH_TLHR;
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break;
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case 0x20: /* TCR */
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if (sim->tmr.t_enb)
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sim->ph.operation = PH_TCR;
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break;
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}
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}
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/* Configure CPU */
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sim->cpu.clocks = phUntil(sim);
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sim->cpu.operation = CPU_PHALT;
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}
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/* Test whether the current memory access matches the monitored access */
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static int phMatches(VB *sim, uint32_t address, int type, int32_t value) {
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int match; /* Parameter match */
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int x; /* Iterator */
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/* New memory access */
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if (sim->ph.step == 0)
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return 0;
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/* Check memory access parameters */
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match =
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address == sim->ph.address &&
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sim->cpu.pc == sim->ph.pc &&
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type == sim->ph.type &&
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value == sim->ph.value
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;
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if (!match || sim->ph.step != 3)
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return match;
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/* Check full CPU state */
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for (x = 1; x < 32; x++) {
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if (sim->ph.program[x - 1] != sim->cpu.program[x])
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return 0;
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}
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return
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sim->ph.adtre == sim->cpu.adtre &&
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sim->ph.chcw == cpuGetSystemRegister(sim, VB_CHCW) &&
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sim->ph.ecr == cpuGetSystemRegister(sim, VB_ECR) &&
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sim->ph.eipc == sim->cpu.eipc &&
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sim->ph.eipsw == sim->cpu.eipsw &&
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sim->ph.fepc == sim->cpu.fepc &&
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sim->ph.fepsw == sim->cpu.fepsw &&
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sim->ph.psw == cpuGetSystemRegister(sim, VB_PSW )
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;
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}
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/****************************** Clock Measurers ******************************/
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/* DPSTTS */
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static uint32_t phDPSTTS(VB *sim) {
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switch (sim->vip.dp.step) {
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case 0: /* 0ms - FCLK rising edge */
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case 2: /* 3ms-8ms - Display left frame buffer */
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case 3: /* 8ms - L*BSY falling edge */
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case 6: /* 13ms-18ms - Display right frame buffer */
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case 7: /* 18ms - R*BSY falling edge */
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case 8: /* 20ms - Display interval complete */
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return sim->vip.dp.until;
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}
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/* case 1: 3ms - L*BSY rising edge */
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/* case 4: 10ms - FCLK falling edge */
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/* case 5: 13ms - R*BSY rising edge */
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return sim->vip.dp.clocks;
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}
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/* INTPND */
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static uint32_t phINTPND(VB *sim) {
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if (!(
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sim->vip.dp.step != 0 ||
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sim->vip.dp.enabled ||
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(sim->vip.dp.disp && sim->vip.dp.synce)
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)) return sim->vip.xp.until;
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if (!(sim->vip.xp.enabled || sim->vip.xp.xpen))
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return sim->vip.dp.until;
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return sim->vip.dp.until < sim->vip.xp.until ?
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sim->vip.dp.until : sim->vip.xp.until;
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}
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/* XPSTTS */
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static uint32_t phXPSTTS(VB *sim) {
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uint32_t clocks; /* Return value */
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uint16_t *halfwords; /* Drawing clocks this SBCOUNT */
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uint32_t x; /* Iterator */
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/* Drawing is underway */
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if (sim->vip.xp.f0bsy || sim->vip.xp.f1bsy) {
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clocks = 0;
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halfwords = &sim->vip.halfwords[
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(uint32_t) sim->vip.xp.sbcount * 384 + sim->vip.xp.column];
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for (x = sim->vip.xp.column; x < 384; x++, halfwords++)
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clocks += *halfwords;
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return clocks;
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}
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/* Drawing is idle */
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switch (sim->vip.dp.step) {
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case 0: /* 0ms - FCLK rising edge */
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return sim->vip.dp.until;
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case 1: /* 3ms - L*BSY rising edge */
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case 2: /* 3ms-8ms - Display left frame buffer */
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case 3: /* 8ms - L*BSY falling edge */
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return sim->vip.dp.until + vipClocksMs(12);
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}
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/* case 4: 10ms - FCLK falling edge */
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/* case 5: 13ms - R*BSY rising edge */
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/* case 6: 13ms-18ms - Display right frame buffer */
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/* case 7: 18ms - R*BSY falling edge */
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return sim->vip.dp.until + vipClocksMs(2);
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}
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/***************************** Library Functions *****************************/
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/* Test whether to activate pseudo-halt */
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static int phAssess(VB *sim, uint32_t address, int type, int32_t value) {
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int x; /* Iterator */
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/* Memory access does not match last time */
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address &= TYPE_MASKS[type];
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if (!phMatches(sim, address, type, value))
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sim->ph.step = 0;
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/* New memory access */
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if (sim->ph.step == 0) {
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sim->ph.address = address;
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sim->ph.pc = sim->cpu.pc;
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sim->ph.step = 1;
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sim->ph.type = type;
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sim->ph.value = value;
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return 0;
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}
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/* Repeated memory access, not checking full CPU state */
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if (sim->ph.step < 2) {
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sim->ph.step++;
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return 0;
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}
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/* Take a snapshot of the full CPU state */
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if (sim->ph.step == 2) {
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for (x = 1; x < 32; x++)
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sim->ph.program[x - 1] = sim->cpu.program[x];
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sim->ph.adtre = sim->cpu.adtre;
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sim->ph.chcw = cpuGetSystemRegister(sim, VB_CHCW);
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sim->ph.ecr = cpuGetSystemRegister(sim, VB_ECR);
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sim->ph.eipc = sim->cpu.eipc;
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sim->ph.eipsw = sim->cpu.eipsw;
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sim->ph.fepc = sim->cpu.fepc;
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sim->ph.fepsw = sim->cpu.fepsw;
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sim->ph.psw = cpuGetSystemRegister(sim, VB_PSW);
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sim->ph.step = 3;
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return 0;
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}
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/* Activate pseudo-halt */
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phActivate(sim, address, type);
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return 1;
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}
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/* Determine how long the CPU should wait before checking the monitor value */
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static uint32_t phUntil(VB *sim) {
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switch (sim->ph.operation) {
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case PH_DPSTTS : return phDPSTTS(sim);
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case PH_GAME_PAD: return sim->pad.si_stat;
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case PH_INTPND : return phINTPND(sim);
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case PH_TCR : return sim->tmr.until;
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case PH_TLHR : return sim->tmr.clocks;
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case PH_XPSTTS : return phXPSTTS(sim);
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}
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return 0; /* PH_NEVER */
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}
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#endif /* VBAPI */
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