562 lines
18 KiB
C
562 lines
18 KiB
C
/* This file is included into vb.c and cannot be compiled on its own. */
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#ifdef VBAPI
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/********************************* Constants *********************************/
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/* Analog output high-pass filter coefficient = 0.022 / (0.022 + 1 / 41700) */
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#define RC_A (float) (1 - 1 / 918.4)
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/******************************** Lookup Data ********************************/
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/* Noise feedback bit positions by tap field */
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static uint8_t NOISE_TAPS[] = { 14, 10, 13, 4, 8, 6, 9, 11 };
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/* Clock flags per output sample -- 479 clocks plus bit value */
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/* Ensures exactly 200,000 clocks every 417 samples = 41,700 Hz */
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static uint32_t SAMPLE_CLOCKS[] = {
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0xD6B6B5B5, 0x5ADAD6D6, 0x6D6B6B5B, 0xB5B5ADAD,
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0xD6D6B6B5, 0x6B5B5ADA, 0xAD6D6D6B, 0xB6B5B5AD,
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0x5ADAD6D6, 0x6B6B5B5B, 0xB5ADAD6D, 0xD6D6B6B5,
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0x5B5ADAD6, 1
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};
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/***************************** Callback Handlers *****************************/
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/* Samples buffer is full */
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#ifndef VB_DIRECT_SAMPLES
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#define VB_ON_SAMPLES sim->onSamples
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#else
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extern void VB_DIRECT_SAMPLES(VB *, void *, uint32_t);
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#define VB_ON_SAMPLES VB_DIRECT_SAMPLES
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#endif
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static void vsuOnSamples(VB *sim) {
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if (sim->onSamples != NULL)
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VB_ON_SAMPLES(sim, sim->vsu.out.samples, sim->vsu.out.capacity);
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}
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#undef VB_ON_SAMPLES
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/***************************** Module Functions ******************************/
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/* Stage the next frequency modification value */
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static void vsuNextFreqMod(VB *sim, Channel *chan) {
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uint16_t next;
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/* Sweep */
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if (sim->vsu.freqmod.func == 0) {
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next = chan->freq.current >> sim->vsu.freqmod.shift;
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if (sim->vsu.freqmod.dir == 0)
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next = chan->freq.current - next;
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else next = chan->freq.current + next;
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if (next > 2047)
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chan->int_.enb = 0;
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}
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/* Modulation */
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else {
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next = (chan->freq.written +
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sim->vsu.modulation[sim->vsu.freqmod.sample]) & 2047;
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if (sim->vsu.freqmod.sample != 31)
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sim->vsu.freqmod.sample++;
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else if (sim->vsu.freqmod.rep)
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sim->vsu.freqmod.sample = 0;
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}
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/* Configure state */
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sim->vsu.freqmod.next = next;
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}
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/* Process one channel */
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static void vsuEmulateChannel(VB *sim, int index, uint32_t clocks) {
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uint32_t bit; /* Pseudorandom bit */
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Channel *chan; /* Channel handle */
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int freqmod; /* Frequency modifications enabled */
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uint32_t until; /* Clocks to process sub-channel components */
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/* Select channel */
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chan = &sim->vsu.channels[index];
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/* Channel is disabled */
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if (!chan->int_.enb)
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return;
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/* Frequency modifications are active */
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freqmod =
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index == 4 && /* Channel 5 */
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sim->vsu.freqmod.enb && /* Modifications enabled */
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sim->vsu.freqmod.interval != 0 /* Modifications valid */
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;
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/* Process all clocks */
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do {
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/* Clocks until next state change */
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until = clocks;
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if (chan->clocks < until)
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until = chan->clocks;
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if (chan->env.enb && chan->env.clocks < until)
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until = chan->env.clocks;
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if (chan->int_.auto_ && chan->int_.clocks < until)
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until = chan->int_.clocks;
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if (freqmod && sim->vsu.freqmod.clocks < until)
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until = sim->vsu.freqmod.clocks;
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/* Manage clocks */
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clocks -= until;
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chan->clocks -= until;
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if (chan->env.enb)
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chan->env.clocks -= until;
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if (chan->int_.auto_)
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chan->int_.clocks -= until;
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if (freqmod)
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sim->vsu.freqmod.clocks -= until;
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/* Automatic shutoff */
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if (chan->int_.auto_ && chan->int_.clocks == 0) {
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chan->int_.enb = 0;
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return;
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}
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/* Next sample */
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if (chan->clocks == 0) {
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/* Wave */
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if (index != 5) {
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chan->clocks = 4 * (2048 - (uint32_t) chan->freq.current);
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chan->wave.sample = (chan->wave.sample + 1) & 31;
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}
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/* Noise */
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else {
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chan->clocks = 40 * (2048 - (uint32_t) chan->freq.current);
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bit = ((
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sim->vsu.noise.register_ >> NOISE_TAPS[sim->vsu.noise.tap]^
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sim->vsu.noise.register_ >> 7
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) & 1) ^ 1;
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sim->vsu.noise.register_ = bit |
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(sim->vsu.noise.register_ << 1 & 0x7FFE);
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}
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}
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/* Envelope modification */
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if (chan->env.enb && chan->env.clocks == 0) {
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if (chan->env.dir == 0 && chan->env.value != 0)
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chan->env.value--;
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else if (chan->env.dir == 1 && chan->env.value != 15)
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chan->env.value++;
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else if (chan->env.rep)
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chan->env.value = chan->env.reload;
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chan->env.clocks = ((uint32_t) chan->env.interval + 1) * 307220;
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}
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/* Frequency modification */
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if (freqmod && sim->vsu.freqmod.clocks == 0) {
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chan->freq.current = sim->vsu.freqmod.next;
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vsuNextFreqMod(sim, chan);
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if (!chan->int_.enb)
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return;
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sim->vsu.freqmod.clocks = (uint32_t) sim->vsu.freqmod.interval *
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(sim->vsu.freqmod.clk == 0 ? 19200 : 153600);
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}
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} while (clocks != 0);
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}
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/* Produce output for a channel */
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static void vsuOutputChannel(VB *sim, int index, uint16_t *output) {
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Channel *chan; /* Channel handle */
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uint32_t level; /* Stereo output level */
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uint32_t sample; /* Input sample */
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int e; /* Iterator */
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/* Select channel */
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chan = &sim->vsu.channels[index];
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/* Select input sample */
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sample =
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!chan->int_.enb ? 0 : /* Disabled */
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index == 5 ? (sim->vsu.noise.register_ & 1) ? 63 : 0 : /* Noise */
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chan->wave.wave > 4 ? 0 : /* Wave range */
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sim->vsu.waves[chan->wave.wave][chan->wave.sample] /* Wave */
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;
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/* Compute output samples */
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for (e = 0; e < 2; e++) {
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level = e == 0 ? chan->lrv.left : chan->lrv.right;
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level = (level * chan->env.value >> 3) + (level && chan->env.value);
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output[e] += level * sample;
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}
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}
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/* Write a value to S*EV0 */
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static void vsuWriteEV0(VB *sim, int index, uint8_t value) {
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Channel *chan = &sim->vsu.channels[index];
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/* Parse fields */
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chan->env.dir = value >> 3 & 1;
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chan->env.interval = value & 7;
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chan->env.value = value >> 4 & 15;
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chan->env.reload = chan->env.value;
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if (index == 4)
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vsuNextFreqMod(sim, chan);
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/* Configure state */
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chan->env.clocks = 307220 * ((uint32_t) chan->env.interval + 1);
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}
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/* Write a value to S*EV1 */
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static void vsuWriteEV1(VB *sim, int index, uint8_t value) {
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Channel *chan = &sim->vsu.channels[index];
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/* Parse fields */
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chan->env.enb = value & 1;
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chan->env.rep = value >> 1 & 1;
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/* Processing by channel */
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switch (index) {
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case 4: /* Channel 5 */
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sim->vsu.freqmod.enb = value >> 6 & 1;
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sim->vsu.freqmod.func = value >> 4 & 1;
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sim->vsu.freqmod.rep = value >> 5 & 1;
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vsuNextFreqMod(sim, chan);
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break;
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case 5: /* Channel 6 */
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sim->vsu.noise.tap = value >> 4 & 7;
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sim->vsu.noise.register_ = 0x0000;
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}
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}
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/* Write a value to S*FQH */
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static void vsuWriteFQH(VB *sim, int index, uint16_t value) {
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Channel *chan = &sim->vsu.channels[index];
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value = value << 8 & 0x0700;
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chan->freq.current = (chan->freq.current & 0x00FF) | value;
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chan->freq.written = (chan->freq.written & 0x00FF) | value;
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if (index == 4)
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vsuNextFreqMod(sim, chan);
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}
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/* Write a value to S*FQL */
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static void vsuWriteFQL(VB *sim, int index, uint8_t value) {
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Channel *chan = &sim->vsu.channels[index];
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chan->freq.current = (chan->freq.current & 0x0700) | value;
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chan->freq.written = (chan->freq.written & 0x0700) | value;
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if (index == 4)
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vsuNextFreqMod(sim, chan);
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}
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/* Write a value to S*INT */
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static void vsuWriteINT(VB *sim, int index, uint8_t value) {
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Channel *chan = &sim->vsu.channels[index];
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/* Parse fields */
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chan->int_.auto_ = value >> 5 & 1;
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chan->int_.enb = value >> 7 & 1;
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chan->int_.interval = value & 31;
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/* Update state */
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chan->int_.clocks = 76805 * ((uint32_t) chan->int_.interval + 1);
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if (chan->env.enb)
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chan->env.clocks = 307220 * ((uint32_t) chan->env.interval + 1);
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if (index != 5) {
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chan->wave.sample = 0;
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chan->clocks = 4 * (2048 - (uint32_t) chan->freq.current);
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} else {
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sim->vsu.noise.register_ = 0x0000;
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chan->clocks = 40 * (2048 - (uint32_t) chan->freq.current);
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}
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if (index == 4) {
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sim->vsu.freqmod.clocks = (uint32_t) sim->vsu.freqmod.interval *
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(sim->vsu.freqmod.clk == 0 ? 19200 : 153600);
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sim->vsu.freqmod.sample = 0;
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}
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}
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/* Write a value to S*LRV */
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static void vsuWriteLRV(VB *sim, int index, uint8_t value) {
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Channel *chan = &sim->vsu.channels[index];
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chan->lrv.left = value >> 4 & 15;
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chan->lrv.right = value & 15;
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}
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/* Write a value to S*RAM */
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static void vsuWriteRAM(VB *sim, int index, uint8_t value) {
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sim->vsu.channels[index].wave.wave = value & 7;
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}
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/* Write a value to S5SWP */
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static void vsuWriteSWP(VB *sim, uint8_t value) {
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uint32_t clocks;
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/* Parse fields */
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sim->vsu.freqmod.clk = value >> 7 & 1;
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sim->vsu.freqmod.dir = value >> 3 & 1;
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sim->vsu.freqmod.interval = value >> 4 & 7;
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sim->vsu.freqmod.shift = value & 7;
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/* Configure state */
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clocks = (uint32_t) sim->vsu.freqmod.interval *
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(sim->vsu.freqmod.clk == 0 ? 19200 : 153600);
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if (clocks < sim->vsu.freqmod.clocks)
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sim->vsu.freqmod.clocks = clocks;
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}
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/***************************** Module Functions ******************************/
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/* Process component */
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static void vsuEmulate(VB *sim, uint32_t clocks) {
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float i0; /* Current analog input sample */
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float o0; /* Current analog output sample */
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uint16_t output[2]; /* Digital output samples */
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uint32_t until; /* Clocks to process channels */
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int e, x; /* Iterators */
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/* Process all clocks */
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do {
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/* Clocks until next sample */
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until = clocks;
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if (sim->vsu.clocks < until)
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until = sim->vsu.clocks;
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/* Manage clocks */
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clocks -= until;
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sim->vsu.clocks -= until;
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/* Process all channels */
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for (x = 0; x < 6; x++)
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vsuEmulateChannel(sim, x, until);
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/* Wait for the current sample to finish */
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if (sim->vsu.clocks != 0)
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return;
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/* Compute the output sample */
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output[0] = output[1] = 0;
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for (x = 0; x < 6; x++)
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vsuOutputChannel(sim, x, output);
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/* Output sample */
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for (e = 0; e < 2; e++) {
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/* Compute the output sample for this stereo channel */
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i0 = (output[e] >> 4) / 685.0f;
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o0 = RC_A * (sim->vsu.out.o1[e] + i0 - sim->vsu.out.i1[e]);
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if (o0 < -1.0f) o0 = -1.0f;
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if (o0 > +1.0f) o0 = +1.0f;
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sim->vsu.out.i1[e] = i0;
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sim->vsu.out.o1[e] = o0;
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/* Output the sample to caller memory */
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if (
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sim->vsu.out.samples != NULL &&
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sim->vsu.out.offset >> 1 < sim->vsu.out.capacity
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) {
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/* Processing by data type */
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switch (sim->vsu.out.type) {
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case VB_S16:
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((int16_t *) sim->vsu.out.samples)
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[sim->vsu.out.offset++] = (int16_t)
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(o0 * 32767.0f + (o0 < 0.0f ? -0.5f : +0.5f));
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break;
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case VB_F32:
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((float *) sim->vsu.out.samples)
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[sim->vsu.out.offset++] = o0;
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break;
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}
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/* Invoke the samples callback */
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if (
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e == 1 &&
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sim->vsu.out.offset >> 1 == sim->vsu.out.capacity
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) vsuOnSamples(sim);
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}
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}
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/* Advance to the next sample */
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sim->vsu.sample += sim->vsu.sample == 416 ? -416 : 1;
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sim->vsu.clocks = 479 + (1 &
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SAMPLE_CLOCKS[sim->vsu.sample >> 5] >> (sim->vsu.sample & 31));
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} while (clocks != 0);
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}
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/* Simulate a hardware reset */
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static void vsuReset(VB *sim) {
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Channel *chan; /* Channel handle */
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int x, y; /* Iterators */
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/* Memory */
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for (x = 0; x < 32; x++) {
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sim->vsu.modulation[x] = 0;
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for (y = 0; y < 5; y++)
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sim->vsu.waves[y][x] = 0;
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}
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/* Channel state */
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for (x = 0; x < 6; x++) {
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chan = &sim->vsu.channels[x];
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chan->clocks = 0;
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chan->env.clocks = 0;
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chan->env.enb = 0;
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chan->env.dir = 0;
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chan->env.interval = 0;
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chan->env.reload = 0;
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chan->env.rep = 0;
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chan->env.value = 0;
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chan->freq.current = 0x000;
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chan->freq.written = 0x000;
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chan->lrv.left = 0;
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chan->lrv.right = 0;
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chan->int_.auto_ = 0;
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chan->int_.clocks = 0;
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chan->int_.enb = 0;
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chan->int_.interval = 0;
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chan->wave.sample = 0;
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chan->wave.wave = 0;
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}
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/* Other channel state */
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sim->vsu.freqmod.clk = 0;
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sim->vsu.freqmod.clocks = 0;
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sim->vsu.freqmod.dir = 0;
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sim->vsu.freqmod.enb = 0;
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sim->vsu.freqmod.func = 0;
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sim->vsu.freqmod.interval = 0;
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sim->vsu.freqmod.next = 0;
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sim->vsu.freqmod.rep = 0;
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sim->vsu.freqmod.sample = 0;
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sim->vsu.freqmod.shift = 0;
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sim->vsu.noise.register_ = 0;
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sim->vsu.noise.tap = 0;
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/* Other */
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sim->vsu.clocks = 479 + (SAMPLE_CLOCKS[0] & 1);
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sim->vsu.sample = 0;
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for (x = 0; x < 2; x++)
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sim->vsu.out.i1[x] = sim->vsu.out.o1[x] = 0;
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}
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/* Write a typed value to the VSU bus */
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static void vsuWrite(VB*sim,uint32_t address,int type,int32_t value,int debug){
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/* Only byte writes are allowed */
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switch (type) {
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case VB_S16:
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case VB_U16:
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case VB_S32:
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return;
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}
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/* Unmapped */
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if (address & 3)
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return;
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/* Working variables */
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address &= 0x7FF;
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/* Wave memory */
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if (address < 0x280) {
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if (debug || !(
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sim->vsu.channels[0].int_.enb |
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sim->vsu.channels[1].int_.enb |
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sim->vsu.channels[2].int_.enb |
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sim->vsu.channels[3].int_.enb |
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sim->vsu.channels[4].int_.enb |
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sim->vsu.channels[5].int_.enb
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)) sim->vsu.waves[address >> 7][address >> 2 & 31] = value & 63;
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}
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/* Modulation memory */
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else if (address < 0x300) {
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if (debug || !sim->vsu.channels[4].int_.enb)
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sim->vsu.modulation[address >> 2 & 31] = value;
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}
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/* I/O register */
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else switch (address >> 2) {
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case 0x400>>2: vsuWriteINT(sim, 0, value); break; /* S1INT */
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case 0x404>>2: vsuWriteLRV(sim, 0, value); break; /* S1LRV */
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case 0x408>>2: vsuWriteFQL(sim, 0, value); break; /* S1FQL */
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|
case 0x40C>>2: vsuWriteFQH(sim, 0, value); break; /* S1FQH */
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|
case 0x410>>2: vsuWriteEV0(sim, 0, value); break; /* S1EV0 */
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|
case 0x414>>2: vsuWriteEV1(sim, 0, value); break; /* S1EV1 */
|
|
case 0x418>>2: vsuWriteRAM(sim, 0, value); break; /* S1RAM */
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|
|
|
case 0x440>>2: vsuWriteINT(sim, 1, value); break; /* S2INT */
|
|
case 0x444>>2: vsuWriteLRV(sim, 1, value); break; /* S2LRV */
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|
case 0x448>>2: vsuWriteFQL(sim, 1, value); break; /* S2FQL */
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|
case 0x44C>>2: vsuWriteFQH(sim, 1, value); break; /* S2FQH */
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|
case 0x450>>2: vsuWriteEV0(sim, 1, value); break; /* S2EV0 */
|
|
case 0x454>>2: vsuWriteEV1(sim, 1, value); break; /* S2EV1 */
|
|
case 0x458>>2: vsuWriteRAM(sim, 1, value); break; /* S2RAM */
|
|
|
|
case 0x480>>2: vsuWriteINT(sim, 2, value); break; /* S3INT */
|
|
case 0x484>>2: vsuWriteLRV(sim, 2, value); break; /* S3LRV */
|
|
case 0x488>>2: vsuWriteFQL(sim, 2, value); break; /* S3FQL */
|
|
case 0x48C>>2: vsuWriteFQH(sim, 2, value); break; /* S3FQH */
|
|
case 0x490>>2: vsuWriteEV0(sim, 2, value); break; /* S3EV0 */
|
|
case 0x494>>2: vsuWriteEV1(sim, 2, value); break; /* S3EV1 */
|
|
case 0x498>>2: vsuWriteRAM(sim, 2, value); break; /* S3RAM */
|
|
|
|
case 0x4C0>>2: vsuWriteINT(sim, 3, value); break; /* S4INT */
|
|
case 0x4C4>>2: vsuWriteLRV(sim, 3, value); break; /* S4LRV */
|
|
case 0x4C8>>2: vsuWriteFQL(sim, 3, value); break; /* S4FQL */
|
|
case 0x4CC>>2: vsuWriteFQH(sim, 3, value); break; /* S4FQH */
|
|
case 0x4D0>>2: vsuWriteEV0(sim, 3, value); break; /* S4EV0 */
|
|
case 0x4D4>>2: vsuWriteEV1(sim, 3, value); break; /* S4EV1 */
|
|
case 0x4D8>>2: vsuWriteRAM(sim, 3, value); break; /* S4RAM */
|
|
|
|
case 0x500>>2: vsuWriteINT(sim, 4, value); break; /* S5INT */
|
|
case 0x504>>2: vsuWriteLRV(sim, 4, value); break; /* S5LRV */
|
|
case 0x508>>2: vsuWriteFQL(sim, 4, value); break; /* S5FQL */
|
|
case 0x50C>>2: vsuWriteFQH(sim, 4, value); break; /* S5FQH */
|
|
case 0x510>>2: vsuWriteEV0(sim, 4, value); break; /* S5EV0 */
|
|
case 0x514>>2: vsuWriteEV1(sim, 4, value); break; /* S5EV1 */
|
|
case 0x518>>2: vsuWriteRAM(sim, 4, value); break; /* S5RAM */
|
|
case 0x51C>>2: vsuWriteSWP(sim, value); break; /* S5SWP */
|
|
|
|
case 0x540>>2: vsuWriteINT(sim, 5, value); break; /* S6INT */
|
|
case 0x544>>2: vsuWriteLRV(sim, 5, value); break; /* S6LRV */
|
|
case 0x548>>2: vsuWriteFQL(sim, 5, value); break; /* S6FQL */
|
|
case 0x54C>>2: vsuWriteFQH(sim, 5, value); break; /* S6FQH */
|
|
case 0x550>>2: vsuWriteEV0(sim, 5, value); break; /* S6EV0 */
|
|
case 0x554>>2: vsuWriteEV1(sim, 5, value); break; /* S6EV1 */
|
|
|
|
case 0x580>>2: /* SSTOP */
|
|
if ((value & 1) == 0)
|
|
break;
|
|
sim->vsu.channels[0].int_.enb =
|
|
sim->vsu.channels[1].int_.enb =
|
|
sim->vsu.channels[2].int_.enb =
|
|
sim->vsu.channels[3].int_.enb =
|
|
sim->vsu.channels[4].int_.enb =
|
|
sim->vsu.channels[5].int_.enb = 0;
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif /* VBAPI */
|