232 lines
6.8 KiB
C
232 lines
6.8 KiB
C
/* This file is included into vb.c and cannot be compiled on its own. */
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#ifdef VBAPI
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/********************************* Constants *********************************/
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/* Memory access address masks by data type */
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static const uint32_t TYPE_MASKS[] = {
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0x07FFFFFF, /* S8 */
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0x07FFFFFF, /* U8 */
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0x07FFFFFE, /* S16 */
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0x07FFFFFE, /* U16 */
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0x07FFFFFC /* S32 */
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};
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/**************************** Forward references *****************************/
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static void vipRead (VB *, uint32_t, int, int32_t *);
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static void vipWrite(VB *, uint32_t, int, int32_t, int);
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/*************************** Sub-Module Functions ****************************/
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/* Read a typed value from a buffer in host memory */
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static int32_t busReadBuffer(uint8_t *data, int type) {
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/* Processing by data type */
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switch (type) {
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/* Generic implementation */
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#ifndef VB_LITTLE_ENDIAN
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case VB_S8 : return ((int8_t *)data)[0];
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case VB_U8 : return data [0];
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case VB_S16: return (int32_t) ((int8_t *)data)[1] << 8 | data[0];
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case VB_U16: return (int32_t) data [1] << 8 | data[0];
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case VB_S32: return
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(int32_t) data[3] << 24 | (int32_t) data[2] << 16 |
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(int32_t) data[1] << 8 | data[0];
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/* Little-endian host */
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#else
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case VB_S8 : return *(int8_t *) data;
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case VB_U8 : return * data;
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case VB_S16: return *(int16_t *) data;
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case VB_U16: return *(uint16_t *) data;
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case VB_S32: return *(int32_t *) data;
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#endif
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}
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return 0; /* Unreachable */
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}
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/* Write a typed value to a buffer in host memory */
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static void busWriteBuffer(uint8_t *data, int type, int32_t value) {
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/* Processing by data type */
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switch (type) {
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/* Generic implementation */
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#ifndef VB_LITTLE_ENDIAN
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case VB_S32: data[3] = value >> 24;
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data[2] = value >> 16; /* Fallthrough */
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case VB_S16: /* Fallthrough */
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case VB_U16: data[1] = value >> 8; /* Fallthrough */
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case VB_S8 : /* Fallthrough */
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case VB_U8 : data[0] = value;
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/* Little-endian host */
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#else
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case VB_S8 : /* Fallthrough */
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case VB_U8 : * data = value; return;
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case VB_S16: /* Fallthrough */
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case VB_U16: *(uint16_t *) data = value; return;
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case VB_S32: *(int32_t *) data = value; return;
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#endif
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}
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}
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/* Read a value from miscellaneous hardware I/O */
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static int32_t busReadMisc(VB *sim, uint8_t address, int type) {
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/* Unmapped */
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switch (type) {
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case VB_S8 : case VB_U8 : if (address & 3) return 0; break;
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case VB_S16: case VB_U16: if (address & 1) return 0;
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}
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/* Access by register */
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switch (address >> 2 & 15) {
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case 0x00>>2: break; /* CCR */
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case 0x04>>2: break; /* CCSR */
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case 0x08>>2: break; /* CDTR */
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case 0x0C>>2: break; /* CDRR */
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case 0x10>>2: return sim->pad.sdlr; /* SDLR */
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case 0x14>>2: return sim->pad.sdhr; /* SDHR */
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case 0x18>>2: return sim->tmr.counter & 0xFF; /* TLR */
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case 0x1C>>2: return sim->tmr.counter >> 8 & 0xFF; /* THR */
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case 0x20>>2: return tmrReadControl(sim); /* TCR */
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case 0x24>>2: return sim->wcr; /* WCR */
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case 0x28>>2: return padReadControl(sim); /* SCR */
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}
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/* Unmapped */
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return 0;
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}
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/* Write a value to miscellaneous hardware I/O */
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static void busWriteMisc(VB *sim, uint8_t address, int type, int32_t value) {
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/* Unmapped */
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switch (type) {
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case VB_S8 : case VB_U8 : if (address & 3) return; break;
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case VB_S16: case VB_U16: if (address & 1) return;
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}
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/* Access by register */
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switch (address >> 2 & 15) {
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case 0x00>>2: break; /* CCR */
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case 0x04>>2: break; /* CCSR */
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case 0x08>>2: break; /* CDTR */
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case 0x0C>>2: break; /* CDRR */
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case 0x18>>2: tmrWriteLow (sim, value); break; /* TLR */
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case 0x1C>>2: tmrWriteHigh (sim, value); break; /* THR */
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case 0x20>>2: tmrWriteControl(sim, value); break; /* TCR */
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case 0x24>>2: sim->wcr = value & 3; break; /* WCR */
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case 0x28>>2: padWriteControl(sim, value); break; /* SCR */
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}
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}
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/***************************** Library Functions *****************************/
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/* Read a typed value from the simulation bus */
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static void busRead(VB *sim, uint32_t address, int type, int32_t *value) {
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/* Working variables */
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address &= TYPE_MASKS[type];
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*value = 0;
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/* Process by address range */
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switch (address >> 24) {
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case 0: /* VIP */
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vipRead(sim, address, type, value);
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break;
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case 1: break; /* VSU */
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case 2: /* Misc. I/O */
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*value = busReadMisc(sim, address, type);
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break;
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case 3: break; /* Unmapped */
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case 4: break; /* Game Pak expansion */
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case 5: /* WRAM */
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*value = busReadBuffer(&sim->wram[address & 0x0000FFFF], type);
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break;
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case 6: /* Game Pak RAM */
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if (sim->cart.ram != NULL) {
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*value = busReadBuffer(
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&sim->cart.ram[address & sim->cart.ramMask], type);
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}
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break;
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case 7: /* Game Pak ROM */
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if (sim->cart.rom != NULL) {
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*value = busReadBuffer(
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&sim->cart.rom[address & sim->cart.romMask], type);
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}
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break;
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}
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}
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/* Write a typed value to the simulation bus */
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static void busWrite(VB*sim,uint32_t address,int type,int32_t value,int debug){
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/* Working variables */
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address &= TYPE_MASKS[type];
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/* Process by address range */
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switch (address >> 24) {
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case 0: /* VIP */
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vipWrite(sim, address, type, value, debug);
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break;
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case 1: break; /* VSU */
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case 2: /* Misc. I/O */
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busWriteMisc(sim, address, type, value);
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break;
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case 3: break; /* Unmapped */
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case 4: break; /* Game Pak expansion */
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case 5: /* WRAM */
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busWriteBuffer(&sim->wram[address & 0x0000FFFF], type, value);
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break;
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case 6: /* Game Pak RAM */
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if (sim->cart.ram != NULL) {
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busWriteBuffer(
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&sim->cart.ram[address & sim->cart.ramMask], type, value);
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}
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break;
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case 7: /* Game Pak ROM */
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if (debug && sim->cart.rom != NULL) {
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busWriteBuffer(
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&sim->cart.rom[address & sim->cart.romMask], type, value);
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}
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break;
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}
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}
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#endif /* VBAPI */
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