Pre-bit-string adjustments
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bfc2254b9e
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44
core/cpu.c
44
core/cpu.c
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@ -117,20 +117,6 @@
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#define CPU_XOR_BS 6
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#define CPU_XORN_BS 7
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/* Instruction code lengths by opcode */
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static const uint8_t INST_LENGTHS[] = {
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
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1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 1, 2, 2, 2, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2
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};
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/* Highest interrupt level by IRQ bit mask value */
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static const int8_t IRQ_LEVELS[] = {
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-1, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3,
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4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4
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};
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/********************************** Macros ***********************************/
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@ -145,6 +131,20 @@ static const int8_t IRQ_LEVELS[] = {
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/******************************** Lookup Data ********************************/
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/* Instruction code lengths by opcode */
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static const uint8_t INST_LENGTHS[] = {
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
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1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2,
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2, 2, 1, 2, 2, 2, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2
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};
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/* Highest interrupt level by IRQ bit mask value */
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static const int8_t IRQ_LEVELS[] = {
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-1, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3,
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4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4
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};
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/* Opdefs by opcode */
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static const uint8_t OPDEFS[] = {
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CPU_MOV_REG, CPU_ADD_REG, CPU_SUB , CPU_CMP_REG , /* 000000 */
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@ -407,7 +407,7 @@ static int cpuIRQ(VB *sim) {
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if (sim->cpu.psw.id | sim->cpu.psw.ep | sim->cpu.psw.np)
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return 0;
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level = IRQ_LEVELS[sim->cpu.irq];
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if (level > sim->cpu.psw.i)
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if (level == -1 || level > sim->cpu.psw.i)
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return 0;
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cpuThrow(sim, 0xFE00 | level << 4);
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return 1;
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@ -835,15 +835,7 @@ static int cpuST_OUT(VB *sim, int type) {
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}
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/* Update state */
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sim->cpu.clocks += cpuClocks(1);
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/* Wait for clocks taken */
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sim->cpu.step = 2;
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return 0;
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case 2:
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cpuSetReg2(sim, auxData.value);
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cpuAdvance(sim, cpuClocks(3)); /* TODO: Research */
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cpuAdvance(sim, cpuClocks(4)); /* TODO: Research */
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}
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return 0;
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}
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@ -1125,6 +1117,7 @@ static void cpuDIVU(VB *sim) {
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/* HALT */
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static void cpuHALT(VB *sim) {
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sim->cpu.halt = 1;
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sim->cpu.operation = CPU_HALTING;
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/* TODO: Research clocks */
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}
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@ -1309,6 +1302,7 @@ static void cpuREV(VB *sim) {
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x = (x << 2 & 0xCCCCCCCC) | (x >> 2 & 0x33333333);
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x = (x << 1 & 0xAAAAAAAA) | (x >> 1 & 0x55555555);
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cpuSetReg2(sim, x);
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cpuAdvance(sim, cpuClocks(22));
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}
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/* SAR immediate */
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@ -1436,6 +1430,7 @@ static void cpuXB(VB *sim) {
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uint32_t x = cpuGetReg2(sim);
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x = (x & 0xFFFF0000) | (x << 8 & 0x0000FF00) | (x >> 8 & 0x000000FF);
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cpuSetReg2(sim, x);
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cpuAdvance(sim, cpuClocks(6));
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}
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/* XH */
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@ -1443,6 +1438,7 @@ static void cpuXH(VB *sim) {
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uint32_t x = cpuGetReg2(sim);
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x = (x << 16 & 0xFFFF0000) | (x >> 16 & 0x0000FFFF);
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cpuSetReg2(sim, x);
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cpuAdvance(sim, cpuClocks(1));
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}
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/* XOR */
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