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Pre-bit-string adjustments

This commit is contained in:
Guy Perfect 2024-10-13 16:31:18 -05:00
parent bfc2254b9e
commit 2273761222
1 changed files with 20 additions and 24 deletions
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44
core/cpu.c
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@ -117,20 +117,6 @@
#define CPU_XOR_BS 6 #define CPU_XOR_BS 6
#define CPU_XORN_BS 7 #define CPU_XORN_BS 7
/* Instruction code lengths by opcode */
static const uint8_t INST_LENGTHS[] = {
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 1, 2, 2, 2, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2
};
/* Highest interrupt level by IRQ bit mask value */
static const int8_t IRQ_LEVELS[] = {
-1, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4
};
/********************************** Macros ***********************************/ /********************************** Macros ***********************************/
@ -145,6 +131,20 @@ static const int8_t IRQ_LEVELS[] = {
/******************************** Lookup Data ********************************/ /******************************** Lookup Data ********************************/
/* Instruction code lengths by opcode */
static const uint8_t INST_LENGTHS[] = {
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 1, 2, 2, 2, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2
};
/* Highest interrupt level by IRQ bit mask value */
static const int8_t IRQ_LEVELS[] = {
-1, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3,
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4
};
/* Opdefs by opcode */ /* Opdefs by opcode */
static const uint8_t OPDEFS[] = { static const uint8_t OPDEFS[] = {
CPU_MOV_REG, CPU_ADD_REG, CPU_SUB , CPU_CMP_REG , /* 000000 */ CPU_MOV_REG, CPU_ADD_REG, CPU_SUB , CPU_CMP_REG , /* 000000 */
@ -407,7 +407,7 @@ static int cpuIRQ(VB *sim) {
if (sim->cpu.psw.id | sim->cpu.psw.ep | sim->cpu.psw.np) if (sim->cpu.psw.id | sim->cpu.psw.ep | sim->cpu.psw.np)
return 0; return 0;
level = IRQ_LEVELS[sim->cpu.irq]; level = IRQ_LEVELS[sim->cpu.irq];
if (level > sim->cpu.psw.i) if (level == -1 || level > sim->cpu.psw.i)
return 0; return 0;
cpuThrow(sim, 0xFE00 | level << 4); cpuThrow(sim, 0xFE00 | level << 4);
return 1; return 1;
@ -835,15 +835,7 @@ static int cpuST_OUT(VB *sim, int type) {
} }
/* Update state */ /* Update state */
sim->cpu.clocks += cpuClocks(1); cpuAdvance(sim, cpuClocks(4)); /* TODO: Research */
/* Wait for clocks taken */
sim->cpu.step = 2;
return 0;
case 2:
cpuSetReg2(sim, auxData.value);
cpuAdvance(sim, cpuClocks(3)); /* TODO: Research */
} }
return 0; return 0;
} }
@ -1125,6 +1117,7 @@ static void cpuDIVU(VB *sim) {
/* HALT */ /* HALT */
static void cpuHALT(VB *sim) { static void cpuHALT(VB *sim) {
sim->cpu.halt = 1;
sim->cpu.operation = CPU_HALTING; sim->cpu.operation = CPU_HALTING;
/* TODO: Research clocks */ /* TODO: Research clocks */
} }
@ -1309,6 +1302,7 @@ static void cpuREV(VB *sim) {
x = (x << 2 & 0xCCCCCCCC) | (x >> 2 & 0x33333333); x = (x << 2 & 0xCCCCCCCC) | (x >> 2 & 0x33333333);
x = (x << 1 & 0xAAAAAAAA) | (x >> 1 & 0x55555555); x = (x << 1 & 0xAAAAAAAA) | (x >> 1 & 0x55555555);
cpuSetReg2(sim, x); cpuSetReg2(sim, x);
cpuAdvance(sim, cpuClocks(22));
} }
/* SAR immediate */ /* SAR immediate */
@ -1436,6 +1430,7 @@ static void cpuXB(VB *sim) {
uint32_t x = cpuGetReg2(sim); uint32_t x = cpuGetReg2(sim);
x = (x & 0xFFFF0000) | (x << 8 & 0x0000FF00) | (x >> 8 & 0x000000FF); x = (x & 0xFFFF0000) | (x << 8 & 0x0000FF00) | (x >> 8 & 0x000000FF);
cpuSetReg2(sim, x); cpuSetReg2(sim, x);
cpuAdvance(sim, cpuClocks(6));
} }
/* XH */ /* XH */
@ -1443,6 +1438,7 @@ static void cpuXH(VB *sim) {
uint32_t x = cpuGetReg2(sim); uint32_t x = cpuGetReg2(sim);
x = (x << 16 & 0xFFFF0000) | (x >> 16 & 0x0000FFFF); x = (x << 16 & 0xFFFF0000) | (x >> 16 & 0x0000FFFF);
cpuSetReg2(sim, x); cpuSetReg2(sim, x);
cpuAdvance(sim, cpuClocks(1));
} }
/* XOR */ /* XOR */