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Renaming "vb" variable to "sim"

This commit is contained in:
Guy Perfect 2023-03-10 19:00:45 -06:00
parent 133a5e7e82
commit 265aeed8cd
5 changed files with 713 additions and 713 deletions
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16
core/bus.c
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@ -112,7 +112,7 @@ static void busWriteBuffer(
/***************************** Module Functions ******************************/ /***************************** Module Functions ******************************/
/* Read a typed value from the simulation bus */ /* Read a typed value from the simulation bus */
static int32_t busRead(VB *vb, uint32_t address, int type) { static int32_t busRead(VB *sim, uint32_t address, int type) {
/* Processing by address region */ /* Processing by address region */
switch (address >> 24 & 7) { switch (address >> 24 & 7) {
@ -122,11 +122,11 @@ static int32_t busRead(VB *vb, uint32_t address, int type) {
case 3: return 0; /* Unmapped */ case 3: return 0; /* Unmapped */
case 4: return 0; /* Game pak expansion */ case 4: return 0; /* Game pak expansion */
case 5: return /* WRAM */ case 5: return /* WRAM */
busReadBuffer(vb->wram , 0x10000 , address, type); busReadBuffer(sim->wram , 0x10000 , address, type);
case 6: return /* Game pak RAM */ case 6: return /* Game pak RAM */
busReadBuffer(vb->cart.ram, vb->cart.ramSize, address, type); busReadBuffer(sim->cart.ram, sim->cart.ramSize, address, type);
case 7: return /* Game pak ROM */ case 7: return /* Game pak ROM */
busReadBuffer(vb->cart.rom, vb->cart.romSize, address, type); busReadBuffer(sim->cart.rom, sim->cart.romSize, address, type);
} }
/* Unreachable */ /* Unreachable */
@ -134,7 +134,7 @@ static int32_t busRead(VB *vb, uint32_t address, int type) {
} }
/* Write a typed value to the simulation bus */ /* Write a typed value to the simulation bus */
static void busWrite(VB *vb,uint32_t address,int type,int32_t value,int debug){ static void busWrite(VB*sim,uint32_t address,int type,int32_t value,int debug){
(void) debug; (void) debug;
/* Processing by address region */ /* Processing by address region */
@ -145,13 +145,13 @@ static void busWrite(VB *vb,uint32_t address,int type,int32_t value,int debug){
case 3: break; /* Unmapped */ case 3: break; /* Unmapped */
case 4: break; /* Game pak expansion */ case 4: break; /* Game pak expansion */
case 5: /* WRAM */ case 5: /* WRAM */
busWriteBuffer(vb->wram ,0x10000 ,address,type,value); busWriteBuffer(sim->wram ,0x10000 ,address,type,value);
break; break;
case 6: /* Game pak RAM */ case 6: /* Game pak RAM */
busWriteBuffer(vb->cart.ram,vb->cart.ramSize,address,type,value); busWriteBuffer(sim->cart.ram,sim->cart.ramSize,address,type,value);
break; break;
case 7: /* Game pak ROM */ case 7: /* Game pak ROM */
busWriteBuffer(vb->cart.rom,vb->cart.romSize,address,type,value); busWriteBuffer(sim->cart.rom,sim->cart.romSize,address,type,value);
break; break;
} }

1196
core/cpu.c
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File diff suppressed because it is too large Load Diff

180
core/vb.c
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@ -38,15 +38,15 @@ static uint32_t Min(uint32_t a, uint32_t b) {
/***************************** Module Functions ******************************/ /***************************** Module Functions ******************************/
/* Process a simulation for a given number of clocks */ /* Process a simulation for a given number of clocks */
static int sysEmulate(VB *vb, uint32_t clocks) { static int sysEmulate(VB *sim, uint32_t clocks) {
return return
cpuEmulate(vb, clocks) cpuEmulate(sim, clocks)
; ;
} }
/* Determine how many clocks can be simulated without a breakpoint */ /* Determine how many clocks can be simulated without a breakpoint */
static uint32_t sysUntil(VB *vb, uint32_t clocks) { static uint32_t sysUntil(VB *sim, uint32_t clocks) {
clocks = cpuUntil(vb, clocks); clocks = cpuUntil(sim, clocks);
return clocks; return clocks;
} }
@ -55,21 +55,21 @@ static uint32_t sysUntil(VB *vb, uint32_t clocks) {
/************************************ API ************************************/ /************************************ API ************************************/
/* Process a simulation */ /* Process a simulation */
int vbEmulate(VB *vb, uint32_t *clocks) { int vbEmulate(VB *sim, uint32_t *clocks) {
int brk; /* A break was requested */ int brk; /* A break was requested */
uint32_t until; /* Number of clocks during which no break will occur */ uint32_t until; /* Number of clocks during which no break will occur */
/* Process all clocks */ /* Process all clocks */
for (brk = 0; *clocks != 0 && !brk; *clocks -= until) { for (brk = 0; *clocks != 0 && !brk; *clocks -= until) {
until = sysUntil (vb, *clocks); until = sysUntil (sim, *clocks);
brk = sysEmulate(vb, until ); brk = sysEmulate(sim, until );
} }
return brk; return brk;
} }
/* Process multiple simulations */ /* Process multiple simulations */
int vbEmulateEx(VB **vbs, int count, uint32_t *clocks) { int vbEmulateEx(VB **sims, int count, uint32_t *clocks) {
int brk; /* A break was requested */ int brk; /* A break was requested */
uint32_t until; /* Number of clocks during which no break will occur */ uint32_t until; /* Number of clocks during which no break will occur */
int x; /* Iterator */ int x; /* Iterator */
@ -78,160 +78,160 @@ int vbEmulateEx(VB **vbs, int count, uint32_t *clocks) {
for (brk = 0; *clocks != 0 && !brk; *clocks -= until) { for (brk = 0; *clocks != 0 && !brk; *clocks -= until) {
until = *clocks; until = *clocks;
for (x = 0; x < count; x++) for (x = 0; x < count; x++)
until = sysUntil (vbs[x], until); until = sysUntil (sims[x], until);
for (x = 0; x < count; x++) for (x = 0; x < count; x++)
brk |= sysEmulate(vbs[x], until); brk |= sysEmulate(sims[x], until);
} }
return brk; return brk;
} }
/* Retrieve a current breakpoint handler */ /* Retrieve a current breakpoint handler */
void* vbGetCallback(VB *vb, int id) { void* vbGetCallback(VB *sim, int id) {
switch (id) { switch (id) {
case VB_ONEXCEPTION: return *(void **)&vb->onException; case VB_ONEXCEPTION: return *(void **)&sim->onException;
case VB_ONEXECUTE : return *(void **)&vb->onExecute; case VB_ONEXECUTE : return *(void **)&sim->onExecute;
case VB_ONFETCH : return *(void **)&vb->onFetch; case VB_ONFETCH : return *(void **)&sim->onFetch;
case VB_ONREAD : return *(void **)&vb->onRead; case VB_ONREAD : return *(void **)&sim->onRead;
case VB_ONWRITE : return *(void **)&vb->onWrite; case VB_ONWRITE : return *(void **)&sim->onWrite;
} }
return NULL; return NULL;
} }
/* Retrieve the value of a register */ /* Retrieve the value of a register */
int32_t vbGetRegister(VB *vb, int type, int id) { int32_t vbGetRegister(VB *sim, int type, int id) {
switch (type) { switch (type) {
case VB_PROGRAM: case VB_PROGRAM:
return id < 0 || id > 31 ? 0 : vb->cpu.program[id]; return id < 0 || id > 31 ? 0 : sim->cpu.program[id];
case VB_SYSTEM: case VB_SYSTEM:
return cpuGetSystemRegister(vb, id); return cpuGetSystemRegister(sim, id);
case VB_OTHER: case VB_OTHER:
switch (id) { switch (id) {
case VB_PC: return vb->cpu.pc; case VB_PC: return sim->cpu.pc;
} }
} }
return 0; /* Invalid type */ return 0; /* Invalid type */
} }
/* Retrieve a handle to the current cartridge ROM data */ /* Retrieve a handle to the current cartridge ROM data */
uint8_t* vbGetROM(VB *vb, uint32_t *size) { uint8_t* vbGetROM(VB *sim, uint32_t *size) {
if (size != NULL) if (size != NULL)
*size = vb->cart.romSize; *size = sim->cart.romSize;
return vb->cart.rom; return sim->cart.rom;
} }
/* Retrieve a handle to the current cartridge RAM data */ /* Retrieve a handle to the current cartridge RAM data */
uint8_t* vbGetSRAM(VB *vb, uint32_t *size) { uint8_t* vbGetSRAM(VB *sim, uint32_t *size) {
if (size != NULL) if (size != NULL)
*size = vb->cart.ramSize; *size = sim->cart.ramSize;
return vb->cart.ram; return sim->cart.ram;
} }
/* Prepare a simulation instance for use */ /* Prepare a simulation instance for use */
void vbInit(VB *vb) { void vbInit(VB *sim) {
/* Breakpoint handlers */ /* Breakpoint handlers */
vb->onException = NULL; sim->onException = NULL;
vb->onExecute = NULL; sim->onExecute = NULL;
vb->onFetch = NULL; sim->onFetch = NULL;
vb->onRead = NULL; sim->onRead = NULL;
vb->onWrite = NULL; sim->onWrite = NULL;
/* Game pak */ /* Game pak */
vb->cart.ram = NULL; sim->cart.ram = NULL;
vb->cart.ramSize = 0; sim->cart.ramSize = 0;
vb->cart.rom = NULL; sim->cart.rom = NULL;
vb->cart.romSize = 0; sim->cart.romSize = 0;
/* Hardware reset */ /* Hardware reset */
vbReset(vb); vbReset(sim);
} }
/* Read a value from memory */ /* Read a value from memory */
int32_t vbRead(VB *vb, uint32_t address, int type) { int32_t vbRead(VB *sim, uint32_t address, int type) {
return busRead(vb, address, type); return busRead(sim, address, type);
} }
/* Read multiple bytes from memory */ /* Read multiple bytes from memory */
void vbReadEx(VB *vb, uint32_t address, uint8_t *buffer, uint32_t length) { void vbReadEx(VB *sim, uint32_t address, uint8_t *buffer, uint32_t length) {
while (length--) *buffer++ = busRead(vb, address++, VB_U8); while (length--) *buffer++ = busRead(sim, address++, VB_U8);
} }
/* Simulate a hardware reset */ /* Simulate a hardware reset */
void vbReset(VB *vb) { void vbReset(VB *sim) {
int x; /* Iterator */ int x; /* Iterator */
/* Reset WRAM (the hardware does not do this) */ /* Reset WRAM (the hardware does not do this) */
for (x = 0; x < 0x10000; x++) for (x = 0; x < 0x10000; x++)
vb->wram[x] = 0x00; sim->wram[x] = 0x00;
/* CPU (normal) */ /* CPU (normal) */
vb->cpu.pc = 0xFFFFFFF0; sim->cpu.pc = 0xFFFFFFF0;
cpuSetSystemRegister(vb, VB_ECR, 0x0000FFF0, 1); cpuSetSystemRegister(sim, VB_ECR, 0x0000FFF0, 1);
cpuSetSystemRegister(vb, VB_PSW, 0x00008000, 1); cpuSetSystemRegister(sim, VB_PSW, 0x00008000, 1);
for (x = 0; x < 5; x++) for (x = 0; x < 5; x++)
vb->cpu.irq[x] = 0; sim->cpu.irq[x] = 0;
/* CPU (extra, hardware doesn't do this) */ /* CPU (extra, hardware doesn't do this) */
vb->cpu.adtre = 0x00000000; sim->cpu.adtre = 0x00000000;
vb->cpu.eipc = 0x00000000; sim->cpu.eipc = 0x00000000;
vb->cpu.eipsw = 0x00000000; sim->cpu.eipsw = 0x00000000;
vb->cpu.fepc = 0x00000000; sim->cpu.fepc = 0x00000000;
vb->cpu.fepsw = 0x00000000; sim->cpu.fepsw = 0x00000000;
vb->cpu.sr29 = 0x00000000; sim->cpu.sr29 = 0x00000000;
vb->cpu.sr31 = 0x00000000; sim->cpu.sr31 = 0x00000000;
cpuSetSystemRegister(vb, VB_CHCW, 0x00000000, 1); cpuSetSystemRegister(sim, VB_CHCW, 0x00000000, 1);
for (x = 0; x < 32; x++) for (x = 0; x < 32; x++)
vb->cpu.program[x] = 0x00000000; sim->cpu.program[x] = 0x00000000;
/* CPU (internal) */ /* CPU (internal) */
vb->cpu.bitstring = 0; sim->cpu.bitstring = 0;
vb->cpu.clocks = 0; sim->cpu.clocks = 0;
vb->cpu.exception = 0; sim->cpu.exception = 0;
vb->cpu.stage = CPU_FETCH; sim->cpu.stage = CPU_FETCH;
vb->cpu.step = 0; sim->cpu.step = 0;
} }
/* Specify a breakpoint handler */ /* Specify a breakpoint handler */
void* vbSetCallback(VB *vb, int id, void *proc) { void* vbSetCallback(VB *sim, int id, void *proc) {
void *prev = vbGetCallback(vb, id); void *prev = vbGetCallback(sim, id);
switch (id) { switch (id) {
case VB_ONEXCEPTION: *(void **)&vb->onException = proc; break; case VB_ONEXCEPTION: *(void **)&sim->onException = proc; break;
case VB_ONEXECUTE : *(void **)&vb->onExecute = proc; break; case VB_ONEXECUTE : *(void **)&sim->onExecute = proc; break;
case VB_ONFETCH : *(void **)&vb->onFetch = proc; break; case VB_ONFETCH : *(void **)&sim->onFetch = proc; break;
case VB_ONREAD : *(void **)&vb->onRead = proc; break; case VB_ONREAD : *(void **)&sim->onRead = proc; break;
case VB_ONWRITE : *(void **)&vb->onWrite = proc; break; case VB_ONWRITE : *(void **)&sim->onWrite = proc; break;
} }
return prev; return prev;
} }
/* Specify a value for a register */ /* Specify a value for a register */
int32_t vbSetRegister(VB *vb, int type, int id, int32_t value) { int32_t vbSetRegister(VB *sim, int type, int id, int32_t value) {
switch (type) { switch (type) {
case VB_PROGRAM: case VB_PROGRAM:
return id < 1 || id > 31 ? 0 : (vb->cpu.program[id] = value); return id < 1 || id > 31 ? 0 : (sim->cpu.program[id] = value);
case VB_SYSTEM: case VB_SYSTEM:
return cpuSetSystemRegister(vb, id, value, 1); return cpuSetSystemRegister(sim, id, value, 1);
case VB_OTHER: case VB_OTHER:
switch (id) { switch (id) {
case VB_PC: case VB_PC:
vb->cpu.bitstring = 0; sim->cpu.bitstring = 0;
vb->cpu.clocks = 0; sim->cpu.clocks = 0;
vb->cpu.exception = 0; sim->cpu.exception = 0;
vb->cpu.stage = CPU_FETCH; sim->cpu.stage = CPU_FETCH;
return vb->cpu.pc = value & 0xFFFFFFFE; return sim->cpu.pc = value & 0xFFFFFFFE;
} }
} }
return 0; /* Invalid type or ID */ return 0; /* Invalid type or ID */
} }
/* Specify a cartridge ROM buffer */ /* Specify a cartridge ROM buffer */
int vbSetROM(VB *vb, uint8_t *data, uint32_t size) { int vbSetROM(VB *sim, uint8_t *data, uint32_t size) {
/* Specifying no ROM */ /* Specifying no ROM */
if (data == NULL) { if (data == NULL) {
vb->cart.rom = NULL; sim->cart.rom = NULL;
vb->cart.romSize = 0; sim->cart.romSize = 0;
return 0; return 0;
} }
@ -243,18 +243,18 @@ int vbSetROM(VB *vb, uint8_t *data, uint32_t size) {
) return 1; ) return 1;
/* Register the ROM data */ /* Register the ROM data */
vb->cart.rom = data; sim->cart.rom = data;
vb->cart.romSize = size; sim->cart.romSize = size;
return 0; return 0;
} }
/* Specify a cartridge RAM buffer */ /* Specify a cartridge RAM buffer */
int vbSetSRAM(VB *vb, uint8_t *data, uint32_t size) { int vbSetSRAM(VB *sim, uint8_t *data, uint32_t size) {
/* Specifying no SRAM */ /* Specifying no SRAM */
if (data == NULL) { if (data == NULL) {
vb->cart.ram = NULL; sim->cart.ram = NULL;
vb->cart.ramSize = 0; sim->cart.ramSize = 0;
return 0; return 0;
} }
@ -266,17 +266,17 @@ int vbSetSRAM(VB *vb, uint8_t *data, uint32_t size) {
) return 1; ) return 1;
/* Register the SRAM data */ /* Register the SRAM data */
vb->cart.ram = data; sim->cart.ram = data;
vb->cart.ramSize = size; sim->cart.ramSize = size;
return 0; return 0;
} }
/* Write a value to memory */ /* Write a value to memory */
void vbWrite(VB *vb, uint32_t address, int type, int32_t value) { void vbWrite(VB *sim, uint32_t address, int type, int32_t value) {
busWrite(vb, address, type, value, 1); busWrite(sim, address, type, value, 1);
} }
/* Write multiple values to memory */ /* Write multiple values to memory */
void vbWriteEx(VB *vb, uint32_t address, uint8_t *buffer, uint32_t length) { void vbWriteEx(VB *sim, uint32_t address, uint8_t *buffer, uint32_t length) {
while (length--) busWrite(vb, address++, VB_U8, *buffer++, 1); while (length--) busWrite(sim, address++, VB_U8, *buffer++, 1);
} }

32
core/vb.h
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@ -195,22 +195,22 @@ struct VB {
/************************************ API ************************************/ /************************************ API ************************************/
VBAPI int vbEmulate (VB *vb, uint32_t *clocks); VBAPI int vbEmulate (VB *sim, uint32_t *clocks);
VBAPI int vbEmulateEx (VB **vbs, int count, uint32_t *clocks); VBAPI int vbEmulateEx (VB **sims, int count, uint32_t *clocks);
VBAPI void* vbGetCallback(VB *vb, int id); VBAPI void* vbGetCallback(VB *sim, int id);
VBAPI int32_t vbGetRegister(VB *vb, int type, int id); VBAPI int32_t vbGetRegister(VB *sim, int type, int id);
VBAPI uint8_t* vbGetROM (VB *vb, uint32_t *size); VBAPI uint8_t* vbGetROM (VB *sim, uint32_t *size);
VBAPI uint8_t* vbGetSRAM (VB *vb, uint32_t *size); VBAPI uint8_t* vbGetSRAM (VB *sim, uint32_t *size);
VBAPI void vbInit (VB *vb); VBAPI void vbInit (VB *sim);
VBAPI int32_t vbRead (VB *vb, uint32_t address, int type); VBAPI int32_t vbRead (VB *sim, uint32_t address, int type);
VBAPI void vbReadEx (VB *vb, uint32_t address, uint8_t *buffer, uint32_t length); VBAPI void vbReadEx (VB *sim, uint32_t address, uint8_t *buffer, uint32_t length);
VBAPI void vbReset (VB *vb); VBAPI void vbReset (VB *sim);
VBAPI void* vbSetCallback(VB *vb, int id, void *proc); VBAPI void* vbSetCallback(VB *sim, int id, void *proc);
VBAPI int32_t vbSetRegister(VB *vb, int type, int id, int32_t value); VBAPI int32_t vbSetRegister(VB *sim, int type, int id, int32_t value);
VBAPI int vbSetROM (VB *vb, uint8_t *data, uint32_t size); VBAPI int vbSetROM (VB *sim, uint8_t *data, uint32_t size);
VBAPI int vbSetSRAM (VB *vb, uint8_t *data, uint32_t size); VBAPI int vbSetSRAM (VB *sim, uint8_t *data, uint32_t size);
VBAPI void vbWrite (VB *vb, uint32_t address, int type, int32_t value); VBAPI void vbWrite (VB *sim, uint32_t address, int type, int32_t value);
VBAPI void vbWriteEx (VB *vb, uint32_t address, uint8_t *buffer, uint32_t length); VBAPI void vbWriteEx (VB *sim, uint32_t address, uint8_t *buffer, uint32_t length);

2
web/core/Core.js
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@ -147,7 +147,7 @@ class Core {
} }
// Retrieve the value of a program register // Retrieve the value of a program register
getSystemRegister(sim, id, options) { getProgramRegister(sim, id, options) {
return this.message({ return this.message({
command: "getProgramRegister", command: "getProgramRegister",
id : id, id : id,