Implementing CPU emulation logic
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@ -234,6 +234,7 @@ typedef struct {
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*****************************************************************************/
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VUEAPI int32_t vueEmulate (VUE *vue, int32_t maxCycles);
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VUEAPI int32_t vueGetBreakCode(VUE *vue);
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VUEAPI int32_t vueGetRegister (VUE *vue, int32_t index, vbool system);
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VUEAPI void vueInitialize (VUE *vue);
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VUEAPI int32_t vueRead (VUE *vue, uint32_t address, int32_t type);
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@ -198,6 +198,11 @@ int32_t vueEmulate(VUE *vue, int32_t maxCycles) {
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return maxCycles;
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}
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/* Retrieve the application break code */
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int32_t vueGetBreakCode(VUE *vue) {
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return vue == NULL ? 0 : vue->breakCode;
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}
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/* Retrieve the value of a register */
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int32_t vueGetRegister(VUE *vue, int32_t index, vbool system) {
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@ -169,7 +169,7 @@ class CPUWindow extends ChildWindow {
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// Private Methods //
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///////////////////////////////////////////////////////////////////////////
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// Determine the maximum character width of a hex character in a font
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// Determine the maximum width of a hex character in a font
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private static Dimension measureHex(Font font) {
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int ret = 0;
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Dimension size = null;
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@ -0,0 +1,21 @@
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package vue;
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// Access state
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public class Access {
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// Instance fields
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public int address; // CPU bus address
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public int fetch; // Index of machine code unit
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public int type; // Data type
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public int value; // Value read/to write
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///////////////////////////////////////////////////////////////////////////
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// Constructors //
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///////////////////////////////////////////////////////////////////////////
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// Default constructor
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Access() { }
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}
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@ -10,9 +10,12 @@ class CPU {
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private JavaVUE vue; // Emulation state
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// Package fields
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Access access; // Access state
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int cycles; // Cycles until next stage
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int exception; // Exception code
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int fetch; // Fetch unit index
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Instruction inst; // Instruction state
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int irq; // Interrupt lines
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int[] jumpFrom; // Source PCs of most recent jumps
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int[] jumpTo; // Destination PCs of most recent jumps
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int stage; // Current processing stage
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@ -67,14 +70,23 @@ class CPU {
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///////////////////////////////////////////////////////////////////////////
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// Stages
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static final int FATAL = -1;
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static final int FETCH = 0;
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static final int EXECUTE = 1;
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static final int HALT = 2;
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static final int EXCEPTION = 3;
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static final int FATAL = 4;
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static final int CLEAR = 5;
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static final int DUMP = 6;
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static final int RESTORE = 7;
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static final int EXCEPTION = 2;
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static final int HALT = 3;
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static final int CLEAR = 4;
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static final int DUMP = 5;
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static final int RESTORE = 6;
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// Instruction cycle counts
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private static final byte[] CYCLES = {
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1, 1, 28, 1, 1, 1, 1, 1, 1, 26, 12, 1, 1, 10, 14, 16,
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38, 44, 36, 1, 5, 5, 5, 3, 3, 3, 5, 5, 5, 8, 1, 1,
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1, 1, 1, 9, 13, 30, 13, 1, 1, 1, 1, 1, 1, 4, 4, 4,
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10, 22, 1, 1, 1, 1, 1, 1, 12, 1, 1, 1, 1, 1, 4, 4,
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4, 8, 1, 28, 15, 14, 6, 1, 1, 1, 1, 1
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};
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@ -84,6 +96,8 @@ class CPU {
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// Default constructor
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CPU(JavaVUE vue) {
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access = new Access();
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inst = new Instruction();
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jumpFrom = new int[3];
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jumpTo = new int[3];
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program = new int[32];
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@ -96,6 +110,33 @@ class CPU {
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// Package Methods //
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///////////////////////////////////////////////////////////////////////////
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// Process the simulation
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void emulate(int cycles) {
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// The CPU is in permanent halt
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if (stage == FATAL)
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return;
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// Process for the given number of cycles
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do {
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// The next event occurs after the given number of cycles
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if (this.cycles > cycles) {
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this.cycles -= cycles;
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return;
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}
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// Processing by stage
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switch (stage) {
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case FETCH : if (fetch ()) return;
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case EXECUTE : if (execute ()) return;
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case HALT : testException(); break;
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case EXCEPTION: if (exception()) return;
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}
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} while (cycles > 0);
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}
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// Read a system register
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int getSystemRegister(int index) {
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switch (index) {
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@ -132,7 +173,9 @@ class CPU {
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// Configure instance fields
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cycles = 0; // Duration of first fetch
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exception = 0;
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fetch = 0;
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irq = 0;
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stage = FETCH;
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// Clear all registers (hardware only sets ECR, PC and PSW)
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@ -224,4 +267,227 @@ class CPU {
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return test(condition & 7) ^ 1;
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}
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// Determine the number of CPU cycles until something can happen
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int until(int cycles) {
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if (stage == FATAL || stage == HALT)
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return cycles;
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return cycles < 0 ? this.cycles : Math.min(cycles, this.cycles);
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}
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///////////////////////////////////////////////////////////////////////////
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// Private Methods //
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///////////////////////////////////////////////////////////////////////////
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// Operations for exception stage
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private boolean exception() {
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// Application callback
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if (vue.onException != null) {
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vue.breakCode = vue.onException.call(vue, exception);
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if (vue.breakCode != 0)
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return true;
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}
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exception &= 0xFFFF;
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boolean isIRQ = (exception & 0xFF00) == 0xFE00;
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int psw = getSystemRegister(VUE.PSW);
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// Fatal exception
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if (psw_np != 0) {
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vue.write(0x00000000, VUE.S32, 0xFFFF0000 | exception);
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vue.write(0x00000004, VUE.S32, psw);
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vue.write(0x00000008, VUE.S32, pc);
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}
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// Duplexed exception
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if (psw_ep != 0) {
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ecr_fecc = exception;
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fepc = pc;
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fepsw = psw;
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pc = 0xFFFFFFD0;
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}
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// Regular exception
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else {
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ecr_eicc = exception;
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eipc = pc;
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eipsw = psw;
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pc = 0xFFFF0000 | exception & 0xFFF0;
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if (pc == 0xFFFFFF70) // FIV
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pc = 0xFFFFFF60;
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}
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// Interrupt
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if (isIRQ)
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psw_i = Math.min(15, exception >> 4 & 15);
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// Common processing
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exception = 0;
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psw_ae = 0;
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psw_id = 1;
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stage = FETCH;
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return false;
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}
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// Operations for execute stage
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private boolean execute() {
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// Application callback
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if (vue.onExecute != null) {
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vue.breakCode = vue.onExecute.call(vue, inst);
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if (vue.breakCode != 0)
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return true;
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}
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// Determine the default number of cycles for the instruction
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if (inst.id >= 0 && inst.id <= 75)
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cycles = CYCLES[inst.id];
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// Processing by instruction ID
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switch (inst.id) {
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//case VUE.ADD_IMM: ADD_IMM(); break;
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//case VUE.ADD_REG: ADD_REG(); break;
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//case VUE.ADDF_S : ADDF_S (); break;
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//case VUE.ADDI : ADDI (); break;
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//case VUE.AND : AND (); break;
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//case VUE.ANDBSU : ANDBSU (); break;
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//case VUE.ANDI : ANDI (); break;
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//case VUE.ANDNBSU: ANDNBSU(); break;
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//case VUE.BCOND : BCOND (); break;
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//case VUE.CAXI : CAXI (); break;
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//case VUE.CLI : CLI (); break;
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//case VUE.CMP_IMM: CMP_IMM(); break;
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//case VUE.CMP_REG: CMP_REG(); break;
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//case VUE.CMPF_S : CMPF_S (); break;
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//case VUE.CVT_SW : CVT_SW (); break;
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//case VUE.CVT_WS : CVT_WS (); break;
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//case VUE.DIV : DIV (); break;
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//case VUE.DIVF_S : DIVF_S (); break;
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//case VUE.DIVU : DIVU (); break;
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//case VUE.HALT : HALT (); break;
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//case VUE.IN_B : IN_B (); break;
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//case VUE.IN_H : IN_H (); break;
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//case VUE.IN_W : IN_W (); break;
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//case VUE.JAL : JAL (); break;
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//case VUE.JMP : JMP (); break;
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//case VUE.JR : JR (); break;
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//case VUE.LD_B : LD_B (); break;
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//case VUE.LD_H : LD_H (); break;
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//case VUE.LD_W : LD_W (); break;
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//case VUE.LDSR : LDSR (); break;
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//case VUE.MOV_IMM: MOV_IMM(); break;
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//case VUE.MOV_REG: MOV_REG(); break;
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//case VUE.MOVBSU : MOVBSU (); break;
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//case VUE.MOVEA : MOVEA (); break;
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//case VUE.MOVHI : MOVHI (); break;
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//case VUE.MPYHW : MPYHW (); break;
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//case VUE.MUL : MUL (); break;
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//case VUE.MULF_S : MULF_S (); break;
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//case VUE.MULU : MULU (); break;
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//case VUE.NOT : NOT (); break;
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//case VUE.NOTBSU : NOTBSU (); break;
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//case VUE.OR : OR (); break;
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//case VUE.ORBSU : ORBSU (); break;
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//case VUE.ORI : ORI (); break;
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//case VUE.ORNBSU : ORNBSU (); break;
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//case VUE.OUT_B : OUT_B (); break;
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//case VUE.OUT_H : OUT_H (); break;
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//case VUE.OUT_W : OUT_W (); break;
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//case VUE.RETI : RETI (); break;
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//case VUE.REV : REV (); break;
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//case VUE.SAR_IMM: SAR_IMM(); break;
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//case VUE.SAR_REG: SAR_REG(); break;
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//case VUE.SCH0BSD: SCH0BSD(); break;
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//case VUE.SCH0BSU: SCH0BSU(); break;
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//case VUE.SCH1BSD: SCH1BSD(); break;
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//case VUE.SCH1BSU: SCH1BSU(); break;
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//case VUE.SEI : SEI (); break;
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//case VUE.SETF : SETF (); break;
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//case VUE.SHL_IMM: SHL_IMM(); break;
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//case VUE.SHL_REG: SHL_REG(); break;
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//case VUE.SHR_IMM: SHR_IMM(); break;
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//case VUE.SHR_REG: SHR_REG(); break;
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//case VUE.ST_B : ST_B (); break;
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//case VUE.ST_H : ST_H (); break;
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//case VUE.ST_W : ST_W (); break;
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//case VUE.STSR : STSR (); break;
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//case VUE.SUB : SUB (); break;
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//case VUE.SUBF_S : SUBF_S (); break;
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//case VUE.TRAP : TRAP (); break;
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//case VUE.TRNC_SW: TRNC_SW(); break;
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//case VUE.XB : XB (); break;
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//case VUE.XH : XH (); break;
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//case VUE.XOR : XOR (); break;
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//case VUE.XORBSU : XORBSU (); break;
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//case VUE.XORI : XORI (); break;
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//case VUE.XORNBSU: XORNBSU(); break;
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default: exception = 0xFF90; // Invalid instruction
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}
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// Common processing
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pc += inst.size;
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program[0] = 0;
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testException();
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return false;
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}
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// Operations for fetch stage
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private boolean fetch() {
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// Read the bits from the bus
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access.address = pc + (fetch << 1);
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access.fetch = fetch;
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access.type = VUE.U16;
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access.value = vue.read(access.address, VUE.U16);
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// Application callback
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if (vue.onRead != null) {
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vue.breakCode = vue.onRead.call(vue, access);
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if (vue.breakCode != 0)
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return true;
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}
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// First unit
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if (fetch == 0) {
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inst.bits = access.value << 16;
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if (Instruction.size(access.value & 0x3F) == 4) {
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fetch = 1;
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return false;
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}
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}
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// Second unit
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else {
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inst.bits |= access.value & 0xFFFF;
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fetch = 0;
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}
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// Decode the instruction and advance to execute stage
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inst.decode(inst.bits);
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stage = EXECUTE;
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return false;
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}
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// Check for an exception or interrupt
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private void testException() {
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// Check for an interrupt
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if (irq != 0 && (exception | psw_id | psw_ep | psw_np) == 0) {
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int level;
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for (level = 4; level >= 0; level--)
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if ((irq >> level & 1) != 0)
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break;
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exception = 0xFE00 | level << 4;
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}
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// Check for an exception
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if (exception != 0) {
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cycles = 0;
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stage = EXCEPTION;
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}
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}
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}
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@ -6,13 +6,15 @@ import java.util.*;
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// Java emulation core implementation
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class JavaVUE extends VUE {
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// State fields
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int breakCode; // Application break code
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byte[] wram; // System WRAM
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// Package fields
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int breakCode; // Application break code
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CPU cpu; // Processor
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OnException onException; // Exception callback handler
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OnExecute onExecute; // Execute callback handler
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OnRead onRead; // Read callback handler
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OnWrite onWrite; // Write callback handler
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GamePak pak; // Game pak
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byte[] wram; // System WRAM
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@ -53,13 +55,19 @@ class JavaVUE extends VUE {
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do {
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// Determine the number of cycles during which nothing will happen
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int cycles = maxCycles;
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//cycles = cpu .until(cycles);
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int cycles = -1;
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//cycles = pad .until(cycles);
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//cycles = link .until(cycles);
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//cycles = timer.until(cycles);
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//cycles = vip .until(cycles);
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//cycles = vsu .until(cycles);
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cycles = cpu .until(cycles);
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// Range checking
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if (cycles == -1) // No activity on any component
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break;
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if (maxCycles >= 0) // Restrict to given number of cycles
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cycles = Math.min(cycles, maxCycles);
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// Process all system components
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breakCode = 0;
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@ -68,7 +76,7 @@ class JavaVUE extends VUE {
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//timer.emulate(cycles);
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//vip .emulate(cycles);
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//vsu .emulate(cycles);
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//cpu .emulate(cycles);
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cpu .emulate(cycles);
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// An application break was requested
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if (breakCode != 0)
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@ -80,7 +88,12 @@ class JavaVUE extends VUE {
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} while (maxCycles != 0);
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// A break condition has occurred
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return maxCycles;
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return Math.max(0, maxCycles);
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}
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// Retrieve the application break code
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public int getBreakCode() {
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return breakCode;
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}
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// Retrieve a register value
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@ -293,7 +306,7 @@ class JavaVUE extends VUE {
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// Write a value to a byte buffer
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static void writeBuffer(byte[] data, int address, int type, int value) {
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// Error checking
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// The destination does not exist
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if (data == null)
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return;
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@ -89,6 +89,13 @@ JNIEXPORT jint JNICALL Java_vue_NativeVUE_emulate
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return vueEmulate(&core->vue, maxCycles);
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}
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// Retrieve the application break code
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JNIEXPORT jint JNICALL Java_vue_NativeVUE_getRegister
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(JNIEnv *env, jobject vue) {
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CORE *core = GetCore(env, vue);
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return vueGetBreakCode(&core->vue);
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}
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// Retrieve a register value
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JNIEXPORT jint JNICALL Java_vue_NativeVUE_getRegister
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(JNIEnv *env, jobject vue, jint index, jboolean system) {
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@ -29,6 +29,9 @@ class NativeVUE extends VUE {
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// Process the simulation
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public native int emulate(int maxCycles);
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// Retrieve the application break code
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public native int getBreakCode();
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// Retrieve a register value
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public native int getRegister(int index, boolean system);
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@ -8,6 +8,17 @@ public abstract class VUE {
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///////////////////////////////////////////////////////////////////////////
|
||||
// Types //
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
|
||||
public interface OnException { int call(VUE vue, int code ); }
|
||||
public interface OnExecute { int call(VUE vue, Instruction inst ); }
|
||||
public interface OnRead { int call(VUE vue, Access access); }
|
||||
public interface OnWrite { int call(VUE vue, Access access); }
|
||||
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
// Constants //
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
|
|
@ -161,6 +172,9 @@ public abstract class VUE {
|
|||
// Process the simulation
|
||||
public abstract int emulate(int maxCycles);
|
||||
|
||||
// Retrieve the application break code
|
||||
public abstract int getBreakCode();
|
||||
|
||||
// Retrieve a register value
|
||||
public abstract int getRegister(int index, boolean system);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue