122 lines
3.6 KiB
C
122 lines
3.6 KiB
C
/* This file is included into vb.c and cannot be compiled on its own. */
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#ifdef VBAPI
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/********************************* Constants *********************************/
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/* Instruction IDs */
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#define CPU_ILLEGAL -1
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#define CPU_ADD_IMM 0
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#define CPU_ADD_REG 1
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#define CPU_ADDF_S 2
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#define CPU_ADDI 3
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#define CPU_AND 4
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#define CPU_ANDBSU 5
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#define CPU_ANDI 6
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#define CPU_ANDNBSU 7
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#define CPU_BCOND 8
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#define CPU_CAXI 9
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#define CPU_CLI 10
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#define CPU_CMP_IMM 11
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#define CPU_CMP_REG 12
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#define CPU_CMPF_S 13
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#define CPU_CVT_SW 14
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#define CPU_CVT_WS 15
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#define CPU_DIV 16
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#define CPU_DIVF_S 17
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#define CPU_DIVU 18
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#define CPU_HALT 19
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#define CPU_IN_B 20
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#define CPU_IN_H 21
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#define CPU_IN_W 22
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#define CPU_JAL 23
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#define CPU_JMP 24
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#define CPU_JR 25
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#define CPU_LD_B 26
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#define CPU_LD_H 27
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#define CPU_LD_W 28
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#define CPU_LDSR 29
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#define CPU_MOV_IMM 30
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#define CPU_MOV_REG 31
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#define CPU_MOVBSU 32
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#define CPU_MOVEA 33
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#define CPU_MOVHI 34
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#define CPU_MPYHW 35
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#define CPU_MUL 36
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#define CPU_MULF_S 37
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#define CPU_MULU 38
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#define CPU_NOT 39
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#define CPU_NOTBSU 40
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#define CPU_OR 41
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#define CPU_ORBSU 42
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#define CPU_ORI 43
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#define CPU_ORNBSU 44
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#define CPU_OUT_B 45
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#define CPU_OUT_H 46
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#define CPU_OUT_W 47
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#define CPU_RETI 48
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#define CPU_REV 49
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#define CPU_SAR_IMM 50
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#define CPU_SAR_REG 51
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#define CPU_SCH0BSD 52
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#define CPU_SCH0BSU 53
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#define CPU_SCH1BSD 54
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#define CPU_SCH1BSU 55
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#define CPU_SEI 56
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#define CPU_SETF 57
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#define CPU_SHL_IMM 58
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#define CPU_SHL_REG 59
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#define CPU_SHR_IMM 60
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#define CPU_SHR_REG 61
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#define CPU_ST_B 62
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#define CPU_ST_H 63
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#define CPU_ST_W 64
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#define CPU_STSR 65
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#define CPU_SUB 66
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#define CPU_SUBF_S 67
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#define CPU_TRAP 68
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#define CPU_TRNC_SW 69
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#define CPU_XB 70
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#define CPU_XH 71
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#define CPU_XOR 72
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#define CPU_XORBSU 73
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#define CPU_XORI 74
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#define CPU_XORNBSU 75
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#define CPU_BITSTRING 76
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#define CPU_FLOATENDO 77
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/* Mapping for bit string sub-opcodes */
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static const int8_t CPU_BITSTRINGS[] = {
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CPU_SCH0BSU, CPU_SCH0BSD, CPU_SCH1BSU, CPU_SCH1BSD,
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CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL,
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CPU_ORBSU , CPU_ANDBSU , CPU_XORBSU , CPU_MOVBSU ,
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CPU_ORNBSU , CPU_ANDNBSU, CPU_XORNBSU, CPU_NOTBSU ,
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CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL,
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CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL,
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CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL,
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CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL
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};
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/* Mapping for floating-point/Nintendo sub-opcodes */
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static const int8_t CPU_FLOATENDO[] = {
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CPU_CMPF_S , CPU_ILLEGAL, CPU_CVT_WS , CPU_CVT_SW ,
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CPU_ADDF_S , CPU_SUBF_S , CPU_MULF_S , CPU_DIVF_S ,
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CPU_XB , CPU_XH , CPU_REV , CPU_TRNC_SW,
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CPU_MPYHW , CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL,
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CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL,
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CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL,
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CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL,
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CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL,
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CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL,
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CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL,
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CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL,
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CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL,
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CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL,
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CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL,
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CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL,
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CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL, CPU_ILLEGAL
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};
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#endif /* VBAPI */
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