Introduce pseudo-halt
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+133
-95
@@ -10,97 +10,86 @@
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#define CPU_HALTING 1
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#define CPU_FATAL 2
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#define CPU_FETCH 3
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#define CPU_ILLEGAL 4
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#define CPU_BITSTRING 5
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#define CPU_FLOATENDO 6
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#define CPU_ADD_IMM 7
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#define CPU_ADD_REG 8
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#define CPU_ADDF_S 9
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#define CPU_ADDI 10
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#define CPU_AND 11
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#define CPU_ANDI 12
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#define CPU_BCOND 13
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#define CPU_CAXI 14
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#define CPU_CLI 15
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#define CPU_CMP_IMM 16
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#define CPU_CMP_REG 17
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#define CPU_CMPF_S 18
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#define CPU_CVT_SW 19
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#define CPU_CVT_WS 20
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#define CPU_DIV 21
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#define CPU_DIVF_S 22
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#define CPU_DIVU 23
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#define CPU_HALT 24
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#define CPU_IN_B 25
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#define CPU_IN_H 26
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#define CPU_IN_W 27
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#define CPU_JAL 28
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#define CPU_JMP 29
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#define CPU_JR 30
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#define CPU_LD_B 31
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#define CPU_LD_H 32
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#define CPU_LD_W 33
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#define CPU_LDSR 34
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#define CPU_MOV_IMM 35
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#define CPU_MOV_REG 36
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#define CPU_MOVEA 37
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#define CPU_MOVHI 38
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#define CPU_MPYHW 39
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#define CPU_MUL 40
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#define CPU_MULF_S 41
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#define CPU_MULU 42
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#define CPU_NOT 43
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#define CPU_OR 44
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#define CPU_ORI 45
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#define CPU_OUT_B 46
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#define CPU_OUT_H 47
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#define CPU_OUT_W 48
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#define CPU_RETI 49
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#define CPU_REV 50
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#define CPU_SAR_IMM 51
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#define CPU_SAR_REG 52
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#define CPU_SCH0BSD 53
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#define CPU_SCH0BSU 54
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#define CPU_SCH1BSD 55
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#define CPU_SCH1BSU 56
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#define CPU_SEI 57
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#define CPU_SETF 58
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#define CPU_SHL_IMM 59
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#define CPU_SHL_REG 60
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#define CPU_SHR_IMM 61
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#define CPU_SHR_REG 62
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#define CPU_ST_B 63
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#define CPU_ST_H 64
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#define CPU_ST_W 65
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#define CPU_STSR 66
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#define CPU_SUB 67
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#define CPU_SUBF_S 68
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#define CPU_TRAP 69
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#define CPU_TRNC_SW 70
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#define CPU_XB 71
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#define CPU_XH 72
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#define CPU_XOR 73
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#define CPU_XORI 74
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#define CPU_ANDBSU 75 /* Keep bit string ALU commands sequential */
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#define CPU_ANDNBSU 76
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#define CPU_MOVBSU 77
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#define CPU_NOTBSU 78
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#define CPU_ORBSU 79
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#define CPU_ORNBSU 80
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#define CPU_XORBSU 81
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#define CPU_XORNBSU 82
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/* Abstract operand types */
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#define CPU_IMP(x) -x-1
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#define CPU_DISP9 1
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#define CPU_DISP26 2
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#define CPU_IMM16S 3
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#define CPU_IMM16U 4
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#define CPU_IMM5S 5
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#define CPU_IMM5U 6
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#define CPU_MEM 7
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#define CPU_REG1 8
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#define CPU_REG2 9
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#define CPU_PHALT 4
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#define CPU_ILLEGAL 5
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#define CPU_BITSTRING 6
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#define CPU_FLOATENDO 7
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#define CPU_ADD_IMM 8
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#define CPU_ADD_REG 9
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#define CPU_ADDF_S 10
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#define CPU_ADDI 11
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#define CPU_AND 12
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#define CPU_ANDI 13
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#define CPU_BCOND 14
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#define CPU_CAXI 15
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#define CPU_CLI 16
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#define CPU_CMP_IMM 17
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#define CPU_CMP_REG 18
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#define CPU_CMPF_S 19
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#define CPU_CVT_SW 20
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#define CPU_CVT_WS 21
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#define CPU_DIV 22
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#define CPU_DIVF_S 23
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#define CPU_DIVU 24
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#define CPU_HALT 25
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#define CPU_IN_B 26
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#define CPU_IN_H 27
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#define CPU_IN_W 28
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#define CPU_JAL 29
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#define CPU_JMP 30
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#define CPU_JR 31
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#define CPU_LD_B 32
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#define CPU_LD_H 33
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#define CPU_LD_W 34
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#define CPU_LDSR 35
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#define CPU_MOV_IMM 36
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#define CPU_MOV_REG 37
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#define CPU_MOVEA 38
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#define CPU_MOVHI 39
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#define CPU_MPYHW 40
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#define CPU_MUL 41
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#define CPU_MULF_S 42
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#define CPU_MULU 43
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#define CPU_NOT 44
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#define CPU_OR 45
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#define CPU_ORI 46
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#define CPU_OUT_B 47
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#define CPU_OUT_H 48
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#define CPU_OUT_W 49
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#define CPU_RETI 50
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#define CPU_REV 51
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#define CPU_SAR_IMM 52
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#define CPU_SAR_REG 53
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#define CPU_SCH0BSD 54
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#define CPU_SCH0BSU 55
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#define CPU_SCH1BSD 56
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#define CPU_SCH1BSU 57
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#define CPU_SEI 58
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#define CPU_SETF 59
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#define CPU_SHL_IMM 60
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#define CPU_SHL_REG 61
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#define CPU_SHR_IMM 62
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#define CPU_SHR_REG 63
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#define CPU_ST_B 64
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#define CPU_ST_H 65
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#define CPU_ST_W 66
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#define CPU_STSR 67
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#define CPU_SUB 68
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#define CPU_SUBF_S 69
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#define CPU_TRAP 70
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#define CPU_TRNC_SW 71
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#define CPU_XB 72
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#define CPU_XH 73
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#define CPU_XOR 74
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#define CPU_XORI 75
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#define CPU_ANDBSU 76 /* Keep bit string ALU IDs consecutive */
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#define CPU_ANDNBSU 77
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#define CPU_MOVBSU 78
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#define CPU_NOTBSU 79
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#define CPU_ORBSU 80
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#define CPU_ORNBSU 81
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#define CPU_XORBSU 82
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#define CPU_XORNBSU 83
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/* Functional operand types */
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#define CPU_LITERAL 0
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@@ -206,6 +195,13 @@ static const uint8_t OPDEFS_FLOATENDO[] = {
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/**************************** Forward references *****************************/
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static int phAssess (VB *, uint32_t, int, int32_t);
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static uint32_t phUntil (VB *);
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/***************************** Callback Handlers *****************************/
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/* Prepare to handle an exception */
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@@ -248,6 +244,10 @@ static int cpuRead(VB *sim, uint32_t address, int type, int32_t *value) {
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/* Retrieve the value from the simulation state directly */
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busRead(sim, address, type, value);
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/* Check for pseudo-halt */
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if (sim->ph.enabled && phAssess(sim, address, type, *value))
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return 0;
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/* Invoke the callback if available */
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if (
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sim->onRead != NULL &&
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@@ -296,6 +296,10 @@ static int cpuWrite(VB *sim, uint32_t address, int type, int32_t value) {
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int cancel = 0;
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uint32_t cycles = 3; /* TODO: Research this */
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/* Reset pseudo-halt */
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if (sim->ph.enabled)
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sim->ph.step = 0;
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/* Invoke the callback if available */
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if (
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sim->onWrite != NULL &&
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@@ -482,10 +486,13 @@ static int cpuException(VB *sim) {
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/* Interrupts only */
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if ((cause & 0xFF00) == 0xFE00) {
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sim->cpu.psw.i = (cause >> 4 & 7) + 1;
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/* HALT instruction */
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if (sim->cpu.halt) {
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sim->cpu.halt = 0;
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sim->cpu.pc += 2;
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}
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}
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/* All exceptions */
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@@ -583,6 +590,30 @@ static int cpuHalt(VB *sim) {
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return !cpuIRQ(sim);
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}
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/* Pseudo-halt is pending */
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static int cpuPHalt(VB *sim) {
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int32_t value; /* Value read from memory */
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/* An interrupt will be accepted */
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if (cpuIRQ(sim)) {
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sim->ph.step = 0;
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return 0;
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}
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/* Monitor value has not changed */
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busRead(sim, sim->ph.address, sim->ph.type, &value);
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if (value == sim->ph.value) {
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sim->cpu.clocks = phUntil(sim);
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return 1;
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}
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/* Release pseudo-halt */
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sim->cpu.operation = CPU_FETCH;
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sim->cpu.step = 0;
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sim->ph.step = 0;
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return 0;
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}
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/**************************** Instruction Helpers ****************************/
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@@ -1699,10 +1730,11 @@ static int cpuEmulate(VB *sim, uint32_t clocks) {
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/* Processing by operation ID */
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switch (sim->cpu.operation) {
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case CPU_EXCEPTION: brk = cpuException(sim); break;
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case CPU_EXCEPTION: brk = cpuException(sim); break;
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case CPU_FATAL : return 0;
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case CPU_FETCH : brk = cpuFetch (sim); break;
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case CPU_HALTING : if (cpuHalt(sim)) return 0; break;
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case CPU_FETCH : brk = cpuFetch (sim); break;
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case CPU_HALTING : if (cpuHalt (sim)) return 0; break;
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case CPU_PHALT : if (cpuPHalt(sim)) return 0; break;
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case CPU_ADD_IMM: cpuADDImm (sim); break;
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case CPU_ADD_REG: cpuADDReg (sim); break;
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@@ -1826,8 +1858,14 @@ static void cpuReset(VB *sim) {
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/* Determine how many clocks are guaranteed to process */
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static uint32_t cpuUntil(VB *sim, uint32_t clocks) {
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/* Pseudo-halting */
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if (sim->cpu.operation == CPU_PHALT) {
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if (!sim->ph.operation)
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return clocks;
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}
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/* Halting */
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if (sim->cpu.halt) {
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else if (sim->cpu.halt) {
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return
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sim->cpu.operation == CPU_HALTING &&
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!(sim->cpu.psw.id | sim->cpu.psw.ep | sim->cpu.psw.np) &&
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