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Fix double CPU clocks in reads/writes, assuage unused argument in vsuWrite()

This commit is contained in:
Guy Perfect 2025-08-24 11:03:51 -05:00
parent fe9c5c4781
commit 8598eab087
2 changed files with 3 additions and 2 deletions
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4
core/cpu.c
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@ -234,7 +234,7 @@ static int cpuOnExecute(VB *sim) {
#define VB_ON_READ VB_DIRECT_READ #define VB_ON_READ VB_DIRECT_READ
#endif #endif
static int cpuRead(VB *sim, uint32_t address, int type, int32_t *value) { static int cpuRead(VB *sim, uint32_t address, int type, int32_t *value) {
uint32_t cycles = 4; /* TODO: Research this */ uint32_t cycles = 0; /* TODO: Research this */
/* Retrieve the value from the simulation state directly */ /* Retrieve the value from the simulation state directly */
busRead(sim, address, type, value); busRead(sim, address, type, value);
@ -289,7 +289,7 @@ static int cpuReadFetch(VB *sim, int fetch, uint32_t address, int32_t *value) {
#endif #endif
static int cpuWrite(VB *sim, uint32_t address, int type, int32_t value) { static int cpuWrite(VB *sim, uint32_t address, int type, int32_t value) {
int cancel = 0; int cancel = 0;
uint32_t cycles = 3; /* TODO: Research this */ uint32_t cycles = 0; /* TODO: Research this */
/* Reset pseudo-halt */ /* Reset pseudo-halt */
if (sim->ph.enabled) if (sim->ph.enabled)

1
core/vsu.c
View File

@ -548,6 +548,7 @@ static void vsuReset(VB *sim) {
/* Write a typed value to the VSU bus */ /* Write a typed value to the VSU bus */
static void vsuWrite(VB*sim,uint32_t address,int type,int32_t value,int debug){ static void vsuWrite(VB*sim,uint32_t address,int type,int32_t value,int debug){
(void) type;
/* Unmapped */ /* Unmapped */
if (address & 1) if (address & 1)