Overplane and sweep fixes
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+13
-7
@@ -164,7 +164,7 @@ static void vsuEmulateChannel(VB *sim, int index, uint32_t clocks) {
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if (!chan->int_.enb)
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return;
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sim->vsu.freqmod.clocks = (uint32_t) sim->vsu.freqmod.interval *
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(sim->vsu.freqmod.clk == 0 ? 19201 : 153610);
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(sim->vsu.freqmod.clk == 0 ? 19200 : 153600);
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}
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} while (clocks != 0);
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@@ -207,6 +207,8 @@ static void vsuWriteEV0(VB *sim, int index, uint8_t value) {
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chan->env.interval = value & 7;
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chan->env.value = value >> 4 & 15;
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chan->env.reload = chan->env.value;
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if (index == 4)
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vsuNextFreqMod(sim, chan);
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/* Configure state */
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chan->env.clocks = 307220 * ((uint32_t) chan->env.interval + 1);
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@@ -243,6 +245,8 @@ static void vsuWriteFQH(VB *sim, int index, uint16_t value) {
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value = value << 8 & 0x0700;
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chan->freq.current = (chan->freq.current & 0x00FF) | value;
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chan->freq.written = (chan->freq.written & 0x00FF) | value;
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if (index == 4)
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vsuNextFreqMod(sim, chan);
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}
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/* Write a value to S*FQL */
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@@ -250,6 +254,8 @@ static void vsuWriteFQL(VB *sim, int index, uint8_t value) {
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Channel *chan = &sim->vsu.channels[index];
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chan->freq.current = (chan->freq.current & 0x0700) | value;
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chan->freq.written = (chan->freq.written & 0x0700) | value;
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if (index == 4)
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vsuNextFreqMod(sim, chan);
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}
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/* Write a value to S*INT */
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@@ -274,7 +280,7 @@ static void vsuWriteINT(VB *sim, int index, uint8_t value) {
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}
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if (index == 4) {
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sim->vsu.freqmod.clocks = (uint32_t) sim->vsu.freqmod.interval *
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(sim->vsu.freqmod.clk ? 153610 : 19201);
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(sim->vsu.freqmod.clk == 0 ? 19200 : 153600);
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sim->vsu.freqmod.sample = 0;
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}
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@@ -297,14 +303,14 @@ static void vsuWriteSWP(VB *sim, uint8_t value) {
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uint32_t clocks;
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/* Parse fields */
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sim->vsu.freqmod.clk = value >> 7 & 1;
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sim->vsu.freqmod.dir = value >> 3 & 1;
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sim->vsu.freqmod.interval = value >> 4 & 15;
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sim->vsu.freqmod.shift = value & 7;
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sim->vsu.freqmod.clk = value >> 7 & 1;
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sim->vsu.freqmod.dir = value >> 3 & 1;
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sim->vsu.freqmod.interval = value >> 4 & 7;
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sim->vsu.freqmod.shift = value & 7;
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/* Configure state */
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clocks = (uint32_t) sim->vsu.freqmod.interval *
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(sim->vsu.freqmod.clk ? 153610 : 19201);
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(sim->vsu.freqmod.clk == 0 ? 19200 : 153600);
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if (clocks < sim->vsu.freqmod.clocks)
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sim->vsu.freqmod.clocks = clocks;
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}
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