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Pseudo-halt timing fix

This commit is contained in:
Guy Perfect 2024-10-23 21:16:35 -05:00
parent 0c914fce1a
commit bcd80d291b
3 changed files with 20 additions and 8 deletions
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2
core/cpu.c
View File

@ -1860,7 +1860,7 @@ static uint32_t cpuUntil(VB *sim, uint32_t clocks) {
/* Pseudo-halting */
if (sim->cpu.operation == CPU_PHALT) {
if (sim->cpu.clocks == 0) /* Requires an interrupt */
if (sim->cpu.clocks == 0)
return clocks;
}

4
core/pseudo-halt.c
View File

@ -121,11 +121,12 @@ static int phMatches(VB *sim, uint32_t address, int type, int32_t value) {
return
sim->ph.adtre == sim->cpu.adtre &&
sim->ph.chcw == cpuGetSystemRegister(sim, VB_CHCW) &&
sim->ph.ecr == cpuGetSystemRegister(sim, VB_ECR) &&
sim->ph.eipc == sim->cpu.eipc &&
sim->ph.eipsw == sim->cpu.eipsw &&
sim->ph.fepc == sim->cpu.fepc &&
sim->ph.fepsw == sim->cpu.fepsw &&
sim->ph.psw == cpuGetSystemRegister(sim, VB_PSW)
sim->ph.psw == cpuGetSystemRegister(sim, VB_PSW )
;
}
@ -229,6 +230,7 @@ static int phAssess(VB *sim, uint32_t address, int type, int32_t value) {
sim->ph.program[x - 1] = sim->cpu.program[x];
sim->ph.adtre = sim->cpu.adtre;
sim->ph.chcw = cpuGetSystemRegister(sim, VB_CHCW);
sim->ph.ecr = cpuGetSystemRegister(sim, VB_ECR);
sim->ph.eipc = sim->cpu.eipc;
sim->ph.eipsw = sim->cpu.eipsw;
sim->ph.fepc = sim->cpu.fepc;

22
core/vb.c
View File

@ -322,6 +322,7 @@ struct VB {
/* CPU snapshot */
uint32_t adtre;
uint32_t chcw;
uint32_t ecr;
uint32_t eipc;
uint32_t eipsw;
uint32_t fepc;
@ -381,12 +382,21 @@ static int32_t SignExtend(int32_t value, int32_t bits) {
/* Process a simulation for a given number of clocks */
static int sysEmulate(VB *sim, uint32_t clocks) {
int ret;
ret = cpuEmulate(sim, clocks);
padEmulate(sim, clocks);
tmrEmulate(sim, clocks);
vsuEmulate(sim, clocks);
ret |= vipEmulate(sim, clocks);
int ret = 0;
/* CPU is in a pseudo-halt state that requires an interrupt to exit */
int never =
sim->cpu.operation == CPU_PHALT &&
sim->ph.operation == PH_NEVER
;
/* Process all components */
if (!never) ret = cpuEmulate(sim, clocks);
padEmulate(sim, clocks);
tmrEmulate(sim, clocks);
vsuEmulate(sim, clocks);
ret |= vipEmulate(sim, clocks);
if ( never) ret |= cpuEmulate(sim, clocks);
return ret;
}