PVB/shrooms-vb-core
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Implement game pad and timer

Browse Source
This commit is contained in:
GuyPerfect
2024-10-19 20:35:56 -05:00
parent 37b9a94338
commit e9f5437c1f
6 changed files with 386 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files
core/bus.c
+69 -6
View File
@@ -16,6 +16,13 @@ static const uint32_t TYPE_MASKS[] = {
/**************************** Forward references *****************************/
static void vipRead (VB *, uint32_t, int, int32_t *);
static void vipWrite(VB *, uint32_t, int, int32_t, int);
/*************************** Sub-Module Functions ****************************/
/* Read a typed value from a buffer in host memory */
@@ -76,14 +83,62 @@ static void busWriteBuffer(uint8_t *data, int type, int32_t value) {
}
/* Read a value from miscellaneous hardware I/O */
static int32_t busReadMisc(VB *sim, uint8_t address, int type) {
/* Unmapped */
switch (type) {
case VB_S8 : case VB_U8 : if (address & 3) return 0; break;
case VB_S16: case VB_U16: if (address & 1) return 0;
}
/* Access by register */
switch (address >> 2 & 15) {
case 0x00>>2: break; /* CCR */
case 0x04>>2: break; /* CCSR */
case 0x08>>2: break; /* CDTR */
case 0x0C>>2: break; /* CDRR */
case 0x10>>2: return sim->pad.sdlr; /* SDLR */
case 0x14>>2: return sim->pad.sdhr; /* SDHR */
case 0x18>>2: return sim->tmr.counter & 0xFF; /* TLR */
case 0x1C>>2: return sim->tmr.counter >> 8 & 0xFF; /* THR */
case 0x20>>2: return tmrReadControl(sim); /* TCR */
case 0x24>>2: return sim->wcr; /* WCR */
case 0x28>>2: return padReadControl(sim); /* SCR */
}
/* Unmapped */
return 0;
}
/* Write a value to miscellaneous hardware I/O */
static void busWriteMisc(VB *sim, uint8_t address, int type, int32_t value) {
/* Unmapped */
switch (type) {
case VB_S8 : case VB_U8 : if (address & 3) return; break;
case VB_S16: case VB_U16: if (address & 1) return;
}
/* Access by register */
switch (address >> 2 & 15) {
case 0x00>>2: break; /* CCR */
case 0x04>>2: break; /* CCSR */
case 0x08>>2: break; /* CDTR */
case 0x0C>>2: break; /* CDRR */
case 0x18>>2: tmrWriteLow (sim, value); break; /* TLR */
case 0x1C>>2: tmrWriteHigh (sim, value); break; /* THR */
case 0x20>>2: tmrWriteControl(sim, value); break; /* TCR */
case 0x24>>2: sim->wcr = value & 3; break; /* WCR */
case 0x28>>2: padWriteControl(sim, value); break; /* SCR */
}
}
/***************************** Library Functions *****************************/
/* Forward references */
static void vipRead (VB *, uint32_t, int, int32_t *);
static void vipWrite(VB *, uint32_t, int, int32_t, int);
/* Read a typed value from the simulation bus */
static void busRead(VB *sim, uint32_t address, int type, int32_t *value) {
@@ -99,7 +154,11 @@ static void busRead(VB *sim, uint32_t address, int type, int32_t *value) {
break;
case 1: break; /* VSU */
case 2: break; /* Misc. I/O */
case 2: /* Misc. I/O */
*value = busReadMisc(sim, address, type);
break;
case 3: break; /* Unmapped */
case 4: break; /* Game Pak expansion */
@@ -139,7 +198,11 @@ static void busWrite(VB*sim,uint32_t address,int type,int32_t value,int debug){
break;
case 1: break; /* VSU */
case 2: break; /* Misc. I/O */
case 2: /* Misc. I/O */
busWriteMisc(sim, address, type, value);
break;
case 3: break; /* Unmapped */
case 4: break; /* Game Pak expansion */