Compare commits
9
Commits
| Author | SHA1 | Date | |
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06849b54ba | ||
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eef255b507 | ||
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db966c8cb8 | ||
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b4feff41f0 | ||
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4449acada0 | ||
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799ac9f51a | ||
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b83b49221d | ||
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27e926bd58 | ||
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d802d39d8d |
@@ -1637,6 +1637,7 @@ static void cpuSUBF_S(VB *sim) {
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/* TRAP */
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/* TRAP */
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static void cpuTRAP(VB *sim) {
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static void cpuTRAP(VB *sim) {
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sim->cpu.clocks += cpuClocks(15);
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sim->cpu.clocks += cpuClocks(15);
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sim->cpu.pc += 2;
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cpuThrow(sim, 0xFFA0 + cpuGetImm5U(sim));
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cpuThrow(sim, 0xFFA0 + cpuGetImm5U(sim));
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}
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}
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+41
-14
@@ -5,6 +5,15 @@
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/***************************** Module Functions ******************************/
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/***************************** Module Functions ******************************/
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/* Compute clocks until the next decrement to zero */
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static uint32_t tmrGetUntil(VB *sim) {
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uint32_t fullTick = sim->tmr.t_clk_sel ? 400 : 2000;
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uint32_t thisTick = sim->tmr.clocks +
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(sim->tmr.t_clk_sel ? 0 : 400 * (4 - sim->tmr.tick20));
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return thisTick + fullTick *
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(sim->tmr.counter == 0 ? sim->tmr.reload : sim->tmr.counter - 1);
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}
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/* Update the counter to a new value */
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/* Update the counter to a new value */
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static void tmrUpdate(VB *sim, uint16_t value) {
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static void tmrUpdate(VB *sim, uint16_t value) {
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if (value == 0 && sim->tmr.counter != 0) {
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if (value == 0 && sim->tmr.counter != 0) {
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@@ -23,10 +32,6 @@ static void tmrUpdate(VB *sim, uint16_t value) {
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/* Process component */
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/* Process component */
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static void tmrEmulate(VB *sim, uint32_t clocks) {
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static void tmrEmulate(VB *sim, uint32_t clocks) {
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/* Timer is disabled */
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if (!sim->tmr.t_enb)
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return;
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/* Process all clocks */
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/* Process all clocks */
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for (;;) {
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for (;;) {
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@@ -38,15 +43,22 @@ static void tmrEmulate(VB *sim, uint32_t clocks) {
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}
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}
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/* Advance forward the component's number of clocks */
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/* Advance forward the component's number of clocks */
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clocks -= sim->tmr.clocks;
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clocks -= sim->tmr.clocks;
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sim->tmr.until -= sim->tmr.clocks;
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sim->tmr.until -= sim->tmr.clocks;
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sim->tmr.clocks = sim->tmr.t_clk_sel ? 400 : 2000;
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sim->tmr.clocks = 400;
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sim->tmr.tick20 += sim->tmr.tick20 == 4 ? -4 : 1;
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/* Do not decrement counter */
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if (
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!sim->tmr.t_enb ||
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(!sim->tmr.t_clk_sel && sim->tmr.tick20 != 0)
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) continue;
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/* Advance to the next counter value */
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/* Advance to the next counter value */
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tmrUpdate(sim, sim->tmr.counter == 0 ?
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tmrUpdate(sim, sim->tmr.counter == 0 ?
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sim->tmr.reload : sim->tmr.counter - 1);
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sim->tmr.reload : sim->tmr.counter - 1);
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if (sim->tmr.counter == 0)
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if (sim->tmr.counter == 0)
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sim->tmr.until = sim->tmr.clocks * ((uint32_t)sim->tmr.reload + 1);
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sim->tmr.until = tmrGetUntil(sim);
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}
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}
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}
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}
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@@ -71,8 +83,10 @@ static void tmrReset(VB *sim) {
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sim->tmr.z_stat = 0;
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sim->tmr.z_stat = 0;
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/* Other */
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/* Other */
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sim->tmr.clocks = 400;
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sim->tmr.counter = 0xFFFF;
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sim->tmr.counter = 0xFFFF;
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sim->tmr.reload = 0x0000;
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sim->tmr.reload = 0x0000;
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sim->tmr.tick20 = 0;
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}
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}
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/* Determine how many clocks are guaranteed to process */
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/* Determine how many clocks are guaranteed to process */
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@@ -88,14 +102,27 @@ static void tmrWriteControl(VB *sim, uint8_t value) {
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if (
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if (
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(value & 0x04) && /* Z-Stat-Clr */
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(value & 0x04) && /* Z-Stat-Clr */
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(
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(
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sim->tmr.counter != 0 ||
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!sim->tmr.t_enb ||
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!sim->tmr.t_enb
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(
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sim->tmr.counter != 0 &&
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!(value & 0x01) /* T-Enb */
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)
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)
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)
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) {
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) {
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sim->tmr.z_stat = sim->tmr.counter != 0;
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sim->tmr.z_stat = sim->tmr.counter != 0;
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sim->cpu.irq &= ~0x0002;
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sim->cpu.irq &= ~0x0002;
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}
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}
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/* Hardware bug: decrement on switch to 20us mode */
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if (
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!sim->tmr.t_clk_sel &&
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(value & 0x10) && /* T-Clk-Sel */
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sim->tmr.tick20 != 0
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) {
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tmrUpdate(sim, sim->tmr.counter == 0 ?
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sim->tmr.reload : sim->tmr.counter - 1);
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}
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/* Parse fields */
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/* Parse fields */
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sim->tmr.t_clk_sel = value >> 4 & 1;
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sim->tmr.t_clk_sel = value >> 4 & 1;
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sim->tmr.tim_z_int = value >> 3 & 1;
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sim->tmr.tim_z_int = value >> 3 & 1;
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@@ -105,10 +132,8 @@ static void tmrWriteControl(VB *sim, uint8_t value) {
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if (!sim->tmr.tim_z_int)
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if (!sim->tmr.tim_z_int)
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sim->cpu.irq &= ~0x0002;
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sim->cpu.irq &= ~0x0002;
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/* Configure countdowns */
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/* Configure state */
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sim->tmr.clocks = sim->tmr.t_clk_sel ? 400 : 2000;
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sim->tmr.until = tmrGetUntil(sim);
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sim->tmr.until = sim->tmr.clocks * (sim->tmr.counter == 0 ?
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(uint32_t) sim->tmr.reload + 1 : sim->tmr.counter);
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/* TODO: Will Z-Stat raise an interrupt when Tim-Z-Int is set? */
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/* TODO: Will Z-Stat raise an interrupt when Tim-Z-Int is set? */
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}
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}
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@@ -117,12 +142,14 @@ static void tmrWriteControl(VB *sim, uint8_t value) {
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static void tmrWriteHigh(VB *sim, uint8_t value) {
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static void tmrWriteHigh(VB *sim, uint8_t value) {
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sim->tmr.reload = (uint16_t) value << 8 | (sim->tmr.reload & 0x00FF);
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sim->tmr.reload = (uint16_t) value << 8 | (sim->tmr.reload & 0x00FF);
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tmrUpdate(sim, sim->tmr.reload);
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tmrUpdate(sim, sim->tmr.reload);
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sim->tmr.until = tmrGetUntil(sim);
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}
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}
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/* Write to the low data register */
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/* Write to the low data register */
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static void tmrWriteLow(VB *sim, uint8_t value) {
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static void tmrWriteLow(VB *sim, uint8_t value) {
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sim->tmr.reload = (sim->tmr.reload & 0xFF00) | value;
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sim->tmr.reload = (sim->tmr.reload & 0xFF00) | value;
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tmrUpdate(sim, sim->tmr.reload);
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tmrUpdate(sim, sim->tmr.reload);
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sim->tmr.until = tmrGetUntil(sim);
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}
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}
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@@ -251,6 +251,7 @@ struct VB {
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uint32_t clocks; /* Master clocks to wait */
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uint32_t clocks; /* Master clocks to wait */
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uint16_t counter; /* Current counter value */
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uint16_t counter; /* Current counter value */
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uint16_t reload; /* Reload counter value */
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uint16_t reload; /* Reload counter value */
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uint8_t tick20; /* Current 20-microsecond tick */
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uint32_t until; /* Clocks until interrupt condition */
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uint32_t until; /* Clocks until interrupt condition */
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} tmr;
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} tmr;
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+9
-7
@@ -234,7 +234,7 @@ static void vipWriteCell(VB *sim, uint32_t offset, int type, int32_t value) {
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case VB_S8:
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case VB_S8:
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case VB_U8:
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case VB_U8:
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value = offset & 1 ?
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value = offset & 1 ?
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value << 8 | sim->vip.ram[0x20000 | offset] :
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value << 8 | sim->vip.ram[0x20001 ^ offset] :
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value | (int32_t) sim->vip.ram[0x20001 | offset] << 8
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value | (int32_t) sim->vip.ram[0x20001 | offset] << 8
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;
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;
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break;
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break;
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@@ -284,7 +284,7 @@ static void vipWriteObject(VB *sim, uint32_t offset, int type, int32_t value) {
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case VB_S8:
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case VB_S8:
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case VB_U8:
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case VB_U8:
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value = offset & 1 ?
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value = offset & 1 ?
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value << 8 | sim->vip.ram[0x3E000 | offset] :
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value << 8 | sim->vip.ram[0x3E001 ^ offset] :
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value | (int32_t) sim->vip.ram[0x3E001 | offset] << 8
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value | (int32_t) sim->vip.ram[0x3E001 | offset] << 8
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;
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;
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break;
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break;
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@@ -326,7 +326,7 @@ static void vipWriteWorld(VB *sim, uint32_t offset, int type, int32_t value) {
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case VB_S8:
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case VB_S8:
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case VB_U8:
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case VB_U8:
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value = offset & 1 ?
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value = offset & 1 ?
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value << 8 | sim->vip.ram[0x3D800 | offset] :
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value << 8 | sim->vip.ram[0x3D801 ^ offset] :
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value | (int32_t) sim->vip.ram[0x3D801 | offset] << 8
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value | (int32_t) sim->vip.ram[0x3D801 | offset] << 8
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;
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;
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break;
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break;
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@@ -481,10 +481,12 @@ static void vipWriteIO(
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break;
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break;
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case 0x5F830>>1: /* CTA */
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case 0x5F830>>1: /* CTA */
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if ((mask & 0xFF00) == 0)
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if (debug) {
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sim->vip.cta.cta_r = value >> 8;
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if ((mask & 0xFF00) == 0)
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if ((mask & 0x00FF) == 0)
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sim->vip.cta.cta_r = value >> 8;
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sim->vip.cta.cta_l = value;
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if ((mask & 0x00FF) == 0)
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sim->vip.cta.cta_l = value;
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}
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break;
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break;
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case 0x5F842>>1: /* XPCTRL */
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case 0x5F842>>1: /* XPCTRL */
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@@ -513,6 +513,8 @@ static int dasmLine(VB *sim, uint32_t *address, uint32_t pc,
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line->isPC = *address == pc;
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line->isPC = *address == pc;
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for (x = 0; x < line->codeLength; x++)
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for (x = 0; x < line->codeLength; x++)
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line->code[x] = vbRead(sim, *address + x, VB_U8);
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line->code[x] = vbRead(sim, *address + x, VB_U8);
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/* Advance to the next instruction or PC, whichever is sooner */
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*address += pc != *address && pc - *address < line->codeLength ?
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*address += pc != *address && pc - *address < line->codeLength ?
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pc - *address : line->codeLength;
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pc - *address : line->codeLength;
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@@ -657,6 +659,8 @@ static VBU_DasmLine* dasmDisassemble(VB *sim, uint32_t address,
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size = vbuCodeSize(sim, addr);
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size = vbuCodeSize(sim, addr);
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if (address - addr < size)
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if (address - addr < size)
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break;
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break;
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/* Advance to the next instruction or PC, whichever is sooner */
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addr += addr != pc && pc - addr < size ? pc - addr : size;
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addr += addr != pc && pc - addr < size ? pc - addr : size;
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}
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}
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+14
-7
@@ -87,11 +87,8 @@ new class Core {
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this.sims.set(sim.pointer, sim);
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this.sims.set(sim.pointer, sim);
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// Video
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// Video
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sim.pixels = this.#noalloc(
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sim.pixels = this.#getPixels(sim);
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this.GetExtPixels(sim.pointer),
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sim.image = new ImageData(sim.pixels, 384, 224);
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384*224*4, sim, "pixels", Uint8ClampedArray
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);
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sim.image = new ImageData(sim.pixels, 384, 224);
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// Audio
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// Audio
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sim.samples = this.#noalloc(
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sim.samples = this.#noalloc(
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@@ -364,8 +361,10 @@ new class Core {
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this.mallocs.set(buffer.pointer, buffer);
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this.mallocs.set(buffer.pointer, buffer);
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this.#updateTarget(buffer);
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this.#updateTarget(buffer);
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}
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}
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for (let sim of this.sims)
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for (let sim of this.sims.values()) {
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sim.image = new ImageData(sim.pixels, 384, 224);
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sim.pixels = this.#getPixels(sim);
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sim.image = new ImageData(sim.pixels, 384, 224);
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}
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}
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}
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@@ -436,6 +435,14 @@ new class Core {
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this.Realloc(buffer.pointer, 0);
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this.Realloc(buffer.pointer, 0);
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}
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}
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// Register a sim's pixel buffer
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#getPixels(sim) {
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return this.#noalloc(
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this.GetExtPixels(sim.pointer),
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384*224*4, sim, "pixels", Uint8ClampedArray
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);
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}
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// Allocate memory in WebAssembly and register the buffer
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// Allocate memory in WebAssembly and register the buffer
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#malloc(count, target = null, assign = null, type = Uint8ClampedArray) {
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#malloc(count, target = null, assign = null, type = Uint8ClampedArray) {
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return this.#noalloc(
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return this.#noalloc(
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Reference in New Issue
Block a user