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7 Commits
Author SHA1 Message Date
GuyPerfect b4feff41f0 Fix broken timer fix bug fixes 2024-12-26 13:23:56 -06:00
GuyPerfect 4449acada0 Fix timer clock computation 2024-12-26 12:57:44 -06:00
GuyPerfect 799ac9f51a Fix style check error 2024-12-26 12:28:10 -06:00
GuyPerfect b83b49221d Timer accuracy adjustments 2024-12-26 12:23:00 -06:00
GuyPerfect 27e926bd58 Fix byte writes to VIP cells, objects and worlds 2024-12-25 13:48:39 -06:00
GuyPerfect d802d39d8d Prevent non-debug writes to CTA 2024-12-23 09:56:54 -06:00
GuyPerfect 18b2c589e6 Add vbuCodeSize() 2024-11-21 18:50:31 -06:00
6 changed files with 71 additions and 34 deletions
+41 -14
View File
@@ -5,6 +5,15 @@
/***************************** Module Functions ******************************/ /***************************** Module Functions ******************************/
/* Compute clocks until the next decrement to zero */
static uint32_t tmrGetUntil(VB *sim) {
uint32_t fullTick = sim->tmr.t_clk_sel ? 400 : 2000;
uint32_t thisTick = sim->tmr.clocks +
(sim->tmr.t_clk_sel ? 0 : 400 * (4 - sim->tmr.tick20));
return thisTick + fullTick *
(sim->tmr.counter == 0 ? sim->tmr.reload : sim->tmr.counter - 1);
}
/* Update the counter to a new value */ /* Update the counter to a new value */
static void tmrUpdate(VB *sim, uint16_t value) { static void tmrUpdate(VB *sim, uint16_t value) {
if (value == 0 && sim->tmr.counter != 0) { if (value == 0 && sim->tmr.counter != 0) {
@@ -23,10 +32,6 @@ static void tmrUpdate(VB *sim, uint16_t value) {
/* Process component */ /* Process component */
static void tmrEmulate(VB *sim, uint32_t clocks) { static void tmrEmulate(VB *sim, uint32_t clocks) {
/* Timer is disabled */
if (!sim->tmr.t_enb)
return;
/* Process all clocks */ /* Process all clocks */
for (;;) { for (;;) {
@@ -38,15 +43,22 @@ static void tmrEmulate(VB *sim, uint32_t clocks) {
} }
/* Advance forward the component's number of clocks */ /* Advance forward the component's number of clocks */
clocks -= sim->tmr.clocks; clocks -= sim->tmr.clocks;
sim->tmr.until -= sim->tmr.clocks; sim->tmr.until -= sim->tmr.clocks;
sim->tmr.clocks = sim->tmr.t_clk_sel ? 400 : 2000; sim->tmr.clocks = 400;
sim->tmr.tick20 += sim->tmr.tick20 == 4 ? -4 : 1;
/* Do not decrement counter */
if (
!sim->tmr.t_enb ||
(!sim->tmr.t_clk_sel && sim->tmr.tick20 != 0)
) continue;
/* Advance to the next counter value */ /* Advance to the next counter value */
tmrUpdate(sim, sim->tmr.counter == 0 ? tmrUpdate(sim, sim->tmr.counter == 0 ?
sim->tmr.reload : sim->tmr.counter - 1); sim->tmr.reload : sim->tmr.counter - 1);
if (sim->tmr.counter == 0) if (sim->tmr.counter == 0)
sim->tmr.until = sim->tmr.clocks * ((uint32_t)sim->tmr.reload + 1); sim->tmr.until = tmrGetUntil(sim);
} }
} }
@@ -71,8 +83,10 @@ static void tmrReset(VB *sim) {
sim->tmr.z_stat = 0; sim->tmr.z_stat = 0;
/* Other */ /* Other */
sim->tmr.clocks = 400;
sim->tmr.counter = 0xFFFF; sim->tmr.counter = 0xFFFF;
sim->tmr.reload = 0x0000; sim->tmr.reload = 0x0000;
sim->tmr.tick20 = 0;
} }
/* Determine how many clocks are guaranteed to process */ /* Determine how many clocks are guaranteed to process */
@@ -88,14 +102,27 @@ static void tmrWriteControl(VB *sim, uint8_t value) {
if ( if (
(value & 0x04) && /* Z-Stat-Clr */ (value & 0x04) && /* Z-Stat-Clr */
( (
sim->tmr.counter != 0 || !sim->tmr.t_enb ||
!sim->tmr.t_enb (
sim->tmr.counter != 0 &&
!(value & 0x01) /* T-Enb */
)
) )
) { ) {
sim->tmr.z_stat = sim->tmr.counter != 0; sim->tmr.z_stat = sim->tmr.counter != 0;
sim->cpu.irq &= ~0x0002; sim->cpu.irq &= ~0x0002;
} }
/* Hardware bug: decrement on switch to 20us mode */
if (
!sim->tmr.t_clk_sel &&
(value & 0x10) && /* T-Clk-Sel */
sim->tmr.tick20 != 4
) {
tmrUpdate(sim, sim->tmr.counter == 0 ?
sim->tmr.reload : sim->tmr.counter - 1);
}
/* Parse fields */ /* Parse fields */
sim->tmr.t_clk_sel = value >> 4 & 1; sim->tmr.t_clk_sel = value >> 4 & 1;
sim->tmr.tim_z_int = value >> 3 & 1; sim->tmr.tim_z_int = value >> 3 & 1;
@@ -105,10 +132,8 @@ static void tmrWriteControl(VB *sim, uint8_t value) {
if (!sim->tmr.tim_z_int) if (!sim->tmr.tim_z_int)
sim->cpu.irq &= ~0x0002; sim->cpu.irq &= ~0x0002;
/* Configure countdowns */ /* Configure state */
sim->tmr.clocks = sim->tmr.t_clk_sel ? 400 : 2000; sim->tmr.until = tmrGetUntil(sim);
sim->tmr.until = sim->tmr.clocks * (sim->tmr.counter == 0 ?
(uint32_t) sim->tmr.reload + 1 : sim->tmr.counter);
/* TODO: Will Z-Stat raise an interrupt when Tim-Z-Int is set? */ /* TODO: Will Z-Stat raise an interrupt when Tim-Z-Int is set? */
} }
@@ -117,12 +142,14 @@ static void tmrWriteControl(VB *sim, uint8_t value) {
static void tmrWriteHigh(VB *sim, uint8_t value) { static void tmrWriteHigh(VB *sim, uint8_t value) {
sim->tmr.reload = (uint16_t) value << 8 | (sim->tmr.reload & 0x00FF); sim->tmr.reload = (uint16_t) value << 8 | (sim->tmr.reload & 0x00FF);
tmrUpdate(sim, sim->tmr.reload); tmrUpdate(sim, sim->tmr.reload);
sim->tmr.until = tmrGetUntil(sim);
} }
/* Write to the low data register */ /* Write to the low data register */
static void tmrWriteLow(VB *sim, uint8_t value) { static void tmrWriteLow(VB *sim, uint8_t value) {
sim->tmr.reload = (sim->tmr.reload & 0xFF00) | value; sim->tmr.reload = (sim->tmr.reload & 0xFF00) | value;
tmrUpdate(sim, sim->tmr.reload); tmrUpdate(sim, sim->tmr.reload);
sim->tmr.until = tmrGetUntil(sim);
} }
+1
View File
@@ -251,6 +251,7 @@ struct VB {
uint32_t clocks; /* Master clocks to wait */ uint32_t clocks; /* Master clocks to wait */
uint16_t counter; /* Current counter value */ uint16_t counter; /* Current counter value */
uint16_t reload; /* Reload counter value */ uint16_t reload; /* Reload counter value */
uint8_t tick20; /* Current 20-microsecond tick */
uint32_t until; /* Clocks until interrupt condition */ uint32_t until; /* Clocks until interrupt condition */
} tmr; } tmr;
+14 -10
View File
@@ -234,7 +234,7 @@ static void vipWriteCell(VB *sim, uint32_t offset, int type, int32_t value) {
case VB_S8: case VB_S8:
case VB_U8: case VB_U8:
value = offset & 1 ? value = offset & 1 ?
value << 8 | sim->vip.ram[0x20000 | offset] : value << 8 | sim->vip.ram[0x20001 ^ offset] :
value | (int32_t) sim->vip.ram[0x20001 | offset] << 8 value | (int32_t) sim->vip.ram[0x20001 | offset] << 8
; ;
break; break;
@@ -284,7 +284,7 @@ static void vipWriteObject(VB *sim, uint32_t offset, int type, int32_t value) {
case VB_S8: case VB_S8:
case VB_U8: case VB_U8:
value = offset & 1 ? value = offset & 1 ?
value << 8 | sim->vip.ram[0x3E000 | offset] : value << 8 | sim->vip.ram[0x3E001 ^ offset] :
value | (int32_t) sim->vip.ram[0x3E001 | offset] << 8 value | (int32_t) sim->vip.ram[0x3E001 | offset] << 8
; ;
break; break;
@@ -326,7 +326,7 @@ static void vipWriteWorld(VB *sim, uint32_t offset, int type, int32_t value) {
case VB_S8: case VB_S8:
case VB_U8: case VB_U8:
value = offset & 1 ? value = offset & 1 ?
value << 8 | sim->vip.ram[0x3D800 | offset] : value << 8 | sim->vip.ram[0x3D801 ^ offset] :
value | (int32_t) sim->vip.ram[0x3D801 | offset] << 8 value | (int32_t) sim->vip.ram[0x3D801 | offset] << 8
; ;
break; break;
@@ -481,10 +481,12 @@ static void vipWriteIO(
break; break;
case 0x5F830>>1: /* CTA */ case 0x5F830>>1: /* CTA */
if ((mask & 0xFF00) == 0) if (debug) {
sim->vip.cta.cta_r = value >> 8; if ((mask & 0xFF00) == 0)
if ((mask & 0x00FF) == 0) sim->vip.cta.cta_r = value >> 8;
sim->vip.cta.cta_l = value; if ((mask & 0x00FF) == 0)
sim->vip.cta.cta_l = value;
}
break; break;
case 0x5F842>>1: /* XPCTRL */ case 0x5F842>>1: /* XPCTRL */
@@ -1085,11 +1087,13 @@ static void vipDrawAffine(VB *sim, World *world) {
pixel = cell->pixels[(py & 7) << 3 | (px & 7)]; pixel = cell->pixels[(py & 7) << 3 | (px & 7)];
if (pixel != 0) if (pixel != 0)
*col = cell->palette[pixel]; *col = cell->palette[pixel];
}
} } /* x */
} /* y */
} /* i */
}
} }
/* Draw an object group into shadow memory */ /* Draw an object group into shadow memory */
+8 -10
View File
@@ -1,4 +1,4 @@
/* This file is included into vb.c and cannot be compiled on its own. */ /* This file is included into vbu.c and cannot be compiled on its own. */
#ifdef VBUAPI #ifdef VBUAPI
@@ -449,12 +449,6 @@ static VBU_DasmLine* dasmGrow(
return *lines == NULL ? NULL : &(*lines)[index]; return *lines == NULL ? NULL : &(*lines)[index];
} }
/* Determine the size of an instruction */
static uint32_t dasmInstSize(VB *sim, uint32_t address) {
unsigned opcode = vbRead(sim, address, VB_U16) >> 10 & 63;
return opcode < 0x20 || opcode == 0x32 || opcode == 0x36 ? 2 : 4;
}
/* Format an operand */ /* Format an operand */
static void dasmOperand(char *dest, VBU_DasmConfig *config, static void dasmOperand(char *dest, VBU_DasmConfig *config,
VBU_DasmLine *line, uint8_t type) { VBU_DasmLine *line, uint8_t type) {
@@ -515,10 +509,12 @@ static int dasmLine(VB *sim, uint32_t *address, uint32_t pc,
/* Process non-text members */ /* Process non-text members */
line = &(*lines)[index]; line = &(*lines)[index];
line->address = *address; line->address = *address;
line->codeLength = dasmInstSize(sim, *address); line->codeLength = vbuCodeSize(sim, *address);
line->isPC = *address == pc; line->isPC = *address == pc;
for (x = 0; x < line->codeLength; x++) for (x = 0; x < line->codeLength; x++)
line->code[x] = vbRead(sim, *address + x, VB_U8); line->code[x] = vbRead(sim, *address + x, VB_U8);
/* Advance to the next instruction or PC, whichever is sooner */
*address += pc != *address && pc - *address < line->codeLength ? *address += pc != *address && pc - *address < line->codeLength ?
pc - *address : line->codeLength; pc - *address : line->codeLength;
@@ -660,9 +656,11 @@ static VBU_DasmLine* dasmDisassemble(VB *sim, uint32_t address,
} }
/* Check if the instruction contains the reference address */ /* Check if the instruction contains the reference address */
size = dasmInstSize(sim, addr); size = vbuCodeSize(sim, addr);
if (address - addr < size) if (address - addr < size)
break; break;
/* Advance to the next instruction or PC, whichever is sooner */
addr += addr != pc && pc - addr < size ? pc - addr : size; addr += addr != pc && pc - addr < size ? pc - addr : size;
} }
@@ -674,7 +672,7 @@ static VBU_DasmLine* dasmDisassemble(VB *sim, uint32_t address,
/* Keep decoding until the first line of output */ /* Keep decoding until the first line of output */
else for (; line < 0; line++) else for (; line < 0; line++)
addr += dasmInstSize(sim, addr); addr += vbuCodeSize(sim, addr);
/* Working variables */ /* Working variables */
size = length * sizeof (VBU_DasmLine); size = length * sizeof (VBU_DasmLine);
+6
View File
@@ -38,6 +38,12 @@ static int32_t SignExtend(int32_t value, int32_t bits) {
/******************************* API Commands ********************************/ /******************************* API Commands ********************************/
/* Determine the size in bytes of an instruction */
VBUAPI int vbuCodeSize(VB *sim, uint32_t address) {
int opcode = vbRead(sim, address, VB_U16) >> 10 & 63;
return opcode < 0x20 || opcode == 0x32 || opcode == 0x36 ? 2 : 4;
}
/* Initialize disassembler options with default settings */ /* Initialize disassembler options with default settings */
VBUAPI VBU_DasmConfig* vbuDasmInit(VBU_DasmConfig *config) { VBUAPI VBU_DasmConfig* vbuDasmInit(VBU_DasmConfig *config) {
config->bcondNotation = VBU_JOINED; config->bcondNotation = VBU_JOINED;
+1
View File
@@ -85,6 +85,7 @@ typedef struct {
/******************************* API Commands ********************************/ /******************************* API Commands ********************************/
VBUAPI int vbuCodeSize (VB *sim, uint32_t address);
VBUAPI VBU_DasmConfig* vbuDasmInit (VBU_DasmConfig *config); VBUAPI VBU_DasmConfig* vbuDasmInit (VBU_DasmConfig *config);
VBUAPI VBU_DasmLine* vbuDisassemble(VB *sim, uint32_t address, VBU_DasmConfig *config, unsigned length, int line); VBUAPI VBU_DasmLine* vbuDisassemble(VB *sim, uint32_t address, VBU_DasmConfig *config, unsigned length, int line);