Compare commits

...
16 Commits
Author SHA1 Message Date
GuyPerfect 06849b54ba Fix TRAP restore PC, but better 2024-12-29 09:52:07 -06:00
GuyPerfect eef255b507 Fix TRAP restore PC 2024-12-29 09:22:14 -06:00
GuyPerfect db966c8cb8 Fix memory growth handling 2024-12-26 14:13:13 -06:00
GuyPerfect b4feff41f0 Fix broken timer fix bug fixes 2024-12-26 13:23:56 -06:00
GuyPerfect 4449acada0 Fix timer clock computation 2024-12-26 12:57:44 -06:00
GuyPerfect 799ac9f51a Fix style check error 2024-12-26 12:28:10 -06:00
GuyPerfect b83b49221d Timer accuracy adjustments 2024-12-26 12:23:00 -06:00
GuyPerfect 27e926bd58 Fix byte writes to VIP cells, objects and worlds 2024-12-25 13:48:39 -06:00
GuyPerfect d802d39d8d Prevent non-debug writes to CTA 2024-12-23 09:56:54 -06:00
GuyPerfect 18b2c589e6 Add vbuCodeSize() 2024-11-21 18:50:31 -06:00
GuyPerfect f45636a491 VIP bugfix 2024-11-19 22:22:34 -06:00
GuyPerfect 9ce8c9c778 VIP bugfix 2024-11-19 22:21:06 -06:00
GuyPerfect c90b8137de VIP optimizations 2024-11-19 21:56:44 -06:00
GuyPerfect bc864644f7 Aid VSU performance 2024-11-17 14:57:56 -06:00
GuyPerfect e97b52e944 Cleanup adjustments 2024-11-17 12:31:37 -06:00
GuyPerfect 7e31fbd582 VSU performance tweak, add immediate notation setting 2024-11-11 20:05:14 -06:00
12 changed files with 862 additions and 461 deletions
+1 -5
View File
@@ -91,11 +91,6 @@
#define CPU_XORBSU 82 #define CPU_XORBSU 82
#define CPU_XORNBSU 83 #define CPU_XORNBSU 83
/* Functional operand types */
#define CPU_LITERAL 0
#define CPU_MEMORY 1
#define CPU_REGISTER 2
/* Bit string operations */ /* Bit string operations */
#define CPU_AND_BS 0 #define CPU_AND_BS 0
#define CPU_ANDN_BS 1 #define CPU_ANDN_BS 1
@@ -1642,6 +1637,7 @@ static void cpuSUBF_S(VB *sim) {
/* TRAP */ /* TRAP */
static void cpuTRAP(VB *sim) { static void cpuTRAP(VB *sim) {
sim->cpu.clocks += cpuClocks(15); sim->cpu.clocks += cpuClocks(15);
sim->cpu.pc += 2;
cpuThrow(sim, 0xFFA0 + cpuGetImm5U(sim)); cpuThrow(sim, 0xFFA0 + cpuGetImm5U(sim));
} }
+39 -12
View File
@@ -5,6 +5,15 @@
/***************************** Module Functions ******************************/ /***************************** Module Functions ******************************/
/* Compute clocks until the next decrement to zero */
static uint32_t tmrGetUntil(VB *sim) {
uint32_t fullTick = sim->tmr.t_clk_sel ? 400 : 2000;
uint32_t thisTick = sim->tmr.clocks +
(sim->tmr.t_clk_sel ? 0 : 400 * (4 - sim->tmr.tick20));
return thisTick + fullTick *
(sim->tmr.counter == 0 ? sim->tmr.reload : sim->tmr.counter - 1);
}
/* Update the counter to a new value */ /* Update the counter to a new value */
static void tmrUpdate(VB *sim, uint16_t value) { static void tmrUpdate(VB *sim, uint16_t value) {
if (value == 0 && sim->tmr.counter != 0) { if (value == 0 && sim->tmr.counter != 0) {
@@ -23,10 +32,6 @@ static void tmrUpdate(VB *sim, uint16_t value) {
/* Process component */ /* Process component */
static void tmrEmulate(VB *sim, uint32_t clocks) { static void tmrEmulate(VB *sim, uint32_t clocks) {
/* Timer is disabled */
if (!sim->tmr.t_enb)
return;
/* Process all clocks */ /* Process all clocks */
for (;;) { for (;;) {
@@ -40,13 +45,20 @@ static void tmrEmulate(VB *sim, uint32_t clocks) {
/* Advance forward the component's number of clocks */ /* Advance forward the component's number of clocks */
clocks -= sim->tmr.clocks; clocks -= sim->tmr.clocks;
sim->tmr.until -= sim->tmr.clocks; sim->tmr.until -= sim->tmr.clocks;
sim->tmr.clocks = sim->tmr.t_clk_sel ? 400 : 2000; sim->tmr.clocks = 400;
sim->tmr.tick20 += sim->tmr.tick20 == 4 ? -4 : 1;
/* Do not decrement counter */
if (
!sim->tmr.t_enb ||
(!sim->tmr.t_clk_sel && sim->tmr.tick20 != 0)
) continue;
/* Advance to the next counter value */ /* Advance to the next counter value */
tmrUpdate(sim, sim->tmr.counter == 0 ? tmrUpdate(sim, sim->tmr.counter == 0 ?
sim->tmr.reload : sim->tmr.counter - 1); sim->tmr.reload : sim->tmr.counter - 1);
if (sim->tmr.counter == 0) if (sim->tmr.counter == 0)
sim->tmr.until = sim->tmr.clocks * ((uint32_t)sim->tmr.reload + 1); sim->tmr.until = tmrGetUntil(sim);
} }
} }
@@ -71,8 +83,10 @@ static void tmrReset(VB *sim) {
sim->tmr.z_stat = 0; sim->tmr.z_stat = 0;
/* Other */ /* Other */
sim->tmr.clocks = 400;
sim->tmr.counter = 0xFFFF; sim->tmr.counter = 0xFFFF;
sim->tmr.reload = 0x0000; sim->tmr.reload = 0x0000;
sim->tmr.tick20 = 0;
} }
/* Determine how many clocks are guaranteed to process */ /* Determine how many clocks are guaranteed to process */
@@ -88,14 +102,27 @@ static void tmrWriteControl(VB *sim, uint8_t value) {
if ( if (
(value & 0x04) && /* Z-Stat-Clr */ (value & 0x04) && /* Z-Stat-Clr */
( (
sim->tmr.counter != 0 || !sim->tmr.t_enb ||
!sim->tmr.t_enb (
sim->tmr.counter != 0 &&
!(value & 0x01) /* T-Enb */
)
) )
) { ) {
sim->tmr.z_stat = sim->tmr.counter != 0; sim->tmr.z_stat = sim->tmr.counter != 0;
sim->cpu.irq &= ~0x0002; sim->cpu.irq &= ~0x0002;
} }
/* Hardware bug: decrement on switch to 20us mode */
if (
!sim->tmr.t_clk_sel &&
(value & 0x10) && /* T-Clk-Sel */
sim->tmr.tick20 != 0
) {
tmrUpdate(sim, sim->tmr.counter == 0 ?
sim->tmr.reload : sim->tmr.counter - 1);
}
/* Parse fields */ /* Parse fields */
sim->tmr.t_clk_sel = value >> 4 & 1; sim->tmr.t_clk_sel = value >> 4 & 1;
sim->tmr.tim_z_int = value >> 3 & 1; sim->tmr.tim_z_int = value >> 3 & 1;
@@ -105,10 +132,8 @@ static void tmrWriteControl(VB *sim, uint8_t value) {
if (!sim->tmr.tim_z_int) if (!sim->tmr.tim_z_int)
sim->cpu.irq &= ~0x0002; sim->cpu.irq &= ~0x0002;
/* Configure countdowns */ /* Configure state */
sim->tmr.clocks = sim->tmr.t_clk_sel ? 400 : 2000; sim->tmr.until = tmrGetUntil(sim);
sim->tmr.until = sim->tmr.clocks * (sim->tmr.counter == 0 ?
(uint32_t) sim->tmr.reload + 1 : sim->tmr.counter);
/* TODO: Will Z-Stat raise an interrupt when Tim-Z-Int is set? */ /* TODO: Will Z-Stat raise an interrupt when Tim-Z-Int is set? */
} }
@@ -117,12 +142,14 @@ static void tmrWriteControl(VB *sim, uint8_t value) {
static void tmrWriteHigh(VB *sim, uint8_t value) { static void tmrWriteHigh(VB *sim, uint8_t value) {
sim->tmr.reload = (uint16_t) value << 8 | (sim->tmr.reload & 0x00FF); sim->tmr.reload = (uint16_t) value << 8 | (sim->tmr.reload & 0x00FF);
tmrUpdate(sim, sim->tmr.reload); tmrUpdate(sim, sim->tmr.reload);
sim->tmr.until = tmrGetUntil(sim);
} }
/* Write to the low data register */ /* Write to the low data register */
static void tmrWriteLow(VB *sim, uint8_t value) { static void tmrWriteLow(VB *sim, uint8_t value) {
sim->tmr.reload = (sim->tmr.reload & 0xFF00) | value; sim->tmr.reload = (sim->tmr.reload & 0xFF00) | value;
tmrUpdate(sim, sim->tmr.reload); tmrUpdate(sim, sim->tmr.reload);
sim->tmr.until = tmrGetUntil(sim);
} }
+65 -4
View File
@@ -8,8 +8,11 @@
/*********************************** Types ***********************************/ /*********************************** Types ***********************************/
/* Output image */ /* VIP BG map cell */
typedef uint8_t Pixels[2][384*224]; typedef struct {
uint8_t *palette; /* Points to a VB.vip.gplt */
uint8_t *pixels; /* Points to a VB.vip.characters */
} Cell;
/* VSU channel */ /* VSU channel */
typedef struct { typedef struct {
@@ -64,9 +67,58 @@ typedef struct {
} wave; } wave;
/* Other state */ /* Other state */
uint32_t clocks; /* Clocks until next sample */ uint32_t clocks; /* Clocks until next wave or noise sample */
uint8_t freqmod; /* Frequency modifications are active */
uint32_t until; /* Clocks until channel component update */
} Channel; } Channel;
/* VIP character (hflp << 1 | vflp) */
typedef uint8_t Character[4][64];
/* VIP object */
typedef struct {
Cell cell; /* BG map-like attributes */
int16_t jp; /* Parallax */
int16_t jx; /* Screen base X */
int16_t jy; /* Screen Y */
uint8_t lron; /* Visible in left and right images */
} Object;
/* Output image */
typedef uint8_t Pixels[2][384*224];
/* VIP world */
typedef struct {
/* Attributes */
uint8_t bgm; /* Mode */
uint8_t end; /* Control world */
int16_t gp; /* World parallax */
int16_t gx; /* World base X */
int16_t gy; /* World Y */
int16_t mx; /* Scroll base X */
int16_t mp; /* Scroll parallax */
int16_t my; /* Scroll Y */
uint8_t over; /* Use overplane */
Cell *overplane; /* Overplane cell */
/* Non-attributes */
Cell *bg[64]; /* Background arrangement */
int32_t bgHeight; /* Height of background in pixels */
uint32_t bgMaskX; /* Horizontal background mask */
uint32_t bgMaskY; /* Vertical background mask */
uint32_t bgShift; /* Bits to shift when selecting a BG map */
int32_t bgWidth; /* Width of background in pixels */
uint32_t hAffine; /* H for affine mode */
uint32_t hNaffine; /* H for not affine mode */
uint32_t height; /* Height of world in pixels */
uint8_t lron; /* Visible in left and right images */
uint32_t paramBase; /* H-bias and affine parameter address */
uint32_t wAffine; /* W for affine mode */
uint32_t wNaffine; /* W for not affine mode */
uint32_t width; /* Width of world in pixels */
} World;
/* Simulation state */ /* Simulation state */
struct VB { struct VB {
@@ -199,6 +251,7 @@ struct VB {
uint32_t clocks; /* Master clocks to wait */ uint32_t clocks; /* Master clocks to wait */
uint16_t counter; /* Current counter value */ uint16_t counter; /* Current counter value */
uint16_t reload; /* Reload counter value */ uint16_t reload; /* Reload counter value */
uint8_t tick20; /* Current 20-microsecond tick */
uint32_t until; /* Clocks until interrupt condition */ uint32_t until; /* Clocks until interrupt condition */
} tmr; } tmr;
@@ -278,7 +331,11 @@ struct VB {
Pixels shadow; /* Drawing shadow image, column-major */ Pixels shadow; /* Drawing shadow image, column-major */
/* Other state */ /* Other state */
Cell cells[0x10000]; /* Pre-computed BG map attributes */
Character characters[2048]; /* Pre-computed character pixels */
Object objects[1024]; /* Pre-computed object attributes */
uint8_t ram[0x40000]; /* Video memory */ uint8_t ram[0x40000]; /* Video memory */
World worlds[32]; /* Pre-computed world attributes */
} vip; } vip;
/* VSU */ /* VSU */
@@ -643,6 +700,7 @@ VBAPI vbOnWrite vbGetWriteCallback(VB *sim) {
VBAPI VB* vbInit(VB *sim) { VBAPI VB* vbInit(VB *sim) {
sim->cart.ram = NULL; sim->cart.ram = NULL;
sim->cart.rom = NULL; sim->cart.rom = NULL;
sim->ph.enabled = 0;
sim->vsu.out.samples = NULL; sim->vsu.out.samples = NULL;
sim->onExecute = NULL; sim->onExecute = NULL;
sim->onFetch = NULL; sim->onFetch = NULL;
@@ -652,7 +710,7 @@ VBAPI VB* vbInit(VB *sim) {
sim->onSamples = NULL; sim->onSamples = NULL;
sim->onWrite = NULL; sim->onWrite = NULL;
sim->peer = NULL; sim->peer = NULL;
sim->ph.enabled = 0; sim->tag = NULL;
vbReset(sim); vbReset(sim);
return sim; return sim;
} }
@@ -774,6 +832,8 @@ VBAPI int vbSetOption(VB *sim, int key, int value) {
VBAPI void vbSetPeer(VB *sim, VB *peer) { VBAPI void vbSetPeer(VB *sim, VB *peer) {
if (sim->peer == peer) if (sim->peer == peer)
return; return;
if (sim->peer != NULL)
sim->peer->peer = NULL;
sim->peer = peer; sim->peer = peer;
if (peer == NULL) if (peer == NULL)
return; return;
@@ -784,6 +844,7 @@ VBAPI void vbSetPeer(VB *sim, VB *peer) {
/* Specify a new value for the program counter */ /* Specify a new value for the program counter */
VBAPI uint32_t vbSetProgramCounter(VB *sim, uint32_t value) { VBAPI uint32_t vbSetProgramCounter(VB *sim, uint32_t value) {
sim->cpu.clocks = 0;
sim->cpu.operation = CPU_FETCH; sim->cpu.operation = CPU_FETCH;
sim->cpu.pc = sim->cpu.nextPC = value & 0xFFFFFFFE; sim->cpu.pc = sim->cpu.nextPC = value & 0xFFFFFFFE;
sim->cpu.step = 0; sim->cpu.step = 0;
+583 -316
View File
File diff suppressed because it is too large Load Diff
+57 -50
View File
@@ -74,49 +74,8 @@ static void vsuNextFreqMod(VB *sim, Channel *chan) {
} }
/* Process one channel */ /* Process one channel */
static void vsuEmulateChannel(VB *sim, int index, uint32_t clocks) { static void vsuEmulateChannel(VB *sim, Channel *chan) {
uint32_t bit; /* Pseudorandom bit */ uint32_t bit; /* Pseudorandom bit */
Channel *chan; /* Channel handle */
int freqmod; /* Frequency modifications enabled */
uint32_t until; /* Clocks to process sub-channel components */
/* Select channel */
chan = &sim->vsu.channels[index];
/* Channel is disabled */
if (!chan->int_.enb)
return;
/* Process all clocks */
do {
/* Frequency modifications are active */
freqmod =
index == 4 && /* Channel 5 */
sim->vsu.freqmod.enb && /* Modifications enabled */
sim->vsu.freqmod.interval != 0 /* Modifications valid */
;
/* Clocks until next state change */
until = clocks;
if (chan->clocks < until)
until = chan->clocks;
if (chan->env.enb && chan->env.clocks < until)
until = chan->env.clocks;
if (chan->int_.auto_ && chan->int_.clocks < until)
until = chan->int_.clocks;
if (freqmod && sim->vsu.freqmod.clocks < until)
until = sim->vsu.freqmod.clocks;
/* Manage clocks */
clocks -= until;
chan->clocks -= until;
if (chan->env.enb)
chan->env.clocks -= until;
if (chan->int_.auto_)
chan->int_.clocks -= until;
if (freqmod)
sim->vsu.freqmod.clocks -= until;
/* Automatic shutoff */ /* Automatic shutoff */
if (chan->int_.auto_ && chan->int_.clocks == 0) { if (chan->int_.auto_ && chan->int_.clocks == 0) {
@@ -124,11 +83,11 @@ static void vsuEmulateChannel(VB *sim, int index, uint32_t clocks) {
return; return;
} }
/* Next sample */ /* Next input sample */
if (chan->clocks == 0) { if (chan->clocks == 0) {
/* Wave */ /* Wave */
if (index != 5) { if (chan != &sim->vsu.channels[5]) {
chan->clocks = 4 * (2048 - (uint32_t) chan->freq.current); chan->clocks = 4 * (2048 - (uint32_t) chan->freq.current);
chan->wave.sample = (chan->wave.sample + 1) & 31; chan->wave.sample = (chan->wave.sample + 1) & 31;
} }
@@ -158,7 +117,7 @@ static void vsuEmulateChannel(VB *sim, int index, uint32_t clocks) {
} }
/* Frequency modification */ /* Frequency modification */
if (freqmod && sim->vsu.freqmod.clocks == 0) { if (chan->freqmod && sim->vsu.freqmod.clocks == 0) {
chan->freq.current = sim->vsu.freqmod.next; chan->freq.current = sim->vsu.freqmod.next;
vsuNextFreqMod(sim, chan); vsuNextFreqMod(sim, chan);
if (!chan->int_.enb) if (!chan->int_.enb)
@@ -167,8 +126,6 @@ static void vsuEmulateChannel(VB *sim, int index, uint32_t clocks) {
(sim->vsu.freqmod.clk == 0 ? 19200 : 153600); (sim->vsu.freqmod.clk == 0 ? 19200 : 153600);
} }
} while (clocks != 0);
} }
/* Produce output for a channel */ /* Produce output for a channel */
@@ -230,6 +187,8 @@ static void vsuWriteEV1(VB *sim, int index, uint8_t value) {
sim->vsu.freqmod.func = value >> 4 & 1; sim->vsu.freqmod.func = value >> 4 & 1;
sim->vsu.freqmod.rep = value >> 5 & 1; sim->vsu.freqmod.rep = value >> 5 & 1;
vsuNextFreqMod(sim, chan); vsuNextFreqMod(sim, chan);
chan->freqmod =
sim->vsu.freqmod.enb && sim->vsu.freqmod.interval != 0;
break; break;
case 5: /* Channel 6 */ case 5: /* Channel 6 */
@@ -313,6 +272,8 @@ static void vsuWriteSWP(VB *sim, uint8_t value) {
(sim->vsu.freqmod.clk == 0 ? 19200 : 153600); (sim->vsu.freqmod.clk == 0 ? 19200 : 153600);
if (clocks < sim->vsu.freqmod.clocks) if (clocks < sim->vsu.freqmod.clocks)
sim->vsu.freqmod.clocks = clocks; sim->vsu.freqmod.clocks = clocks;
sim->vsu.channels[4].freqmod =
sim->vsu.freqmod.enb && sim->vsu.freqmod.interval != 0;
} }
@@ -321,6 +282,8 @@ static void vsuWriteSWP(VB *sim, uint8_t value) {
/* Process component */ /* Process component */
static void vsuEmulate(VB *sim, uint32_t clocks) { static void vsuEmulate(VB *sim, uint32_t clocks) {
Channel *chan; /* Input channel */
uint32_t chantil; /* Clocks until next channel state update */
float i0; /* Current analog input sample */ float i0; /* Current analog input sample */
float o0; /* Current analog output sample */ float o0; /* Current analog output sample */
uint16_t output[2]; /* Digital output samples */ uint16_t output[2]; /* Digital output samples */
@@ -340,12 +303,54 @@ static void vsuEmulate(VB *sim, uint32_t clocks) {
sim->vsu.clocks -= until; sim->vsu.clocks -= until;
/* Process all channels */ /* Process all channels */
for (x = 0; x < 6; x++) for (x = 0; x < 6; x++) {
vsuEmulateChannel(sim, x, until); chan = &sim->vsu.channels[x];
chantil = until;
/* Process all clocks */
while (chan->int_.enb && chantil != 0) {
/* Determine when the next state change will occur */
if (chan->until == 0) {
/* Clocks until next state change */
chan->until = chan->clocks;
if (chan->env.enb && chan->env.clocks < chan->until)
chan->until = chan->env.clocks;
if (chan->int_.auto_ && chan->int_.clocks < chan->until)
chan->until = chan->int_.clocks;
if (chan->freqmod && sim->vsu.freqmod.clocks < chan->until)
chan->until = sim->vsu.freqmod.clocks;
/* Manage clocks */
chan->clocks -= chan->until;
if (chan->env.enb)
chan->env.clocks -= chan->until;
if (chan->int_.auto_)
chan->int_.clocks -= chan->until;
if (chan->freqmod)
sim->vsu.freqmod.clocks -= chan->until;
}
/* Manage clocks */
if (chan->until > chantil) {
chan->until -= chantil;
chantil = 0;
} else {
chantil -= chan->until;
chan->until = 0;
}
/* Update channel state */
if (chan->until == 0)
vsuEmulateChannel(sim, chan);
}
}
/* Wait for the current sample to finish */ /* Wait for the current sample to finish */
if (sim->vsu.clocks != 0) if (sim->vsu.clocks != 0)
continue; return;
/* Compute the output sample */ /* Compute the output sample */
output[0] = output[1] = 0; output[0] = output[1] = 0;
@@ -416,6 +421,8 @@ static void vsuReset(VB *sim) {
for (x = 0; x < 6; x++) { for (x = 0; x < 6; x++) {
chan = &sim->vsu.channels[x]; chan = &sim->vsu.channels[x];
chan->clocks = 0; chan->clocks = 0;
chan->freqmod = 0;
chan->until = 0;
chan->env.clocks = 0; chan->env.clocks = 0;
chan->env.enb = 0; chan->env.enb = 0;
chan->env.dir = 0; chan->env.dir = 0;
+21 -15
View File
@@ -1,4 +1,4 @@
/* This file is included into vb.c and cannot be compiled on its own. */ /* This file is included into vbu.c and cannot be compiled on its own. */
#ifdef VBUAPI #ifdef VBUAPI
@@ -253,18 +253,24 @@ static void dasmOpDisp26(char*dest, VBU_DasmConfig*config, VBU_DasmLine*line) {
} }
/* Format a 5-bit sign-extended immediate operand */ /* Format a 5-bit sign-extended immediate operand */
static void dasmOpImm5S(char *dest, VBU_DasmLine *line) { static void dasmOpImm5S(char *dest, VBU_DasmConfig*config, VBU_DasmLine *line){
if (config->immediateNotation == VBU_NUMBER)
*dest++ = '#';
sprintf(dest, "%d", SignExtend(line->code[0], 5)); sprintf(dest, "%d", SignExtend(line->code[0], 5));
} }
/* Format a 5-bit zero-filled immediate operand */ /* Format a 5-bit zero-filled immediate operand */
static void dasmOpImm5U(char *dest, VBU_DasmLine *line) { static void dasmOpImm5U(char *dest, VBU_DasmConfig*config, VBU_DasmLine *line){
if (config->immediateNotation == VBU_NUMBER)
*dest++ = '#';
sprintf(dest, "%d", line->code[0] & 31); sprintf(dest, "%d", line->code[0] & 31);
} }
/* Format a 16-bit sign-extended immediate operand */ /* Format a 16-bit sign-extended immediate operand */
static void dasmOpImm16S(char*dest, VBU_DasmConfig*config, VBU_DasmLine*line) { static void dasmOpImm16S(char*dest, VBU_DasmConfig*config, VBU_DasmLine*line) {
int32_t imm = (int16_t) ((int16_t) line->code[3] << 8 | line->code[2]); int32_t imm = (int16_t) ((int16_t) line->code[3] << 8 | line->code[2]);
if (config->immediateNotation == VBU_NUMBER)
*dest++ = '#';
if (imm >= -256 && imm <= 256) { if (imm >= -256 && imm <= 256) {
sprintf(dest, "%d", imm); sprintf(dest, "%d", imm);
return; return;
@@ -279,6 +285,8 @@ static void dasmOpImm16S(char*dest, VBU_DasmConfig*config, VBU_DasmLine*line) {
/* Format a 16-bit zero-filled immediate operand */ /* Format a 16-bit zero-filled immediate operand */
static void dasmOpImm16U(char*dest, VBU_DasmConfig*config, VBU_DasmLine*line) { static void dasmOpImm16U(char*dest, VBU_DasmConfig*config, VBU_DasmLine*line) {
uint16_t imm = (uint16_t) line->code[3] << 8 | line->code[2]; uint16_t imm = (uint16_t) line->code[3] << 8 | line->code[2];
if (config->immediateNotation == VBU_NUMBER)
*dest++ = '#';
dasmToHex(dest, config, 4, imm); dasmToHex(dest, config, 4, imm);
} }
@@ -441,12 +449,6 @@ static VBU_DasmLine* dasmGrow(
return *lines == NULL ? NULL : &(*lines)[index]; return *lines == NULL ? NULL : &(*lines)[index];
} }
/* Determine the size of an instruction */
static uint32_t dasmInstSize(VB *sim, uint32_t address) {
unsigned opcode = vbRead(sim, address, VB_U16) >> 10 & 63;
return opcode < 0x20 || opcode == 0x32 || opcode == 0x36 ? 2 : 4;
}
/* Format an operand */ /* Format an operand */
static void dasmOperand(char *dest, VBU_DasmConfig *config, static void dasmOperand(char *dest, VBU_DasmConfig *config,
VBU_DasmLine *line, uint8_t type) { VBU_DasmLine *line, uint8_t type) {
@@ -454,8 +456,8 @@ static void dasmOperand(char *dest, VBU_DasmConfig *config,
case DASM_BCOND : dasmOpBCOND (dest, config, line); break; case DASM_BCOND : dasmOpBCOND (dest, config, line); break;
case DASM_DISP9 : dasmOpDisp9 (dest, config, line); break; case DASM_DISP9 : dasmOpDisp9 (dest, config, line); break;
case DASM_DISP26: dasmOpDisp26(dest, config, line); break; case DASM_DISP26: dasmOpDisp26(dest, config, line); break;
case DASM_IMM5S : dasmOpImm5S (dest, line); break; case DASM_IMM5S : dasmOpImm5S (dest, config, line); break;
case DASM_IMM5U : dasmOpImm5U (dest, line); break; case DASM_IMM5U : dasmOpImm5U (dest, config, line); break;
case DASM_IMM16S: dasmOpImm16S(dest, config, line); break; case DASM_IMM16S: dasmOpImm16S(dest, config, line); break;
case DASM_IMM16U: dasmOpImm16U(dest, config, line); break; case DASM_IMM16U: dasmOpImm16U(dest, config, line); break;
case DASM_JMP : dasmOpJMP (dest, config, line); break; case DASM_JMP : dasmOpJMP (dest, config, line); break;
@@ -507,10 +509,12 @@ static int dasmLine(VB *sim, uint32_t *address, uint32_t pc,
/* Process non-text members */ /* Process non-text members */
line = &(*lines)[index]; line = &(*lines)[index];
line->address = *address; line->address = *address;
line->codeLength = dasmInstSize(sim, *address); line->codeLength = vbuCodeSize(sim, *address);
line->isPC = *address == pc; line->isPC = *address == pc;
for (x = 0; x < line->codeLength; x++) for (x = 0; x < line->codeLength; x++)
line->code[x] = vbRead(sim, *address + x, VB_U8); line->code[x] = vbRead(sim, *address + x, VB_U8);
/* Advance to the next instruction or PC, whichever is sooner */
*address += pc != *address && pc - *address < line->codeLength ? *address += pc != *address && pc - *address < line->codeLength ?
pc - *address : line->codeLength; pc - *address : line->codeLength;
@@ -652,9 +656,11 @@ static VBU_DasmLine* dasmDisassemble(VB *sim, uint32_t address,
} }
/* Check if the instruction contains the reference address */ /* Check if the instruction contains the reference address */
size = dasmInstSize(sim, addr); size = vbuCodeSize(sim, addr);
if (address - addr < size) if (address - addr < size)
break; break;
/* Advance to the next instruction or PC, whichever is sooner */
addr += addr != pc && pc - addr < size ? pc - addr : size; addr += addr != pc && pc - addr < size ? pc - addr : size;
} }
@@ -666,7 +672,7 @@ static VBU_DasmLine* dasmDisassemble(VB *sim, uint32_t address,
/* Keep decoding until the first line of output */ /* Keep decoding until the first line of output */
else for (; line < 0; line++) else for (; line < 0; line++)
addr += dasmInstSize(sim, addr); addr += vbuCodeSize(sim, addr);
/* Working variables */ /* Working variables */
size = length * sizeof (VBU_DasmLine); size = length * sizeof (VBU_DasmLine);
@@ -680,7 +686,7 @@ static VBU_DasmLine* dasmDisassemble(VB *sim, uint32_t address,
if (dasmLine(sim, &addr, pc, config, &lines, &size, &offset, x)) if (dasmLine(sim, &addr, pc, config, &lines, &size, &offset, x))
goto catch; goto catch;
} }
return lines; return VBU_REALLOC(lines, offset);
/* Exception handler */ /* Exception handler */
catch: catch:
+7
View File
@@ -38,6 +38,12 @@ static int32_t SignExtend(int32_t value, int32_t bits) {
/******************************* API Commands ********************************/ /******************************* API Commands ********************************/
/* Determine the size in bytes of an instruction */
VBUAPI int vbuCodeSize(VB *sim, uint32_t address) {
int opcode = vbRead(sim, address, VB_U16) >> 10 & 63;
return opcode < 0x20 || opcode == 0x32 || opcode == 0x36 ? 2 : 4;
}
/* Initialize disassembler options with default settings */ /* Initialize disassembler options with default settings */
VBUAPI VBU_DasmConfig* vbuDasmInit(VBU_DasmConfig *config) { VBUAPI VBU_DasmConfig* vbuDasmInit(VBU_DasmConfig *config) {
config->bcondNotation = VBU_JOINED; config->bcondNotation = VBU_JOINED;
@@ -47,6 +53,7 @@ VBUAPI VBU_DasmConfig* vbuDasmInit(VBU_DasmConfig *config) {
config->conditionNotation = VBU_NAMES; config->conditionNotation = VBU_NAMES;
config->hexCase = VBU_UPPER; config->hexCase = VBU_UPPER;
config->hexNotation = VBU_0X; config->hexNotation = VBU_0X;
config->immediateNotation = VBU_NONE;
config->memoryNotation = VBU_OUTSIDE; config->memoryNotation = VBU_OUTSIDE;
config->mnemonicCase = VBU_UPPER; config->mnemonicCase = VBU_UPPER;
config->operandOrder = VBU_DEST_LAST; config->operandOrder = VBU_DEST_LAST;
+4
View File
@@ -29,6 +29,8 @@ extern "C" {
#define VBU_L 0 #define VBU_L 0
#define VBU_LOWER 1 #define VBU_LOWER 1
#define VBU_NAMES 1 #define VBU_NAMES 1
#define VBU_NONE 0
#define VBU_NUMBER 1
#define VBU_NUMBERS 0 #define VBU_NUMBERS 0
#define VBU_OUTSIDE 0 #define VBU_OUTSIDE 0
#define VBU_SPLIT 1 #define VBU_SPLIT 1
@@ -48,6 +50,7 @@ typedef struct { /* Defaults listed first */
uint8_t conditionNotation; /* NAMES, NUMBERS */ uint8_t conditionNotation; /* NAMES, NUMBERS */
uint8_t hexCase; /* UPPER, LOWER */ uint8_t hexCase; /* UPPER, LOWER */
uint8_t hexNotation; /* 0X, H, DOLLAR */ uint8_t hexNotation; /* 0X, H, DOLLAR */
uint8_t immediateNotation; /* NONE, NUMBER */
uint8_t memoryNotation; /* OUTSIDE, INSIDE */ uint8_t memoryNotation; /* OUTSIDE, INSIDE */
uint8_t mnemonicCase; /* UPPER, LOWER */ uint8_t mnemonicCase; /* UPPER, LOWER */
uint8_t operandOrder; /* DEST_LAST, DEST_FIRST */ uint8_t operandOrder; /* DEST_LAST, DEST_FIRST */
@@ -82,6 +85,7 @@ typedef struct {
/******************************* API Commands ********************************/ /******************************* API Commands ********************************/
VBUAPI int vbuCodeSize (VB *sim, uint32_t address);
VBUAPI VBU_DasmConfig* vbuDasmInit (VBU_DasmConfig *config); VBUAPI VBU_DasmConfig* vbuDasmInit (VBU_DasmConfig *config);
VBUAPI VBU_DasmLine* vbuDisassemble(VB *sim, uint32_t address, VBU_DasmConfig *config, unsigned length, int line); VBUAPI VBU_DasmLine* vbuDisassemble(VB *sim, uint32_t address, VBU_DasmConfig *config, unsigned length, int line);
+2
View File
@@ -61,6 +61,8 @@ let Constants = {
L : 0, L : 0,
LOWER : 1, LOWER : 1,
NAMES : 1, NAMES : 1,
NONE : 0,
NUMBER : 1,
NUMBERS : 0, NUMBERS : 0,
OUTSIDE : 0, OUTSIDE : 0,
SPLIT : 1, SPLIT : 1,
+13 -5
View File
@@ -87,10 +87,7 @@ new class Core {
this.sims.set(sim.pointer, sim); this.sims.set(sim.pointer, sim);
// Video // Video
sim.pixels = this.#noalloc( sim.pixels = this.#getPixels(sim);
this.GetExtPixels(sim.pointer),
384*224*4, sim, "pixels", Uint8ClampedArray
);
sim.image = new ImageData(sim.pixels, 384, 224); sim.image = new ImageData(sim.pixels, 384, 224);
// Audio // Audio
@@ -128,6 +125,7 @@ new class Core {
message.config.conditionNotation, message.config.conditionNotation,
message.config.hexCase, message.config.hexCase,
message.config.hexNotation, message.config.hexNotation,
message.config.immediateNotation,
message.config.memoryNotation, message.config.memoryNotation,
message.config.mnemonicCase, message.config.mnemonicCase,
message.config.operandOrder, message.config.operandOrder,
@@ -363,9 +361,11 @@ new class Core {
this.mallocs.set(buffer.pointer, buffer); this.mallocs.set(buffer.pointer, buffer);
this.#updateTarget(buffer); this.#updateTarget(buffer);
} }
for (let sim of this.sims) for (let sim of this.sims.values()) {
sim.pixels = this.#getPixels(sim);
sim.image = new ImageData(sim.pixels, 384, 224); sim.image = new ImageData(sim.pixels, 384, 224);
} }
}
@@ -435,6 +435,14 @@ new class Core {
this.Realloc(buffer.pointer, 0); this.Realloc(buffer.pointer, 0);
} }
// Register a sim's pixel buffer
#getPixels(sim) {
return this.#noalloc(
this.GetExtPixels(sim.pointer),
384*224*4, sim, "pixels", Uint8ClampedArray
);
}
// Allocate memory in WebAssembly and register the buffer // Allocate memory in WebAssembly and register the buffer
#malloc(count, target = null, assign = null, type = Uint8ClampedArray) { #malloc(count, target = null, assign = null, type = Uint8ClampedArray) {
return this.#noalloc( return this.#noalloc(
+15
View File
@@ -19,6 +19,7 @@ class DasmConfig {
#conditionNotation; #conditionNotation;
#hexCase; #hexCase;
#hexNotation; #hexNotation;
#immediateNotation;
#memoryNotation; #memoryNotation;
#mnemonicCase; #mnemonicCase;
#operandOrder; #operandOrder;
@@ -40,6 +41,7 @@ class DasmConfig {
this.#conditionNotation = Constants.VBU.NAMES; this.#conditionNotation = Constants.VBU.NAMES;
this.#hexCase = Constants.VBU.UPPER; this.#hexCase = Constants.VBU.UPPER;
this.#hexNotation = Constants.VBU["0X"]; this.#hexNotation = Constants.VBU["0X"];
this.#immediateNotation = Constants.VBU.NONE;
this.#memoryNotation = Constants.VBU.OUTSIDE; this.#memoryNotation = Constants.VBU.OUTSIDE;
this.#mnemonicCase = Constants.VBU.UPPER; this.#mnemonicCase = Constants.VBU.UPPER;
this.#operandOrder = Constants.VBU.DEST_LAST; this.#operandOrder = Constants.VBU.DEST_LAST;
@@ -125,6 +127,16 @@ class DasmConfig {
this.#hexNotation = value; this.#hexNotation = value;
} }
get immediateNotation() { return this.#immediateNotation; }
set immediateNotation(value) {
switch (value) {
case Constants.VBU.NONE :
case Constants.VBU.NUMBER: break;
default: return;
}
this.#immediateNotation = value;
}
get memoryNotation() { return this.#memoryNotation; } get memoryNotation() { return this.#memoryNotation; }
set memoryNotation(value) { set memoryNotation(value) {
switch (value) { switch (value) {
@@ -407,6 +419,7 @@ class Sim extends HTMLElement {
conditionNotation: config.conditionNotation, conditionNotation: config.conditionNotation,
hexCase : config.hexCase, hexCase : config.hexCase,
hexNotation : config.hexNotation, hexNotation : config.hexNotation,
immediateNotation: config.immediateNotation,
memoryNotation : config.memoryNotation, memoryNotation : config.memoryNotation,
mnemonicCase : config.mnemonicCase, mnemonicCase : config.mnemonicCase,
operandOrder : config.operandOrder, operandOrder : config.operandOrder,
@@ -650,6 +663,8 @@ class VB {
static get L () { return Constants.VBU.L ; } static get L () { return Constants.VBU.L ; }
static get LOWER () { return Constants.VBU.LOWER ; } static get LOWER () { return Constants.VBU.LOWER ; }
static get NAMES () { return Constants.VBU.NAMES ; } static get NAMES () { return Constants.VBU.NAMES ; }
static get NONE () { return Constants.VBU.NONE ; }
static get NUMBER () { return Constants.VBU.NUMBER ; }
static get NUMBERS () { return Constants.VBU.NUMBERS ; } static get NUMBERS () { return Constants.VBU.NUMBERS ; }
static get OUTSIDE () { return Constants.VBU.OUTSIDE ; } static get OUTSIDE () { return Constants.VBU.OUTSIDE ; }
static get RELATIVE () { return Constants.VBU.RELATIVE ; } static get RELATIVE () { return Constants.VBU.RELATIVE ; }
+4 -3
View File
@@ -108,9 +108,9 @@ EMSCRIPTEN_KEEPALIVE void* CreateSim() {
// Disassemble from a simulation // Disassemble from a simulation
EMSCRIPTEN_KEEPALIVE void* Disassemble( EMSCRIPTEN_KEEPALIVE void* Disassemble(
int bcondNotation, int conditionCase, int conditionCL, int conditionEZ, int bcondNotation, int conditionCase, int conditionCL, int conditionEZ,
int conditionNotation, int hexCase, int hexNotation, int memoryNotation, int conditionNotation, int hexCase, int hexNotation, int immediateNotation,
int mnemonicCase, int operandOrder, int programCase, int programNotation, int memoryNotation, int mnemonicCase, int operandOrder, int programCase,
int setfNotation, int systemCase, int systemNotation, int programNotation, int setfNotation, int systemCase, int systemNotation,
VB *sim, uint32_t address, unsigned length, int line VB *sim, uint32_t address, unsigned length, int line
) { ) {
VBU_DasmConfig config; VBU_DasmConfig config;
@@ -121,6 +121,7 @@ EMSCRIPTEN_KEEPALIVE void* Disassemble(
config.conditionNotation = conditionNotation; config.conditionNotation = conditionNotation;
config.hexCase = hexCase; config.hexCase = hexCase;
config.hexNotation = hexNotation; config.hexNotation = hexNotation;
config.immediateNotation = immediateNotation;
config.memoryNotation = memoryNotation; config.memoryNotation = memoryNotation;
config.mnemonicCase = mnemonicCase; config.mnemonicCase = mnemonicCase;
config.operandOrder = operandOrder; config.operandOrder = operandOrder;